The design of INTC controllers has significantly changed in AST2700 A1.
There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
limitation of interrupt numbers of processors, the interrupts are merged every
32 sources for interrupt numbers greater than 127.
There are two levels of interrupt controllers, INTC0 and INTC1. The interrupt
sources of INTC0 are the interrupt numbers from INTC_0 to INTC_127 and
interrupts from INTC1. The interrupt sources of INTC1 are the interrupt numbers
greater than INTC_127. INTC1 controls the interrupts INTC_128 to INTC_319 only.
Currently, only GIC 192 to 201 are supported, and their source interrupts are
from INTC1 and connected to INTC0 at input pin 0 and output pins 0 to 9 for
GIC 192-201.
To support both AST2700 A1 and A0, INTC0 input pins 1 to 9 and output pins
10 to 18 remain to support GIC 128-136, which source interrupts from INTC0.
These will be removed if we decide not to support AST2700 A0 in the future.
+---------------------------------------------------------------------------------------+
| AST2700 A1 Design |
| |
| +--------------------------+ |
| | INTC1 | +---------------+ |
| | | | orgates[0] | |
| orgates[0]+----> |inpin[0]+------->outpin[0]+------> | 0 | |
| orgates[1]|----> |inpin[1]|------->outpin[1]|------> | 1 0-31 bits +--+ |
| orgates[2]|----> |inpin[2]|------->outpin[2]|------> | 2 | | |
| orgates[3]|----> |inpin[3]|------->outpin[3]|------> | 3 | | |
| orgates[4]|----> |inpin[4]|------->outpin[4]|------> | 4 | | |
| orgates[5]+----> |inpin[5]+------->outpin[5]+------> | 5 | | |
| | | |---------------| | |
| +--------------------------+ | |
| +-----------------------------------------------------------------------| |
| | |
| | |
| | +------------------------------+ +-----------------+ |
| | | INTC0 | | GIC | |
| | |inpin[0:0]--------->outpin[0] +---------> |192 | |
| | |inpin[0:1]|-------->outpin[1] |---------> |193 | |
| | |inpin[0:2]|-------->outpin[2] |---------> |194 | |
| | |inpin[0:3]|-------->outpin[3] |---------> |195 | |
| >--------------> |inpin[0:4]|-------->outpin[4] |---------> |196 | |
| |inpin[0:5]|-------->outpin[5] |---------> |197 | |
| |inpin[0:6]|-------->outpin[6] |---------> |198 | |
| |inpin[0:7]|-------->outpin[7] |---------> |199 | |
| |inpin[0:8]|-------->outpin[8] |---------> |200 | |
| |inpin[0:9]|-------->outpin[9] |---------> |201 | |
+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------+
| orgates[1]|-----> |inpin[1]|---------->outpin[10]|---------> |128 | |
| orgates[2]|-----> |inpin[2]|---------->outpin[11]|---------> |129 | |
| orgates[3]|-----> |inpin[3]|---------->outpin[12]|---------> |130 | |
| orgates[4]|-----> |inpin[4]|---------->outpin[13]|---------> |131 | |
| orgates[5]|-----> |inpin[5]|---------->outpin[14]|---------> |132 | |
| orgates[6]|-----> |inpin[6]|---------->outpin[15]|---------> |133 | |
| orgates[7]|-----> |inpin[7]|---------->outpin[16]|---------> |134 | |
| orgates[8]|-----> |inpin[8]|---------->outpin[17]|---------> |135 | |
| orgates[9]+-----> |inpin[9]|---------->outpin[18]+---------> |136 | |
| +------------------------------+ +-----------------+ |
| |
| AST2700 A0 Design |
| |
+---------------------------------------------------------------------------------------+
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 126 +++++++++++++++++++++++++-----------
include/hw/arm/aspeed_soc.h | 3 +-
2 files changed, 92 insertions(+), 37 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index d5e521cd38..a95fed30cf 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -67,6 +67,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_RTC] = 0x12C0F000,
[ASPEED_DEV_SDHCI] = 0x14080000,
[ASPEED_DEV_TIMER1] = 0x12C10000,
+ [ASPEED_DEV_INTC1] = 0x14C18000,
};
#define AST2700_MAX_IRQ 256
@@ -119,21 +120,27 @@ static const int aspeed_soc_ast2700_irqmap[] = {
};
/* GICINT 128 */
-static const int aspeed_soc_ast2700_gic128_intcmap[] = {
+/* GICINT 192 */
+static const int ast2700_gic128_gic192_intcmap[] = {
[ASPEED_DEV_LPC] = 0,
[ASPEED_DEV_IBT] = 2,
[ASPEED_DEV_KCS] = 4,
};
+/* GICINT 129 */
+/* GICINT 193 */
+
/* GICINT 130 */
-static const int aspeed_soc_ast2700_gic130_intcmap[] = {
+/* GICINT 194 */
+static const int ast2700_gic130_gic194_intcmap[] = {
[ASPEED_DEV_I2C] = 0,
[ASPEED_DEV_ADC] = 16,
[ASPEED_DEV_GPIO] = 18,
};
/* GICINT 131 */
-static const int aspeed_soc_ast2700_gic131_intcmap[] = {
+/* GICINT 195 */
+static const int ast2700_gic131_gic195_intcmap[] = {
[ASPEED_DEV_I3C] = 0,
[ASPEED_DEV_WDT] = 16,
[ASPEED_DEV_FMC] = 25,
@@ -141,7 +148,8 @@ static const int aspeed_soc_ast2700_gic131_intcmap[] = {
};
/* GICINT 132 */
-static const int aspeed_soc_ast2700_gic132_intcmap[] = {
+/* GICINT 196 */
+static const int ast2700_gic132_gic196_intcmap[] = {
[ASPEED_DEV_ETH1] = 0,
[ASPEED_DEV_ETH2] = 1,
[ASPEED_DEV_ETH3] = 2,
@@ -160,40 +168,58 @@ static const int aspeed_soc_ast2700_gic132_intcmap[] = {
};
/* GICINT 133 */
-static const int aspeed_soc_ast2700_gic133_intcmap[] = {
+/* GICINT 197 */
+static const int ast2700_gic133_gic197_intcmap[] = {
[ASPEED_DEV_SDHCI] = 1,
[ASPEED_DEV_PECI] = 4,
};
/* GICINT 128 ~ 136 */
+/* GICINT 192 ~ 201 */
struct gic_intc_irq_info {
int irq;
+ int intc_idx;
+ int orgate_idx;
const int *ptr;
};
-static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = {
- {128, aspeed_soc_ast2700_gic128_intcmap},
- {129, NULL},
- {130, aspeed_soc_ast2700_gic130_intcmap},
- {131, aspeed_soc_ast2700_gic131_intcmap},
- {132, aspeed_soc_ast2700_gic132_intcmap},
- {133, aspeed_soc_ast2700_gic133_intcmap},
- {134, NULL},
- {135, NULL},
- {136, NULL},
+static struct gic_intc_irq_info ast2700_gic_intcmap[] = {
+ {192, 1, 0, ast2700_gic128_gic192_intcmap},
+ {193, 1, 1, NULL},
+ {194, 1, 2, ast2700_gic130_gic194_intcmap},
+ {195, 1, 3, ast2700_gic131_gic195_intcmap},
+ {196, 1, 4, ast2700_gic132_gic196_intcmap},
+ {197, 1, 5, ast2700_gic133_gic197_intcmap},
+ {198, 1, 6, NULL},
+ {199, 1, 7, NULL},
+ {200, 1, 8, NULL},
+ {201, 1, 9, NULL},
+ {128, 0, 1, ast2700_gic128_gic192_intcmap},
+ {129, 0, 2, NULL},
+ {130, 0, 3, ast2700_gic130_gic194_intcmap},
+ {131, 0, 4, ast2700_gic131_gic195_intcmap},
+ {132, 0, 5, ast2700_gic132_gic196_intcmap},
+ {133, 0, 6, ast2700_gic133_gic197_intcmap},
+ {134, 0, 7, NULL},
+ {135, 0, 8, NULL},
+ {136, 0, 9, NULL},
};
static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
{
Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int or_idx;
+ int idx;
int i;
- for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
- if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
- assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
- return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
- aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]);
+ for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
+ if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
+ assert(ast2700_gic_intcmap[i].ptr);
+ or_idx = ast2700_gic_intcmap[i].orgate_idx;
+ idx = ast2700_gic_intcmap[i].intc_idx;
+ return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
+ ast2700_gic_intcmap[i].ptr[dev]);
}
}
@@ -205,13 +231,17 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev,
{
Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int or_idx;
+ int idx;
int i;
- for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
- if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
- assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
- return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
- aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index);
+ for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
+ if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
+ assert(ast2700_gic_intcmap[i].ptr);
+ or_idx = ast2700_gic_intcmap[i].orgate_idx;
+ idx = ast2700_gic_intcmap[i].intc_idx;
+ return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
+ ast2700_gic_intcmap[i].ptr[dev] + index);
}
}
@@ -372,7 +402,8 @@ static void aspeed_soc_ast2700_init(Object *obj)
object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI);
object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO);
- object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC0);
+ object_initialize_child(obj, "intc0", &a->intc[0], TYPE_ASPEED_2700_INTC0);
+ object_initialize_child(obj, "intc1", &a->intc[1], TYPE_ASPEED_2700_INTC1);
snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
object_initialize_child(obj, "adc", &s->adc, typename);
@@ -481,7 +512,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc);
g_autofree char *sram_name = NULL;
qemu_irq irq;
@@ -511,21 +541,45 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
return;
}
- /* INTC */
- if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) {
+ /* INTC0 */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0,
sc->memmap[ASPEED_DEV_INTC0]);
- /* GICINT orgates -> INTC -> GIC */
- for (i = 0; i < ic->num_inpins; i++) {
- qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
- qdev_get_gpio_in(DEVICE(&a->intc), i));
- sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
+ /* INTC1 */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
+ return;
+ }
+
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0,
+ sc->memmap[ASPEED_DEV_INTC1]);
+
+ /* irq source orgates -> INTC0 */
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++) {
+ qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
+ qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
+ }
+ /* INTC0 -> GIC192 - GIC201 */
+ /* INTC0 -> GIC128 - GIC136 */
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_outpins; i++) {
+ assert(i < ARRAY_SIZE(ast2700_gic_intcmap));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
qdev_get_gpio_in(DEVICE(&a->gic),
- aspeed_soc_ast2700_gic_intcmap[i].irq));
+ ast2700_gic_intcmap[i].irq));
+ }
+
+ /* irq source orgates -> INTC1 */
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_inpins; i++) {
+ qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
+ qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
+ }
+ /* INTC1 -> INTC0 */
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_outpins; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
+ qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
}
/* SRAM */
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 51e585e3e4..c079225775 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -128,7 +128,7 @@ struct Aspeed27x0SoCState {
AspeedSoCState parent;
ARMCPU cpu[ASPEED_CPUS_NUM];
- AspeedINTCState intc;
+ AspeedINTCState intc[2];
GICv3State gic;
MemoryRegion dram_empty;
};
@@ -195,6 +195,7 @@ enum {
ASPEED_DEV_EHCI2,
ASPEED_DEV_VIC,
ASPEED_DEV_INTC0,
+ ASPEED_DEV_INTC1,
ASPEED_DEV_SDMC,
ASPEED_DEV_SCU,
ASPEED_DEV_ADC,
--
2.34.1On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> The design of INTC controllers has significantly changed in AST2700 A1.
>
> There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
> from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
> limitation of interrupt numbers of processors, the interrupts are merged every
> 32 sources for interrupt numbers greater than 127.
>
> There are two levels of interrupt controllers, INTC0 and INTC1. The interrupt
> sources of INTC0 are the interrupt numbers from INTC_0 to INTC_127 and
> interrupts from INTC1. The interrupt sources of INTC1 are the interrupt numbers
> greater than INTC_127. INTC1 controls the interrupts INTC_128 to INTC_319 only.
>
> Currently, only GIC 192 to 201 are supported, and their source interrupts are
> from INTC1 and connected to INTC0 at input pin 0 and output pins 0 to 9 for
> GIC 192-201.
>
> To support both AST2700 A1 and A0, INTC0 input pins 1 to 9 and output pins
> 10 to 18 remain to support GIC 128-136, which source interrupts from INTC0.
> These will be removed if we decide not to support AST2700 A0 in the future.
>
> +---------------------------------------------------------------------------------------+
> > AST2700 A1 Design |
> > |
> > +--------------------------+ |
> > | INTC1 | +---------------+ |
> > | | | orgates[0] | |
> > orgates[0]+----> |inpin[0]+------->outpin[0]+------> | 0 | |
> > orgates[1]|----> |inpin[1]|------->outpin[1]|------> | 1 0-31 bits +--+ |
> > orgates[2]|----> |inpin[2]|------->outpin[2]|------> | 2 | | |
> > orgates[3]|----> |inpin[3]|------->outpin[3]|------> | 3 | | |
> > orgates[4]|----> |inpin[4]|------->outpin[4]|------> | 4 | | |
> > orgates[5]+----> |inpin[5]+------->outpin[5]+------> | 5 | | |
> > | | |---------------| | |
> > +--------------------------+ | |
> > +-----------------------------------------------------------------------| |
> > | |
> > | |
> > | +------------------------------+ +-----------------+ |
> > | | INTC0 | | GIC | |
> > | |inpin[0:0]--------->outpin[0] +---------> |192 | |
> > | |inpin[0:1]|-------->outpin[1] |---------> |193 | |
> > | |inpin[0:2]|-------->outpin[2] |---------> |194 | |
> > | |inpin[0:3]|-------->outpin[3] |---------> |195 | |
> > >--------------> |inpin[0:4]|-------->outpin[4] |---------> |196 | |
> > |inpin[0:5]|-------->outpin[5] |---------> |197 | |
> > |inpin[0:6]|-------->outpin[6] |---------> |198 | |
> > |inpin[0:7]|-------->outpin[7] |---------> |199 | |
> > |inpin[0:8]|-------->outpin[8] |---------> |200 | |
> > |inpin[0:9]|-------->outpin[9] |---------> |201 | |
> +---------------------------------------------------------------------------------------+
> +---------------------------------------------------------------------------------------+
> > orgates[1]|-----> |inpin[1]|---------->outpin[10]|---------> |128 | |
> > orgates[2]|-----> |inpin[2]|---------->outpin[11]|---------> |129 | |
> > orgates[3]|-----> |inpin[3]|---------->outpin[12]|---------> |130 | |
> > orgates[4]|-----> |inpin[4]|---------->outpin[13]|---------> |131 | |
> > orgates[5]|-----> |inpin[5]|---------->outpin[14]|---------> |132 | |
> > orgates[6]|-----> |inpin[6]|---------->outpin[15]|---------> |133 | |
> > orgates[7]|-----> |inpin[7]|---------->outpin[16]|---------> |134 | |
> > orgates[8]|-----> |inpin[8]|---------->outpin[17]|---------> |135 | |
> > orgates[9]+-----> |inpin[9]|---------->outpin[18]+---------> |136 | |
> > +------------------------------+ +-----------------+ |
> > |
> > AST2700 A0 Design |
> > |
> +---------------------------------------------------------------------------------------+
>
Okay, so I think this is the diagram and discussion I asked for as
documentation earlier. I still prefer it doesn't just live in a commit
message, that you pull it out to a separate document that we can easily
point to and evolve.
I'm a little hazy on some of your notation in diagram though. Can you
explain your use of pipes ("|"), plusses ("+"), the "orgates" to the
left of INTC1 (what are they ORing?), and the choice of 5 lines into
the "orgates[0]" box? Also why does the "orgates[0]" arrow point where
it does on INTC0?
Andrew
Hi Andrew,
> -----Original Message-----
> From: Andrew Jeffery <andrew@codeconstruct.com.au>
> Sent: Thursday, January 30, 2025 12:20 PM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater <clg@kaod.org>;
> Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Joel Stanley
> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> list:All patches CC here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of
> INTC controllers for AST2700 A1
>
> On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> > The design of INTC controllers has significantly changed in AST2700 A1.
> >
> > There are a total of 480 interrupt sources in AST2700 A1. For
> > interrupt numbers from 0 to 127, they can route directly to PSP, SSP,
> > and TSP. Due to the limitation of interrupt numbers of processors, the
> > interrupts are merged every
> > 32 sources for interrupt numbers greater than 127.
> >
> > There are two levels of interrupt controllers, INTC0 and INTC1. The
> > interrupt sources of INTC0 are the interrupt numbers from INTC_0 to
> > INTC_127 and interrupts from INTC1. The interrupt sources of INTC1 are
> > the interrupt numbers greater than INTC_127. INTC1 controls the interrupts
> INTC_128 to INTC_319 only.
> >
> > Currently, only GIC 192 to 201 are supported, and their source
> > interrupts are from INTC1 and connected to INTC0 at input pin 0 and
> > output pins 0 to 9 for GIC 192-201.
> >
> > To support both AST2700 A1 and A0, INTC0 input pins 1 to 9 and output
> > pins
> > 10 to 18 remain to support GIC 128-136, which source interrupts from INTC0.
> > These will be removed if we decide not to support AST2700 A0 in the future.
> >
> > +---------------------------------------------------------------------------------------+
> > > AST2700 A1
> Design
> > > |
> >
> >
>
> > > |
> >
> > +--------------------------+
>
> > > |
> >
> > | INTC1 |
>
> > > +---------------+ |
> >
> > | |
> |
> > > orgates[0] | |
> > > orgates[0]+----> |inpin[0]+------->outpin[0]+------> |
> 0
> > > | |
> > > orgates[1]|----> |inpin[1]|------->outpin[1]|------> | 1 0-31
> > > bits +--+ |
> > > orgates[2]|----> |inpin[2]|------->outpin[2]|------> |
> 2
> > > | | |
> > > orgates[3]|----> |inpin[3]|------->outpin[3]|------> |
> 3
> > > | | |
> > > orgates[4]|----> |inpin[4]|------->outpin[4]|------> |
> 4
> > > | | |
> > > orgates[5]+----> |inpin[5]+------->outpin[5]+------> |
> 5
> > > | | |
> >
> > | |
>
> > > |---------------| | |
> >
> > +--------------------------+
>
> > > | |
> > >
> > > +-------------------------------------------------------------------
> > > ----| |
> >
> > |
>
> > > |
> >
> > |
>
> > > |
> > > | +------------------------------+
> > > +-----------------+ |
> >
> > | | INTC0 |
> |
> > > GIC | |
> > > | |inpin[0:0]--------->outpin[0] +--------->
> |192
> > > | |
> > > | |inpin[0:1]|-------->outpin[1] |--------->
> |193
> > > | |
> > > | |inpin[0:2]|-------->outpin[2] |--------->
> |194
> > > | |
> > > | |inpin[0:3]|-------->outpin[3] |--------->
> |195
> > > | |
> > > >--------------> |inpin[0:4]|-------->outpin[4] |--------->
> |196
> > > | |
> > > |inpin[0:5]|-------->outpin[5] |--------->
> |197
> > > | |
> > > |inpin[0:6]|-------->outpin[6] |--------->
> |198
> > > | |
> > > |inpin[0:7]|-------->outpin[7] |--------->
> |199
> > > | |
> > > |inpin[0:8]|-------->outpin[8] |--------->
> |200
> > > | |
> > > |inpin[0:9]|-------->outpin[9] |--------->
> |201
> > > | |
> > +---------------------------------------------------------------------------------------+
> > +---------------------------------------------------------------------------------------+
> > > orgates[1]|-----> |inpin[1]|---------->outpin[10]|--------->
> |128
> > > | |
> > > orgates[2]|-----> |inpin[2]|---------->outpin[11]|--------->
> |129
> > > | |
> > > orgates[3]|-----> |inpin[3]|---------->outpin[12]|--------->
> |130
> > > | |
> > > orgates[4]|-----> |inpin[4]|---------->outpin[13]|--------->
> |131
> > > | |
> > > orgates[5]|-----> |inpin[5]|---------->outpin[14]|--------->
> |132
> > > | |
> > > orgates[6]|-----> |inpin[6]|---------->outpin[15]|--------->
> |133
> > > | |
> > > orgates[7]|-----> |inpin[7]|---------->outpin[16]|--------->
> |134
> > > | |
> > > orgates[8]|-----> |inpin[8]|---------->outpin[17]|--------->
> |135
> > > | |
> > > orgates[9]+-----> |inpin[9]|---------->outpin[18]+--------->
> |136
> > > | |
> > > +------------------------------+
> > > +-----------------+ |
> >
> >
>
> > > |
> > > AST2700 A0
> Design
>
> > > |
> >
> >
>
> > > |
> > +---------------------------------------------------------------------------------------+
> >
>
> Okay, so I think this is the diagram and discussion I asked for as documentation
> earlier. I still prefer it doesn't just live in a commit message, that you pull it out
> to a separate document that we can easily point to and evolve.
>
INTC drivers owners update DTS binding document here,
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20241016022410.1154574-2-kevin_chen@aspeedtech.com/
> I'm a little hazy on some of your notation in diagram though. Can you explain
> your use of pipes ("|"), plusses ("+"), the "orgates" to the left of INTC1 (what
> are they ORing?), and the choice of 5 lines into the "orgates[0]" box? Also why
> does the "orgates[0]" arrow point where it does on INTC0?
>
I created this block diagram using the asciiflow tool and both ("I") and "("+") symbols are identical.
I will update the diagram and replace ("+") with ("|").
Sorry to make you confuse.
The design of the OR gates for GICINT 196 is as follows:
It has interrupt sources ranging from 0 to 31, with its output pin connected to INTC_IO "T0 GICINTC_192".
The output pin is then connected to INTC_CPU "GIC_192_201" at bit 0, and its bit 0 output should be connected to GIC 192.
The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as following:
Bit 0 --> GIC 192
BIT 1 -> GIC 193
BIT 2-> GIC 194
Our firmware only utilizes bits 0 to 5, so I have only illustrated bits 0 to 5 in the diagram. However, I have implemented bits 0 to 9 in the code.
Then, orgates[0] "or" the output pins of INTC_IO (To GIC192, To GIC193, To GIC194, To GIC195, To GIC196)
ETH1 +-----------+
+--------v+0 3+
ETH2 | 4|
+-------->+1 5|
ETH3 | 6|
+-------->+2 19|
UART0 | 20|
+-------->+7 21|
UART1 | 22|
+-------->+8 23|
UART2 | 24|
+-------->+9 25|
UART3 | 26|
+--------->10 27|
UART5 | 28|
+-------->+11 29|
UART6 | |
+-------->+12 30|
UART7 | 31|
+-------->+13 |
UART8 | OR[0:31] |
+--------->14 |
UART9 | |
+-------->+15 |
UART10 | |
+-------->+16 |
UART11 | |
+-------->+17 |
UART12 | |
+--------->18 |
| |
| |
| |
+-----------+
https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi#L483
https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi#L1610
Thanks-Jamin
> Andrew
On Tue, 2025-02-04 at 09:43 +0000, Jamin Lin wrote:
> Hi Andrew,
>
> > -----Original Message-----
> > From: Andrew Jeffery <andrew@codeconstruct.com.au>
> > Sent: Thursday, January 30, 2025 12:20 PM
> > To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater <clg@kaod.org>;
> > Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> > <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Joel Stanley
> > <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> > list:All patches CC here <qemu-devel@nongnu.org>
> > Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> > <yunlin.tang@aspeedtech.com>
> > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of
> > INTC controllers for AST2700 A1
> >
> > On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> > > The design of INTC controllers has significantly changed in AST2700 A1.
> > >
> > > There are a total of 480 interrupt sources in AST2700 A1. For
> > > interrupt numbers from 0 to 127, they can route directly to PSP, SSP,
> > > and TSP. Due to the limitation of interrupt numbers of processors, the
> > > interrupts are merged every
> > > 32 sources for interrupt numbers greater than 127.
> > >
> > > There are two levels of interrupt controllers, INTC0 and INTC1. The
> > > interrupt sources of INTC0 are the interrupt numbers from INTC_0 to
> > > INTC_127 and interrupts from INTC1. The interrupt sources of INTC1 are
> > > the interrupt numbers greater than INTC_127. INTC1 controls the interrupts
> > INTC_128 to INTC_319 only.
> > >
> > > Currently, only GIC 192 to 201 are supported, and their source
> > > interrupts are from INTC1 and connected to INTC0 at input pin 0 and
> > > output pins 0 to 9 for GIC 192-201.
> > >
> > > To support both AST2700 A1 and A0, INTC0 input pins 1 to 9 and output
> > > pins
> > > 10 to 18 remain to support GIC 128-136, which source interrupts from INTC0.
> > > These will be removed if we decide not to support AST2700 A0 in the future.
> > >
> > > +---------------------------------------------------------------------------------------+
> > > > AST2700 A1
> > Design
> > > > >
> > >
> > >
> >
> > > > >
> > >
> > > +--------------------------+
> >
> > > > >
> > >
> > > | INTC1 |
> >
> > > > +---------------+ |
> > >
> > > | |
> > |
> > > > orgates[0] | |
> > > > orgates[0]+----> |inpin[0]+------->outpin[0]+------> |
> > 0
> > > > > |
> > > > orgates[1]|----> |inpin[1]|------->outpin[1]|------> | 1 0-31
> > > > bits +--+ |
> > > > orgates[2]|----> |inpin[2]|------->outpin[2]|------> |
> > 2
> > > > > | |
> > > > orgates[3]|----> |inpin[3]|------->outpin[3]|------> |
> > 3
> > > > > | |
> > > > orgates[4]|----> |inpin[4]|------->outpin[4]|------> |
> > 4
> > > > > | |
> > > > orgates[5]+----> |inpin[5]+------->outpin[5]+------> |
> > 5
> > > > > | |
> > >
> > > | |
> >
> > > > > ---------------| | |
> > >
> > > +--------------------------+
> >
> > > > > |
> > > >
> > > > +-------------------------------------------------------------------
> > > > ----| |
> > >
> > > |
> >
> > > > >
> > >
> > > |
> >
> > > > >
> > > > | +------------------------------+
> > > > +-----------------+ |
> > >
> > > | | INTC0 |
> > |
> > > > GIC | |
> > > > | |inpin[0:0]--------->outpin[0] +--------->
> > > 192
> > > > > |
> > > > | |inpin[0:1]|-------->outpin[1] |--------->
> > > 193
> > > > > |
> > > > | |inpin[0:2]|-------->outpin[2] |--------->
> > > 194
> > > > > |
> > > > | |inpin[0:3]|-------->outpin[3] |--------->
> > > 195
> > > > > |
> > > > >--------------> |inpin[0:4]|-------->outpin[4] |--------->
> > > 196
> > > > > |
> > > > |inpin[0:5]|-------->outpin[5] |--------->
> > > 197
> > > > > |
> > > > |inpin[0:6]|-------->outpin[6] |--------->
> > > 198
> > > > > |
> > > > |inpin[0:7]|-------->outpin[7] |--------->
> > > 199
> > > > > |
> > > > |inpin[0:8]|-------->outpin[8] |--------->
> > > 200
> > > > > |
> > > > |inpin[0:9]|-------->outpin[9] |--------->
> > > 201
> > > > > |
> > > +---------------------------------------------------------------------------------------+
> > > +---------------------------------------------------------------------------------------+
> > > > orgates[1]|-----> |inpin[1]|---------->outpin[10]|--------->
> > > 128
> > > > > |
> > > > orgates[2]|-----> |inpin[2]|---------->outpin[11]|--------->
> > > 129
> > > > > |
> > > > orgates[3]|-----> |inpin[3]|---------->outpin[12]|--------->
> > > 130
> > > > > |
> > > > orgates[4]|-----> |inpin[4]|---------->outpin[13]|--------->
> > > 131
> > > > > |
> > > > orgates[5]|-----> |inpin[5]|---------->outpin[14]|--------->
> > > 132
> > > > > |
> > > > orgates[6]|-----> |inpin[6]|---------->outpin[15]|--------->
> > > 133
> > > > > |
> > > > orgates[7]|-----> |inpin[7]|---------->outpin[16]|--------->
> > > 134
> > > > > |
> > > > orgates[8]|-----> |inpin[8]|---------->outpin[17]|--------->
> > > 135
> > > > > |
> > > > orgates[9]+-----> |inpin[9]|---------->outpin[18]+--------->
> > > 136
> > > > > |
> > > > +------------------------------+
> > > > +-----------------+ |
> > >
> > >
> >
> > > > >
> > > > AST2700 A0
> > Design
> >
> > > > >
> > >
> > >
> >
> > > > >
> > > +---------------------------------------------------------------------------------------+
> > >
> >
> > Okay, so I think this is the diagram and discussion I asked for as documentation
> > earlier. I still prefer it doesn't just live in a commit message, that you pull it out
> > to a separate document that we can easily point to and evolve.
> >
> INTC drivers owners update DTS binding document here,
> https://patchwork.kernel.org/project/linux-arm-kernel/patch/20241016022410.1154574-2-kevin_chen@aspeedtech.com/
The diagram there is relatively straight-forward, but I suspect the
devil is in the details.
>
>
> > I'm a little hazy on some of your notation in diagram though. Can you explain
> > your use of pipes ("|"), plusses ("+"), the "orgates" to the left of INTC1 (what
> > are they ORing?), and the choice of 5 lines into the "orgates[0]" box? Also why
> > does the "orgates[0]" arrow point where it does on INTC0?
> >
> I created this block diagram using the asciiflow tool and both ("I") and "("+") symbols are identical.
> I will update the diagram and replace ("+") with ("|").
> Sorry to make you confuse.
Ah, right.
>
> The design of the OR gates for GICINT 196 is as follows:
196? You discuss 192 below.
> It has interrupt sources ranging from 0 to 31, with its output pin connected to INTC_IO "T0 GICINTC_192".
> The output pin is then connected to INTC_CPU "GIC_192_201" at bit 0, and its bit 0 output should be connected to GIC 192.
>
> The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as following:
> Bit 0 --> GIC 192
> BIT 1 -> GIC 193
> BIT 2-> GIC 194
>
> Our firmware only utilizes bits 0 to 5, so I have only illustrated bits 0 to 5 in the diagram. However, I have implemented bits 0 to 9 in the code.
Ah, okay, this is helpful context.
>
> Then, orgates[0] "or" the output pins of INTC_IO (To GIC192, To GIC193, To GIC194, To GIC195, To GIC196)
>
> ETH1 +-----------+
> +--------v+0 3+
> ETH2 | 4|
> +-------->+1 5|
> ETH3 | 6|
> +-------->+2 19|
> UART0 | 20|
> +-------->+7 21|
> UART1 | 22|
> +-------->+8 23|
> UART2 | 24|
> +-------->+9 25|
> UART3 | 26|
> +--------->10 27|
> UART5 | 28|
> +-------->+11 29|
> UART6 | |
> +-------->+12 30|
> UART7 | 31|
> +-------->+13 |
> UART8 | OR[0:31] |
> +--------->14 |
> UART9 | |
> +-------->+15 |
> UART10 | |
> +-------->+16 |
> UART11 | |
> +-------->+17 |
> UART12 | |
> +--------->18 |
> | |
> | |
> | |
> +-----------+
>
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi#L483
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi#L1610
Let me absorb this and develop my own understanding in conjunction with
the datasheet. It may take a few days.
Andrew
Hi Andrew,
> From: Andrew Jeffery <andrew@codeconstruct.com.au>
> Sent: Wednesday, February 5, 2025 11:51 AM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater <clg@kaod.org>;
> Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Joel Stanley
> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> list:All patches CC here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of
> INTC controllers for AST2700 A1
>
> On Tue, 2025-02-04 at 09:43 +0000, Jamin Lin wrote:
> > Hi Andrew,
> >
> > > -----Original Message-----
> > > From: Andrew Jeffery <andrew@codeconstruct.com.au>
> > > Sent: Thursday, January 30, 2025 12:20 PM
> > > To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater
> > > <clg@kaod.org>; Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> > > <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Joel
> > > Stanley <joel@jms.id.au>; open list:ASPEED BMCs
> > > <qemu-arm@nongnu.org>; open list:All patches CC here
> > > <qemu-devel@nongnu.org>
> > > Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> > > <yunlin.tang@aspeedtech.com>
> > > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two
> > > levels of INTC controllers for AST2700 A1
> > >
> > > On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> > > > The design of INTC controllers has significantly changed in AST2700 A1.
> > > >
> > > > There are a total of 480 interrupt sources in AST2700 A1. For
> > > > interrupt numbers from 0 to 127, they can route directly to PSP,
> > > > SSP, and TSP. Due to the limitation of interrupt numbers of
> > > > processors, the interrupts are merged every
> > > > 32 sources for interrupt numbers greater than 127.
> > > >
> > > > There are two levels of interrupt controllers, INTC0 and INTC1.
> > > > The interrupt sources of INTC0 are the interrupt numbers from
> > > > INTC_0 to
> > > > INTC_127 and interrupts from INTC1. The interrupt sources of INTC1
> > > > are the interrupt numbers greater than INTC_127. INTC1 controls
> > > > the interrupts
> > > INTC_128 to INTC_319 only.
> > > >
> > > > Currently, only GIC 192 to 201 are supported, and their source
> > > > interrupts are from INTC1 and connected to INTC0 at input pin 0
> > > > and output pins 0 to 9 for GIC 192-201.
> > > >
> > > > To support both AST2700 A1 and A0, INTC0 input pins 1 to 9 and
> > > > output pins
> > > > 10 to 18 remain to support GIC 128-136, which source interrupts from
> INTC0.
> > > > These will be removed if we decide not to support AST2700 A0 in the
> future.
> > > >
> > > > +---------------------------------------------------------------------------------------+
> > > > > AST2700 A1
> > > Design
> > > > > >
> > > >
> > > >
> > >
> > > > > >
> > > >
> > > > +--------------------------+
> > >
> > > > > >
> > > >
> > > > | INTC1 |
> > >
> > > > > +---------------+ |
> > > >
> > > > | |
> > > |
> > > > > orgates[0] | |
> > > > > orgates[0]+----> |inpin[0]+------->outpin[0]+------> |
> > > 0
> > > > > > |
> > > > > orgates[1]|----> |inpin[1]|------->outpin[1]|------> | 1
> > > > > 0-31 bits +--+ |
> > > > > orgates[2]|----> |inpin[2]|------->outpin[2]|------> |
> > > 2
> > > > > > | |
> > > > > orgates[3]|----> |inpin[3]|------->outpin[3]|------> |
> > > 3
> > > > > > | |
> > > > > orgates[4]|----> |inpin[4]|------->outpin[4]|------> |
> > > 4
> > > > > > | |
> > > > > orgates[5]+----> |inpin[5]+------->outpin[5]+------> |
> > > 5
> > > > > > | |
> > > >
> > > > | |
> > >
> > > > > > ---------------| | |
> > > >
> > > > +--------------------------+
> > >
> > > > > > |
> > > > >
> > > > > +---------------------------------------------------------------
> > > > > +----
> > > > > ----| |
> > > >
> > > > |
> > >
> > > > > >
> > > >
> > > > |
> > >
> > > > > >
> > > > > | +------------------------------+
> > > > > +-----------------+ |
> > > >
> > >
> > | | INTC0 |
> > > |
> > > > > GIC | |
> > > > > | |inpin[0:0]--------->outpin[0] +--------->
> > > > 192
> > > > > > |
> > > > > | |inpin[0:1]|-------->outpin[1] |--------->
> > > > 193
> > > > > > |
> > > > > | |inpin[0:2]|-------->outpin[2] |--------->
> > > > 194
> > > > > > |
> > > > > | |inpin[0:3]|-------->outpin[3] |--------->
> > > > 195
> > > > > > |
> > > > > >--------------> |inpin[0:4]|-------->outpin[4] |--------->
> > > > 196
> > > > > > |
> > > > > |inpin[0:5]|-------->outpin[5] |--------->
> > > > 197
> > > > > > |
> > > > > |inpin[0:6]|-------->outpin[6] |--------->
> > > > 198
> > > > > > |
> > > > > |inpin[0:7]|-------->outpin[7] |--------->
> > > > 199
> > > > > > |
> > > > > |inpin[0:8]|-------->outpin[8] |--------->
> > > > 200
> > > > > > |
> > > > > |inpin[0:9]|-------->outpin[9] |--------->
> > > > 201
> > > > > > |
> > > > +---------------------------------------------------------------------------------------+
> > > > +---------------------------------------------------------------------------------------+
> > > > > orgates[1]|-----> |inpin[1]|---------->outpin[10]|--------->
> > > > 128
> > > > > > |
> > > > > orgates[2]|-----> |inpin[2]|---------->outpin[11]|--------->
> > > > 129
> > > > > > |
> > > > > orgates[3]|-----> |inpin[3]|---------->outpin[12]|--------->
> > > > 130
> > > > > > |
> > > > > orgates[4]|-----> |inpin[4]|---------->outpin[13]|--------->
> > > > 131
> > > > > > |
> > > > > orgates[5]|-----> |inpin[5]|---------->outpin[14]|--------->
> > > > 132
> > > > > > |
> > > > > orgates[6]|-----> |inpin[6]|---------->outpin[15]|--------->
> > > > 133
> > > > > > |
> > > > > orgates[7]|-----> |inpin[7]|---------->outpin[16]|--------->
> > > > 134
> > > > > > |
> > > > > orgates[8]|-----> |inpin[8]|---------->outpin[17]|--------->
> > > > 135
> > > > > > |
> > > > > orgates[9]+-----> |inpin[9]|---------->outpin[18]+--------->
> > > > 136
> > > > > > |
> > > > > +------------------------------+
> > > > > +-----------------+ |
> > > >
> > > >
> > >
> > > > > >
> > > > > AST2700 A0
> > > Design
> > >
> > > > > >
> > > >
> > > >
> > >
> > > > > >
> > > > +---------------------------------------------------------------------------------------+
> > > >
> > >
> > > Okay, so I think this is the diagram and discussion I asked for as
> > > documentation earlier. I still prefer it doesn't just live in a
> > > commit message, that you pull it out to a separate document that we can
> easily point to and evolve.
> > >
> > INTC drivers owners update DTS binding document here,
> > https://patchwork.kernel.org/project/linux-arm-kernel/patch/2024101602
> > 2410.1154574-2-kevin_chen@aspeedtech.com/
>
> The diagram there is relatively straight-forward, but I suspect the devil is in the
> details.
>
> >
> >
> > > I'm a little hazy on some of your notation in diagram though. Can
> > > you explain your use of pipes ("|"), plusses ("+"), the "orgates" to
> > > the left of INTC1 (what are they ORing?), and the choice of 5 lines
> > > into the "orgates[0]" box? Also why does the "orgates[0]" arrow point where
> it does on INTC0?
> > >
> > I created this block diagram using the asciiflow tool and both ("I") and "("+")
> symbols are identical.
> > I will update the diagram and replace ("+") with ("|").
> > Sorry to make you confuse.
>
> Ah, right.
>
> >
> > The design of the OR gates for GICINT 196 is as follows:
>
> 196? You discuss 192 below.
>
Sorry typo. I update my comments.
The design of the OR gates for GICINT 196 is as follows:
It has interrupt sources ranging from 0 to 31, with its output pin connected to
INTC_IO "T0 GICINT_196".
The output pin is then connected to INTC_CPU "GIC_192_201" at bit 4, and
its bit 4 output should be connected to GIC 196.
The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as following:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196
Jamin
|-------------------------------------------------------------------------------------------------------|
| AST2700 A1 Design |
| To GICINT196 |
| |
| ETH1 |-----------| |--------------------------| |--------------| |
| -------->|0 | | INTC_IO | | orgates[0] | |
| ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | |
| -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | |
| ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | |
| -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| |
| UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | | |
| -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | |
| UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | |
| -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | |
| UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | |
| -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | |
| UART3 | 26| |--------------------------| |--------------| | |
| ---------|10 27| | |
| UART5 | 28| | |
| -------->|11 29| | |
| UART6 | | | |
| -------->|12 30| |-----------------------------------------------------------------------| |
| UART7 | 31| | |
| -------->|13 | | |
| UART8 | OR[0:31] | | |------------------------------| |----------| |
| -------->|14 | | | INTC | | GIC | |
| UART9 | | | |inpin[0:0]--------->outpin[0] |---------->|192 | |
| -------->|15 | | |inpin[0:1]--------->outpin[1] |---------->|193 | |
| UART10 | | | |inpin[0:2]--------->outpin[2] |---------->|194 | |
| -------->|16 | | |inpin[0:3]--------->outpin[3] |---------->|195 | |
| UART11 | | |--------------> |inpin[0:4]--------->outpin[4] |---------->|196 | |
| -------->|17 | |inpin[0:5]--------->outpin[5] |---------->|197 | |
| UART12 | | |inpin[0:6]--------->outpin[6] |---------->|198 | |
| -------->|18 | |inpin[0:7]--------->outpin[7] |---------->|199 | |
| |-----------| |inpin[0:8]--------->outpin[8] |---------->|200 | |
| |inpin[0:9]--------->outpin[9] |---------->|201 | |
|-------------------------------------------------------------------------------------------------------|
|-------------------------------------------------------------------------------------------------------|
| ETH1 |-----------| orgates[1]------->|inpin[1]|---------->outpin[10]|---------->|128 | |
| -------->|0 | orgates[2]------->|inpin[2]|---------->outpin[11]|---------->|129 | |
| ETH2 | 4| orgates[3]------->|inpin[3]|---------->outpin[12]|---------->|130 | |
| -------->|1 5| orgates[4]------->|inpin[4]|---------->outpin[13]|---------->|131 | |
| ETH3 | 6|---->orgates[5]------->|inpin[5]|---------->outpin[14]|---------->|132 | |
| -------->|2 19| orgates[6]------->|inpin[6]|---------->outpin[15]|---------->|133 | |
| UART0 | 20| orgates[7]------->|inpin[7]|---------->outpin[16]|---------->|134 | |
| -------->|7 21| orgates[8]------->|inpin[8]|---------->outpin[17]|---------->|135 | |
| UART1 | 22| orgates[9]------->|inpin[9]|---------->outpin[18]|---------->|136 | |
| -------->|8 23| |------------------------------| |----------| |
| UART2 | 24| |
| -------->|9 25| AST2700 A0 Design |
| UART3 | 26| |
| -------->|10 27| |
| UART5 | 28| |
| -------->|11 29| GICINT132 |
| UART6 | | |
| -------->|12 30| |
| UART7 | 31| |
| -------->|13 | |
| UART8 | OR[0:31] | |
| -------->|14 | |
| UART9 | | |
| -------->|15 | |
| UART10 | | |
| -------->|16 | |
| UART11 | | |
| -------->|17 | |
| UART12 | | |
| -------->|18 | |
| |-----------| |
| |
|-------------------------------------------------------------------------------------------------------|
> >
> > Our firmware only utilizes bits 0 to 5, so I have only illustrated bits 0 to 5 in
> the diagram. However, I have implemented bits 0 to 9 in the code.
> > It has interrupt sources ranging from 0 to 31, with its output pin connected to
> INTC_IO "T0 GICINTC_192".
> > The output pin is then connected to INTC_CPU "GIC_192_201" at bit 0, and
> its bit 0 output should be connected to GIC 192.
> >
> > The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as
> following:
> > Bit 0 --> GIC 192
> > BIT 1 -> GIC 193
> > BIT 2-> GIC 194
> >
> > Our firmware only utilizes bits 0 to 5, so I have only illustrated bits 0 to 5 in
> the diagram. However, I have implemented bits 0 to 9 in the code.
>
> Ah, okay, this is helpful context.
>
> >
> > Then, orgates[0] "or" the output pins of INTC_IO (To GIC192, To
> > GIC193, To GIC194, To GIC195, To GIC196)
> >
> > ETH1 +-----------+
> > +--------v+0 3+
> > ETH2 | 4|
> > +-------->+1 5|
> > ETH3 | 6|
> > +-------->+2 19|
> > UART0 | 20|
> > +-------->+7 21|
> > UART1 | 22|
> > +-------->+8 23|
> > UART2 | 24|
> > +-------->+9 25|
> > UART3 | 26|
> > +--------->10 27|
> > UART5 | 28|
> > +-------->+11 29|
> > UART6 | |
> > +-------->+12 30|
> > UART7 | 31|
> > +-------->+13 |
> > UART8 | OR[0:31] |
> > +--------->14 |
> > UART9 | |
> > +-------->+15 |
> > UART10 | |
> > +-------->+16 |
> > UART11 | |
> > +-------->+17 |
> > UART12 | |
> > +--------->18 |
> > | |
> > | |
> > | |
> > +-----------+
> >
> > https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/a
> > rm64/boot/dts/aspeed/aspeed-g7.dtsi#L483
> > https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/a
> > rm64/boot/dts/aspeed/aspeed-g7.dtsi#L1610
>
> Let me absorb this and develop my own understanding in conjunction with the
> datasheet. It may take a few days.
>
> Andrew
> The design of the OR gates for GICINT 196 is as follows: > It has interrupt sources ranging from 0 to 31, with its output pin connected to > INTC_IO "T0 GICINT_196". > The output pin is then connected to INTC_CPU "GIC_192_201" at bit 4, and > its bit 4 output should be connected to GIC 196. > The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as following: > Bit 0 -> GIC 192 > Bit 1 -> GIC 193 > Bit 2 -> GIC 194 > Bit 3 -> GIC 195 > Bit 4 -> GIC 196 > > Jamin > |-------------------------------------------------------------------------------------------------------| > | AST2700 A1 Design | > | To GICINT196 | > | | > | ETH1 |-----------| |--------------------------| |--------------| | > | -------->|0 | | INTC_IO | | orgates[0] | | > | ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | | > | -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | | > | ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | | > | -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| | > | UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | | | > | -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | | > | UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | | > | -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | | > | UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | | > | -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | | > | UART3 | 26| |--------------------------| |--------------| | | > | ---------|10 27| | | > | UART5 | 28| | | > | -------->|11 29| | | > | UART6 | | | | > | -------->|12 30| |-----------------------------------------------------------------------| | > | UART7 | 31| | | > | -------->|13 | | | > | UART8 | OR[0:31] | | |------------------------------| |----------| | > | -------->|14 | | | INTC | | GIC | | > | UART9 | | | |inpin[0:0]--------->outpin[0] |---------->|192 | | > | -------->|15 | | |inpin[0:1]--------->outpin[1] |---------->|193 | | > | UART10 | | | |inpin[0:2]--------->outpin[2] |---------->|194 | | > | -------->|16 | | |inpin[0:3]--------->outpin[3] |---------->|195 | | > | UART11 | | |--------------> |inpin[0:4]--------->outpin[4] |---------->|196 | | > | -------->|17 | |inpin[0:5]--------->outpin[5] |---------->|197 | | > | UART12 | | |inpin[0:6]--------->outpin[6] |---------->|198 | | > | -------->|18 | |inpin[0:7]--------->outpin[7] |---------->|199 | | > | |-----------| |inpin[0:8]--------->outpin[8] |---------->|200 | | > | |inpin[0:9]--------->outpin[9] |---------->|201 | | > |-------------------------------------------------------------------------------------------------------| > |-------------------------------------------------------------------------------------------------------| > | ETH1 |-----------| orgates[1]------->|inpin[1]|---------->outpin[10]|---------->|128 | | > | -------->|0 | orgates[2]------->|inpin[2]|---------->outpin[11]|---------->|129 | | > | ETH2 | 4| orgates[3]------->|inpin[3]|---------->outpin[12]|---------->|130 | | > | -------->|1 5| orgates[4]------->|inpin[4]|---------->outpin[13]|---------->|131 | | > | ETH3 | 6|---->orgates[5]------->|inpin[5]|---------->outpin[14]|---------->|132 | | > | -------->|2 19| orgates[6]------->|inpin[6]|---------->outpin[15]|---------->|133 | | > | UART0 | 20| orgates[7]------->|inpin[7]|---------->outpin[16]|---------->|134 | | > | -------->|7 21| orgates[8]------->|inpin[8]|---------->outpin[17]|---------->|135 | | > | UART1 | 22| orgates[9]------->|inpin[9]|---------->outpin[18]|---------->|136 | | > | -------->|8 23| |------------------------------| |----------| | > | UART2 | 24| | > | -------->|9 25| AST2700 A0 Design | > | UART3 | 26| | > | -------->|10 27| | > | UART5 | 28| | > | -------->|11 29| GICINT132 | > | UART6 | | | > | -------->|12 30| | > | UART7 | 31| | > | -------->|13 | | > | UART8 | OR[0:31] | | > | -------->|14 | | > | UART9 | | | > | -------->|15 | | > | UART10 | | | > | -------->|16 | | > | UART11 | | | > | -------->|17 | | > | UART12 | | | > | -------->|18 | | > | |-----------| | > | | > |-------------------------------------------------------------------------------------------------------| Nice ! When you send the intc series for ast2700a1 support, could you please include this diagram in file docs/specs/aspeed-intc.rst with some description ? The text could be the same as the cover letter. Thanks, C.
Hi Cedric, > From: Cédric Le Goater <clg@kaod.org> > Sent: Thursday, February 6, 2025 3:23 PM > To: Jamin Lin <jamin_lin@aspeedtech.com>; Andrew Jeffery > <andrew@codeconstruct.com.au>; Peter Maydell <peter.maydell@linaro.org>; > Steven Lee <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; > Joel Stanley <joel@jms.id.au>; open list:ASPEED BMCs > <qemu-arm@nongnu.org>; open list:All patches CC here > <qemu-devel@nongnu.org> > Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang > <yunlin.tang@aspeedtech.com> > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of > INTC controllers for AST2700 A1 > > > The design of the OR gates for GICINT 196 is as follows: > > It has interrupt sources ranging from 0 to 31, with its output pin > > connected to INTC_IO "T0 GICINT_196". > > The output pin is then connected to INTC_CPU "GIC_192_201" at bit 4, > > and its bit 4 output should be connected to GIC 196. > > The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as > following: > > Bit 0 -> GIC 192 > > Bit 1 -> GIC 193 > > Bit 2 -> GIC 194 > > Bit 3 -> GIC 195 > > Bit 4 -> GIC 196 > > > > Jamin > > > |----------------------------------------------------------------------------------------------------- > --| > > | > AST2700 A1 Design | > > | To GICINT196 > | > > | > | > > | ETH1 |-----------| > |--------------------------| |--------------| | > > | -------->|0 | | > INTC_IO | | orgates[0] | | > > | ETH2 | 4| > orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | | > > | -------->|1 5| > orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | | > > | ETH3 | 6| > orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | | > > | -------->|2 19| > orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| | > > | UART0 | > 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | > | | > > | -------->|7 21| > orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | | > > | UART1 | 22| > orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | | > > | -------->|8 23| > orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | | > > | UART2 | 24| > orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | | > > | -------->|9 25| > orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | | > > | UART3 | 26| > |--------------------------| |--------------| | | > > | ---------|10 27| > | | > > | UART5 | 28| > | | > > | -------->|11 29| > | | > > | UART6 | | > | | > > | -------->|12 30| > |-----------------------------------------------------------------------| | > > | UART7 | 31| | > | > > | -------->|13 | | > | > > | UART8 | OR[0:31] | | > |------------------------------| |----------| | > > | -------->|14 | | | > INTC | | GIC | | > > | UART9 | | | > |inpin[0:0]--------->outpin[0] |---------->|192 | | > > | -------->|15 | | > |inpin[0:1]--------->outpin[1] |---------->|193 | | > > | UART10 | | | > |inpin[0:2]--------->outpin[2] |---------->|194 | | > > | -------->|16 | | > |inpin[0:3]--------->outpin[3] |---------->|195 | | > > | UART11 | | |--------------> > |inpin[0:4]--------->outpin[4] |---------->|196 | | > > | -------->|17 | > |inpin[0:5]--------->outpin[5] |---------->|197 | | > > | UART12 | | > |inpin[0:6]--------->outpin[6] |---------->|198 | | > > | -------->|18 | > |inpin[0:7]--------->outpin[7] |---------->|199 | | > > | |-----------| > |inpin[0:8]--------->outpin[8] |---------->|200 | | > > | > |inpin[0:9]--------->outpin[9] |---------->|201 | | > > > |----------------------------------------------------------------------------------------------------- > --| > > > |----------------------------------------------------------------------------------------------------- > --| > > | ETH1 |-----------| > orgates[1]------->|inpin[1]|---------->outpin[10]|---------->|128 | | > > | -------->|0 | > orgates[2]------->|inpin[2]|---------->outpin[11]|---------->|129 | | > > | ETH2 | 4| > orgates[3]------->|inpin[3]|---------->outpin[12]|---------->|130 | | > > | -------->|1 5| > orgates[4]------->|inpin[4]|---------->outpin[13]|---------->|131 | | > > | ETH3 | > 6|---->orgates[5]------->|inpin[5]|---------->outpin[14]|---------->|132 | > | > > | -------->|2 19| > orgates[6]------->|inpin[6]|---------->outpin[15]|---------->|133 | | > > | UART0 | 20| > orgates[7]------->|inpin[7]|---------->outpin[16]|---------->|134 | | > > | -------->|7 21| > orgates[8]------->|inpin[8]|---------->outpin[17]|---------->|135 | | > > | UART1 | 22| > orgates[9]------->|inpin[9]|---------->outpin[18]|---------->|136 | | > > | -------->|8 23| > |------------------------------| |----------| | > > | UART2 | 24| > | > > | -------->|9 25| AST2700 A0 > Design | > > | UART3 | 26| > | > > | -------->|10 27| > | > > | UART5 | 28| > | > > | -------->|11 29| GICINT132 > | > > | UART6 | | > | > > | -------->|12 30| > | > > | UART7 | 31| > | > > | -------->|13 | > | > > | UART8 | OR[0:31] | > | > > | -------->|14 | > | > > | UART9 | | > | > > | -------->|15 | > | > > | UART10 | | > | > > | -------->|16 | > | > > | UART11 | | > | > > | -------->|17 | > | > > | UART12 | | > | > > | -------->|18 | > | > > | |-----------| > | > > | > | > > > > |--------------------------------------------------------------------- > > ----------------------------------| > > > Nice ! When you send the intc series for ast2700a1 support, could you please > include this diagram in file docs/specs/aspeed-intc.rst with some description ? > The text could be the same as the cover letter. > Will add Thanks for suggestion Jamin > > Thanks, > > C.
Hi Jamin, > > > > > > The design of the OR gates for GICINT 196 is as follows: > > > > 196? You discuss 192 below. > > > Sorry typo. I update my comments. > > The design of the OR gates for GICINT 196 is as follows: > It has interrupt sources ranging from 0 to 31, with its output pin connected to > INTC_IO "T0 GICINT_196". > The output pin is then connected to INTC_CPU "GIC_192_201" at bit 4, and > its bit 4 output should be connected to GIC 196. > The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as following: > Bit 0 -> GIC 192 > Bit 1 -> GIC 193 > Bit 2 -> GIC 194 > Bit 3 -> GIC 195 > Bit 4 -> GIC 196 > > Jamin > |-------------------------------------------------------------------------------------------------------| > | AST2700 A1 Design | > | To GICINT196 | > | | > | ETH1 |-----------| |--------------------------| |--------------| | > | -------->|0 | | INTC_IO | | orgates[0] | | > | ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | | > | -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | | > | ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | | > | -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| | > | UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | | | > | -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | | > | UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | | > | -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | | > | UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | | > | -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | | > | UART3 | 26| |--------------------------| |--------------| | | > | ---------|10 27| | | > | UART5 | 28| | | > | -------->|11 29| | | > | UART6 | | | | > | -------->|12 30| |-----------------------------------------------------------------------| | > | UART7 | 31| | | > | -------->|13 | | | > | UART8 | OR[0:31] | | |------------------------------| |----------| | > | -------->|14 | | | INTC | | GIC | | > | UART9 | | | |inpin[0:0]--------->outpin[0] |---------->|192 | | > | -------->|15 | | |inpin[0:1]--------->outpin[1] |---------->|193 | | > | UART10 | | | |inpin[0:2]--------->outpin[2] |---------->|194 | | > | -------->|16 | | |inpin[0:3]--------->outpin[3] |---------->|195 | | > | UART11 | | |--------------> |inpin[0:4]--------->outpin[4] |---------->|196 | | > | -------->|17 | |inpin[0:5]--------->outpin[5] |---------->|197 | | > | UART12 | | |inpin[0:6]--------->outpin[6] |---------->|198 | | > | -------->|18 | |inpin[0:7]--------->outpin[7] |---------->|199 | | > | |-----------| |inpin[0:8]--------->outpin[8] |---------->|200 | | > | |inpin[0:9]--------->outpin[9] |---------->|201 | | > |-------------------------------------------------------------------------------------------------------| > |-------------------------------------------------------------------------------------------------------| > | ETH1 |-----------| orgates[1]------->|inpin[1]|---------->outpin[10]|---------->|128 | | > | -------->|0 | orgates[2]------->|inpin[2]|---------->outpin[11]|---------->|129 | | > | ETH2 | 4| orgates[3]------->|inpin[3]|---------->outpin[12]|---------->|130 | | > | -------->|1 5| orgates[4]------->|inpin[4]|---------->outpin[13]|---------->|131 | | > | ETH3 | 6|---->orgates[5]------->|inpin[5]|---------->outpin[14]|---------->|132 | | > | -------->|2 19| orgates[6]------->|inpin[6]|---------->outpin[15]|---------->|133 | | > | UART0 | 20| orgates[7]------->|inpin[7]|---------->outpin[16]|---------->|134 | | > | -------->|7 21| orgates[8]------->|inpin[8]|---------->outpin[17]|---------->|135 | | > | UART1 | 22| orgates[9]------->|inpin[9]|---------->outpin[18]|---------->|136 | | > | -------->|8 23| |------------------------------| |----------| | > | UART2 | 24| | > | -------->|9 25| AST2700 A0 Design | > | UART3 | 26| | > | -------->|10 27| | > | UART5 | 28| | > | -------->|11 29| GICINT132 | > | UART6 | | | > | -------->|12 30| | > | UART7 | 31| | > | -------->|13 | | > | UART8 | OR[0:31] | | > | -------->|14 | | > | UART9 | | | > | -------->|15 | | > | UART10 | | | > | -------->|16 | | > | UART11 | | | > | -------->|17 | | > | UART12 | | | > | -------->|18 | | > | |-----------| | > | | > |-------------------------------------------------------------------------------------------------------| > > Thanks, I'll consider this updated diagram as well while I put my own together from the other pieces of info you've provided. Andrew
Hi Jamin, On Thu, 6 Feb 2025 at 10:09, Andrew Jeffery <andrew@codeconstruct.com.au> wrote: > Thanks, I'll consider this updated diagram as well while I put my own > together from the other pieces of info you've provided. When you send the next version, please try to separate your code cleanups and minor renames into a different patch. It makes it easier to see what you're adding. Thanks, Joel
Hi Joel, > From: Joel Stanley <joel@jms.id.au> > Sent: Thursday, February 6, 2025 12:55 PM > To: Jamin Lin <jamin_lin@aspeedtech.com> > Cc: Andrew Jeffery <andrew@codeconstruct.com.au>; Cédric Le Goater > <clg@kaod.org>; Peter Maydell <peter.maydell@linaro.org>; Steven Lee > <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; open > list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here > <qemu-devel@nongnu.org>; Troy Lee <troy_lee@aspeedtech.com>; Yunlin > Tang <yunlin.tang@aspeedtech.com> > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of > INTC controllers for AST2700 A1 > > Hi Jamin, > > On Thu, 6 Feb 2025 at 10:09, Andrew Jeffery <andrew@codeconstruct.com.au> > wrote: > > Thanks, I'll consider this updated diagram as well while I put my own > > together from the other pieces of info you've provided. > > When you send the next version, please try to separate your code cleanups and > minor renames into a different patch. It makes it easier to see what you're > adding. > > Thanks, > > Joel Thanks for suggestion. Cedric, also made the same suggestion in patch 0, https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jamin_lin@aspeedtech.com/ I think I will re-send this first. 1. INTC rename/prereqs/cleanups hw/intc/aspeed: Rename INTC to INTC0 hw/intc/aspeed: Support different memory region ops hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 hw/intc/aspeed: Support setting different memory and register size hw/intc/aspeed: Introduce helper functions for enable and status registers hw/intc/aspeed: Add ID to trace events for better debugging hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin
On 2/6/25 06:15, Jamin Lin wrote: > Hi Joel, > >> From: Joel Stanley <joel@jms.id.au> >> Sent: Thursday, February 6, 2025 12:55 PM >> To: Jamin Lin <jamin_lin@aspeedtech.com> >> Cc: Andrew Jeffery <andrew@codeconstruct.com.au>; Cédric Le Goater >> <clg@kaod.org>; Peter Maydell <peter.maydell@linaro.org>; Steven Lee >> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; open >> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here >> <qemu-devel@nongnu.org>; Troy Lee <troy_lee@aspeedtech.com>; Yunlin >> Tang <yunlin.tang@aspeedtech.com> >> Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of >> INTC controllers for AST2700 A1 >> >> Hi Jamin, >> >> On Thu, 6 Feb 2025 at 10:09, Andrew Jeffery <andrew@codeconstruct.com.au> >> wrote: >>> Thanks, I'll consider this updated diagram as well while I put my own >>> together from the other pieces of info you've provided. >> >> When you send the next version, please try to separate your code cleanups and >> minor renames into a different patch. It makes it easier to see what you're >> adding. >> >> Thanks, >> >> Joel > > Thanks for suggestion. Cedric, also made the same suggestion in patch 0, > https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jamin_lin@aspeedtech.com/ > > I think I will re-send this first. > > 1. INTC rename/prereqs/cleanups > hw/intc/aspeed: Rename INTC to INTC0 I thought we were keeping INTC and introducing INTC_IO ? As you wish. If we choose to rename INTC to INTC0, I prefer that you send the series below first. > hw/intc/aspeed: Support different memory region ops > hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 > hw/intc/aspeed: Support setting different memory and register size > hw/intc/aspeed: Introduce helper functions for enable and status registers > hw/intc/aspeed: Add ID to trace events for better debugging > hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Thanks, C.
Hi Cedric, > From: Cédric Le Goater <clg@kaod.org> > Sent: Thursday, February 6, 2025 3:17 PM > To: Jamin Lin <jamin_lin@aspeedtech.com>; Joel Stanley <joel@jms.id.au> > Cc: Andrew Jeffery <andrew@codeconstruct.com.au>; Peter Maydell > <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy > Lee <leetroy@gmail.com>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; > open list:All patches CC here <qemu-devel@nongnu.org>; Troy Lee > <troy_lee@aspeedtech.com>; Yunlin Tang <yunlin.tang@aspeedtech.com> > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of > INTC controllers for AST2700 A1 > > On 2/6/25 06:15, Jamin Lin wrote: > > Hi Joel, > > > >> From: Joel Stanley <joel@jms.id.au> > >> Sent: Thursday, February 6, 2025 12:55 PM > >> To: Jamin Lin <jamin_lin@aspeedtech.com> > >> Cc: Andrew Jeffery <andrew@codeconstruct.com.au>; Cédric Le Goater > >> <clg@kaod.org>; Peter Maydell <peter.maydell@linaro.org>; Steven Lee > >> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; open > >> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here > >> <qemu-devel@nongnu.org>; Troy Lee <troy_lee@aspeedtech.com>; Yunlin > >> Tang <yunlin.tang@aspeedtech.com> > >> Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two > >> levels of INTC controllers for AST2700 A1 > >> > >> Hi Jamin, > >> > >> On Thu, 6 Feb 2025 at 10:09, Andrew Jeffery > >> <andrew@codeconstruct.com.au> > >> wrote: > >>> Thanks, I'll consider this updated diagram as well while I put my > >>> own together from the other pieces of info you've provided. > >> > >> When you send the next version, please try to separate your code > >> cleanups and minor renames into a different patch. It makes it easier > >> to see what you're adding. > >> > >> Thanks, > >> > >> Joel > > > > Thanks for suggestion. Cedric, also made the same suggestion in patch > > 0, > > https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2 > > 465942-1-jamin_lin@aspeedtech.com/ > > > > I think I will re-send this first. > > > > > 1. INTC rename/prereqs/cleanups > > hw/intc/aspeed: Rename INTC to INTC0 > > I thought we were keeping INTC and introducing INTC_IO ? As you wish. > Yes, I am working keeping INTC (CPU Die) and introducing INTC_IO(IO Die). I understand that INTC0 and INTC1 are very difficult to interpret or distinguish their meanings. Thanks-Jamin > If we choose to rename INTC to INTC0, I prefer that you send the series below > first. > > > > hw/intc/aspeed: Support different memory region ops > > hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 > > hw/intc/aspeed: Support setting different memory and register size > > hw/intc/aspeed: Introduce helper functions for enable and status > registers > > hw/intc/aspeed: Add ID to trace events for better debugging > > hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 > > Thanks, > > C.
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