Series comparison

-[PULL 0/8] loongarch-to-apply queue
+[PULL v2 0/9] loongarch-to-apply queue
-The following changes since commit 7433709a147706ad7d1956b15669279933d0f82b:
+The following changes since commit ece5f8374d0416a339f0c0a9399faa2c42d4ad6f:
-  Merge tag 'hw-misc-20250113' of https://github.com/philmd/qemu into staging (2025-01-14 12:46:56 -0500)
+  Merge tag 'linux-user-for-7.2-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2022-11-03 10:55:05 -0400)
 are available in the Git repository at:
-  https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20250116
+  https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20221104
-for you to fetch changes up to bb81f237401b5f89f6bba21d9d4f50e0073372a6:
+for you to fetch changes up to 2419978cb09e11bc53a07d4de5621424d2a6a86d:
-  hw/intc/loongarch_ipi: Use alternative implemation for cpu_by_arch_id (2025-01-15 14:36:19 +0800)
+  target/loongarch: Fix emulation of float-point disable exception (2022-11-04 17:10:53 +0800)
 ----------------------------------------------------------------
-pull-loongarch-20250116 queue
+pull-loongarch-20221104
 v2:
  - fix win32/win64 complie error;
  - Add Rui Wang' patches.
 ----------------------------------------------------------------
-Bibo Mao (7):
+Rui Wang (2):
-      hw/intc/loongarch_ipi: Implement realize interface
+      target/loongarch: Adjust the layout of hardware flags bit fields
-      hw/intc/loongson_ipi: Remove num_cpu from loongson_ipi_common
+      target/loongarch: Fix emulation of float-point disable exception
       hw/intc/loongson_ipi: Remove property num_cpu from loongson_ipi_common
       hw/intc/loongarch_ipi: Get cpu number from possible_cpu_arch_ids
       hw/intc/loongarch_ipi: Remove property num-cpu
       hw/intc/loongson_ipi: Add more input parameter for cpu_by_arch_id
       hw/intc/loongarch_ipi: Use alternative implemation for cpu_by_arch_id
-Miao Hao (1):
+Song Gao (2):
-      target/loongarch: Add page table walker support for debugger usage
+      target/loongarch: Add exception subcode
       target/loongarch: Fix raise_mmu_exception() set wrong exception_index
- hw/intc/loongarch_ipi.c               | 69 ++++++++++++++++++-------
+Xiaojuan Yang (5):
- hw/intc/loongson_ipi.c                | 43 +++++++++++++++-
+      hw/intc: Convert the memops to with_attrs in LoongArch extioi
- hw/intc/loongson_ipi_common.c         | 41 +++++----------
+      hw/intc: Fix LoongArch extioi coreisr accessing
- hw/loongarch/virt.c                   |  1 -
+      hw/loongarch: Load FDT table into dram memory space
- include/hw/intc/loongarch_ipi.h       |  1 +
+      hw/loongarch: Improve fdt for LoongArch virt machine
- include/hw/intc/loongson_ipi_common.h |  5 +-
+      hw/loongarch: Add TPM device for LoongArch virt machine
- target/loongarch/cpu_helper.c         | 94 +++++++++++++++++++++++++++++++++--
- target/loongarch/internals.h          |  4 +-
+ hw/intc/loongarch_extioi.c                         | 41 +++++++------
- target/loongarch/tcg/tlb_helper.c     |  4 +-
+ hw/intc/trace-events                               |  3 +-
-files changed, 203 insertions(+), 59 deletions(-)
+ hw/loongarch/acpi-build.c                          | 51 +++++++++++++++-
  hw/loongarch/virt.c                                | 53 ++++++++++++++---
  include/hw/loongarch/virt.h                        |  3 -
  include/hw/pci-host/ls7a.h                         |  1 +
  target/loongarch/cpu.c                             | 10 +++-
  target/loongarch/cpu.h                             | 69 +++++++++++++---------
  target/loongarch/insn_trans/trans_farith.c.inc     | 30 ++++++++++
  target/loongarch/insn_trans/trans_fcmp.c.inc       | 11 +++-
  target/loongarch/insn_trans/trans_fmemory.c.inc    | 34 +++++++++--
  target/loongarch/insn_trans/trans_fmov.c.inc       | 29 ++++++++-
  target/loongarch/insn_trans/trans_privileged.c.inc |  2 +-
  target/loongarch/iocsr_helper.c                    | 19 +++---
  target/loongarch/tlb_helper.c                      |  5 +-
  target/loongarch/translate.c                       |  6 +-
 files changed, 283 insertions(+), 84 deletions(-)

-[PULL 4/8] hw/intc/loongson_ipi: Remove property num_cpu from loongson_ipi_common
+[PULL v2 1/9] hw/intc: Convert the memops to with_attrs in LoongArch extioi
-With mips64 loongson ipi, num_cpu property is used. With loongarch
+From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
 ipi, num_cpu can be acquired from possible_cpu_arch_ids.
-Here remove property num_cpu from loongson_ipi_common, and put it into
+Converting the MemoryRegionOps read/write handlers to
-loongson and loongarch ipi separately.
+with_attrs in LoongArch extioi emulation.
-Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
-Reviewed-by: Bibo Mao <maobibo@loongson.cn>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-Id: <20221021015307.2570844-2-yangxiaojuan@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
- hw/intc/loongarch_ipi.c       | 6 ++++++
+ hw/intc/loongarch_extioi.c | 31 +++++++++++++++++--------------
- hw/intc/loongson_ipi.c        | 6 ++++++
+ hw/intc/trace-events       |  3 +--
- hw/intc/loongson_ipi_common.c | 6 ------
+files changed, 18 insertions(+), 16 deletions(-)
 files changed, 12 insertions(+), 6 deletions(-)
-diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
+diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/loongarch_ipi.c
+--- a/hw/intc/loongarch_extioi.c
-+++ b/hw/intc/loongarch_ipi.c
++++ b/hw/intc/loongarch_extioi.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void extioi_setirq(void *opaque, int irq, int level)
- #include "hw/boards.h"
+     extioi_update_irq(s, irq, level);
- #include "qapi/error.h"
+ }
- #include "hw/intc/loongarch_ipi.h"
-+#include "hw/qdev-properties.h"
+-static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size)
- #include "target/loongarch/cpu.h"
++static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
++                                unsigned size, MemTxAttrs attrs)
- static AddressSpace *get_iocsr_as(CPUState *cpu)
+ {
-@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
+     LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
      unsigned long offset = addr & 0xffff;
 -    uint32_t index, cpu, ret = 0;
 +    uint32_t index, cpu;
      switch (offset) {
      case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
          index = (offset - EXTIOI_NODETYPE_START) >> 2;
 -        ret = s->nodetype[index];
 +        *data = s->nodetype[index];
          break;
      case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
          index = (offset - EXTIOI_IPMAP_START) >> 2;
 -        ret = s->ipmap[index];
 +        *data = s->ipmap[index];
          break;
      case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
          index = (offset - EXTIOI_ENABLE_START) >> 2;
 -        ret = s->enable[index];
 +        *data = s->enable[index];
          break;
      case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:
          index = (offset - EXTIOI_BOUNCE_START) >> 2;
 -        ret = s->bounce[index];
 +        *data = s->bounce[index];
          break;
      case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
          index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
          cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
 -        ret = s->coreisr[cpu][index];
 +        *data = s->coreisr[cpu][index];
          break;
      case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
          index = (offset - EXTIOI_COREMAP_START) >> 2;
 -        ret = s->coremap[index];
 +        *data = s->coremap[index];
          break;
      default:
          break;
      }
 -    trace_loongarch_extioi_readw(addr, ret);
 -    return ret;
 +    trace_loongarch_extioi_readw(addr, *data);
 +    return MEMTX_OK;
  }
  static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
@@ -XXX,XX +XXX,XX @@ static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
      }
  }
-+static const Property loongarch_ipi_properties[] = {
+-static void extioi_writew(void *opaque, hwaddr addr,
-+    DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1),
+-                          uint64_t val, unsigned size)
-+};
++static MemTxResult extioi_writew(void *opaque, hwaddr addr,
-+
++                          uint64_t val, unsigned size,
- static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
++                          MemTxAttrs attrs)
  {
-     LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
+     LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
-@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
+     int i, cpu, index, old_data, irq;
+@@ -XXX,XX +XXX,XX @@ static void extioi_writew(void *opaque, hwaddr addr,
-     device_class_set_parent_realize(dc, loongarch_ipi_realize,
+     default:
-                                     &lic->parent_realize);
+         break;
-+    device_class_set_props(dc, loongarch_ipi_properties);
+     }
-     licc->get_iocsr_as = get_iocsr_as;
++    return MEMTX_OK;
      licc->cpu_by_arch_id = loongarch_cpu_by_arch_id;
  }
-diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
  static const MemoryRegionOps extioi_ops = {
 -    .read = extioi_readw,
 -    .write = extioi_writew,
 +    .read_with_attrs = extioi_readw,
 +    .write_with_attrs = extioi_writew,
      .impl.min_access_size = 4,
      .impl.max_access_size = 4,
      .valid.min_access_size = 4,
 diff --git a/hw/intc/trace-events b/hw/intc/trace-events
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/loongson_ipi.c
+--- a/hw/intc/trace-events
-+++ b/hw/intc/loongson_ipi.c
++++ b/hw/intc/trace-events
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ loongarch_msi_set_irq(int irq_num) "set msi irq %d"
- #include "qemu/osdep.h"
+ # loongarch_extioi.c
- #include "hw/intc/loongson_ipi.h"
+ loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d"
-+#include "hw/qdev-properties.h"
+-loongarch_extioi_readw(uint64_t addr, uint32_t val) "addr: 0x%"PRIx64 "val: 0x%x"
- #include "qapi/error.h"
++loongarch_extioi_readw(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
- #include "target/mips/cpu.h"
+ loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_unrealize(DeviceState *dev)
      k->parent_unrealize(dev);
  }
 +static const Property loongson_ipi_properties[] = {
 +    DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1),
 +};
 +
  static void loongson_ipi_class_init(ObjectClass *klass, void *data)
  {
      DeviceClass *dc = DEVICE_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data)
                                      &lic->parent_realize);
      device_class_set_parent_unrealize(dc, loongson_ipi_unrealize,
                                        &lic->parent_unrealize);
 +    device_class_set_props(dc, loongson_ipi_properties);
      licc->get_iocsr_as = get_iocsr_as;
      licc->cpu_by_arch_id = cpu_by_arch_id;
  }
 diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/loongson_ipi_common.c
 +++ b/hw/intc/loongson_ipi_common.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/sysbus.h"
  #include "hw/intc/loongson_ipi_common.h"
  #include "hw/irq.h"
 -#include "hw/qdev-properties.h"
  #include "qemu/log.h"
  #include "migration/vmstate.h"
  #include "trace.h"
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongson_ipi_common = {
      }
  };
 -static const Property ipi_common_properties[] = {
 -    DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1),
 -};
 -
- static void loongson_ipi_common_class_init(ObjectClass *klass, void *data)
- {
-     DeviceClass *dc = DEVICE_CLASS(klass);
-@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_common_class_init(ObjectClass *klass, void *data)
-                                     &licc->parent_realize);
-     device_class_set_parent_unrealize(dc, loongson_ipi_common_unrealize,
-                                       &licc->parent_unrealize);
--    device_class_set_props(dc, ipi_common_properties);
-     dc->vmsd = &vmstate_loongson_ipi_common;
- }
 --
-.43.5
+.31.1

-[PULL 7/8] hw/intc/loongson_ipi: Add more input parameter for cpu_by_arch_id
+[PULL v2 2/9] hw/intc: Fix LoongArch extioi coreisr accessing
-Add logic cpu index input parameter for function cpu_by_arch_id,
+From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
 CPUState::cpu_index is logic cpu slot index for possible_cpus.
-At the same time it is logic index with LoongsonIPICommonState::IPICore,
+. When cpu read or write extioi COREISR reg, it should access
-here hide access for CPUState::cpu_index directly, it comes from
+the reg belonged to itself, so the cpu index of 's->coreisr'
-function cpu_by_arch_id().
+is current cpu number. Using MemTxAttrs' requester_id to get
 the cpu index.
 . it need not to mask 0x1f when calculate the coreisr array index.
-Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
-Reviewed-by: Bibo Mao <maobibo@loongson.cn>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-Id: <20221021015307.2570844-3-yangxiaojuan@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
- hw/intc/loongarch_ipi.c               | 19 +++++++++++++++----
+ hw/intc/loongarch_extioi.c      | 10 ++++++----
- hw/intc/loongson_ipi.c                | 23 ++++++++++++++++++++++-
+ target/loongarch/iocsr_helper.c | 19 +++++++++++--------
- hw/intc/loongson_ipi_common.c         | 21 ++++++++++++---------
+files changed, 17 insertions(+), 12 deletions(-)
  include/hw/intc/loongson_ipi_common.h |  3 ++-
 files changed, 51 insertions(+), 15 deletions(-)
-diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
+diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/loongarch_ipi.c
+--- a/hw/intc/loongarch_extioi.c
-+++ b/hw/intc/loongarch_ipi.c
++++ b/hw/intc/loongarch_extioi.c
-@@ -XXX,XX +XXX,XX @@ static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
+@@ -XXX,XX +XXX,XX @@ static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
-     return found_cpu;
+         *data = s->bounce[index];
          break;
      case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
 -        index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
 -        cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
 +        index = (offset - EXTIOI_COREISR_START) >> 2;
 +        /* using attrs to get current cpu index */
 +        cpu = attrs.requester_id;
          *data = s->coreisr[cpu][index];
          break;
      case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
@@ -XXX,XX +XXX,XX @@ static MemTxResult extioi_writew(void *opaque, hwaddr addr,
          s->bounce[index] = val;
          break;
      case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
 -        index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
 -        cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
 +        index = (offset - EXTIOI_COREISR_START) >> 2;
 +        /* using attrs to get current cpu index */
 +        cpu = attrs.requester_id;
          old_data = s->coreisr[cpu][index];
          s->coreisr[cpu][index] = old_data & ~val;
          /* write 1 to clear interrrupt */
 diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/iocsr_helper.c
 +++ b/target/loongarch/iocsr_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/cpu_ldst.h"
  #include "tcg/tcg-ldst.h"
 +#define GET_MEMTXATTRS(cas) \
 +        ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})
 +
  uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
  {
      return address_space_ldub(&env->address_space_iocsr, r_addr,
 -                              MEMTXATTRS_UNSPECIFIED, NULL);
 +                              GET_MEMTXATTRS(env), NULL);
  }
--static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id)
+ uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
 +static int loongarch_cpu_by_arch_id(LoongsonIPICommonState *lics,
 +                                    int64_t arch_id, int *index, CPUState **pcs)
  {
-     MachineState *machine = MACHINE(qdev_get_machine());
+     return address_space_lduw(&env->address_space_iocsr, r_addr,
-     CPUArchId *archid;
+-                              MEMTXATTRS_UNSPECIFIED, NULL);
-+    CPUState *cs;
++                              GET_MEMTXATTRS(env), NULL);
      archid = find_cpu_by_archid(machine, arch_id);
 -    if (archid) {
 -        return CPU(archid->cpu);
 +    if (archid && archid->cpu) {
 +        cs = archid->cpu;
 +        if (index) {
 +            *index = cs->cpu_index;
 +        }
 +
 +        if (pcs) {
 +            *pcs = cs;
 +        }
 +
 +        return MEMTX_OK;
      }
 -    return NULL;
 +    return MEMTX_ERROR;
  }
- static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
+ uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
-diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
+ {
-index XXXXXXX..XXXXXXX 100644
+     return address_space_ldl(&env->address_space_iocsr, r_addr,
---- a/hw/intc/loongson_ipi.c
+-                             MEMTXATTRS_UNSPECIFIED, NULL);
-+++ b/hw/intc/loongson_ipi.c
++                             GET_MEMTXATTRS(env), NULL);
@@ -XXX,XX +XXX,XX @@ static AddressSpace *get_iocsr_as(CPUState *cpu)
      return NULL;
  }
-+static int loongson_cpu_by_arch_id(LoongsonIPICommonState *lics,
+ uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)
-+                                   int64_t arch_id, int *index, CPUState **pcs)
+ {
-+{
+     return address_space_ldq(&env->address_space_iocsr, r_addr,
-+    CPUState *cs;
+-                             MEMTXATTRS_UNSPECIFIED, NULL);
-+
++                             GET_MEMTXATTRS(env), NULL);
 +    cs = cpu_by_arch_id(arch_id);
 +    if (cs == NULL) {
 +        return MEMTX_ERROR;
 +    }
 +
 +    if (index) {
 +        *index = cs->cpu_index;
 +    }
 +
 +    if (pcs) {
 +        *pcs = cs;
 +    }
 +
 +    return MEMTX_OK;
 +}
 +
  static const MemoryRegionOps loongson_ipi_core_ops = {
      .read_with_attrs = loongson_ipi_core_readl,
      .write_with_attrs = loongson_ipi_core_writel,
@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data)
                                        &lic->parent_unrealize);
      device_class_set_props(dc, loongson_ipi_properties);
      licc->get_iocsr_as = get_iocsr_as;
 -    licc->cpu_by_arch_id = cpu_by_arch_id;
 +    licc->cpu_by_arch_id = loongson_cpu_by_arch_id;
  }
- static const TypeInfo loongson_ipi_types[] = {
+ void helper_iocsrwr_b(CPULoongArchState *env, target_ulong w_addr,
-diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c
+                       target_ulong val)
-index XXXXXXX..XXXXXXX 100644
+ {
---- a/hw/intc/loongson_ipi_common.c
+     address_space_stb(&env->address_space_iocsr, w_addr,
-+++ b/hw/intc/loongson_ipi_common.c
+-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
-@@ -XXX,XX +XXX,XX @@ static MemTxResult mail_send(LoongsonIPICommonState *ipi,
++                      val, GET_MEMTXATTRS(env), NULL);
      uint32_t cpuid;
      hwaddr addr;
      CPUState *cs;
 +    int cpu, ret;
      cpuid = extract32(val, 16, 10);
 -    cs = licc->cpu_by_arch_id(cpuid);
 -    if (cs == NULL) {
 +    ret = licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs);
 +    if (ret != MEMTX_OK) {
          return MEMTX_DECODE_ERROR;
      }
      /* override requester_id */
      addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
 -    attrs.requester_id = cs->cpu_index;
 +    attrs.requester_id = cpu;
      return send_ipi_data(ipi, cs, val, addr, attrs);
  }
-@@ -XXX,XX +XXX,XX @@ static MemTxResult any_send(LoongsonIPICommonState *ipi,
+ void helper_iocsrwr_h(CPULoongArchState *env, target_ulong w_addr,
-     uint32_t cpuid;
+                       target_ulong val)
-     hwaddr addr;
+ {
-     CPUState *cs;
+     address_space_stw(&env->address_space_iocsr, w_addr,
-+    int cpu, ret;
+-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
++                      val, GET_MEMTXATTRS(env), NULL);
      cpuid = extract32(val, 16, 10);
 -    cs = licc->cpu_by_arch_id(cpuid);
 -    if (cs == NULL) {
 +    ret = licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs);
 +    if (ret != MEMTX_OK) {
          return MEMTX_DECODE_ERROR;
      }
      /* override requester_id */
      addr = val & 0xffff;
 -    attrs.requester_id = cs->cpu_index;
 +    attrs.requester_id = cpu;
      return send_ipi_data(ipi, cs, val, addr, attrs);
  }
-@@ -XXX,XX +XXX,XX @@ MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
+ void helper_iocsrwr_w(CPULoongArchState *env, target_ulong w_addr,
-     uint32_t cpuid;
+                       target_ulong val)
-     uint8_t vector;
+ {
-     CPUState *cs;
+     address_space_stl(&env->address_space_iocsr, w_addr,
-+    int cpu, ret;
+-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
++                      val, GET_MEMTXATTRS(env), NULL);
-     addr &= 0xff;
+ }
-     trace_loongson_ipi_write(size, (uint64_t)addr, val);
-@@ -XXX,XX +XXX,XX @@ MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
+ void helper_iocsrwr_d(CPULoongArchState *env, target_ulong w_addr,
-         cpuid = extract32(val, 16, 10);
+                       target_ulong val)
-         /* IPI status vector */
+ {
-         vector = extract8(val, 0, 5);
+     address_space_stq(&env->address_space_iocsr, w_addr,
--        cs = licc->cpu_by_arch_id(cpuid);
+-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
--        if (cs == NULL || cs->cpu_index >= ipi->num_cpu) {
++                      val, GET_MEMTXATTRS(env), NULL);
-+        ret = licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs);
+ }
 +        if (ret != MEMTX_OK || cpu >= ipi->num_cpu) {
              return MEMTX_DECODE_ERROR;
          }
 -        loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF,
 +        loongson_ipi_core_writel(&ipi->cpu[cpu], CORE_SET_OFF,
                                   BIT(vector), 4, attrs);
          break;
      default:
 diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/intc/loongson_ipi_common.h
 +++ b/include/hw/intc/loongson_ipi_common.h
@@ -XXX,XX +XXX,XX @@ struct LoongsonIPICommonClass {
      DeviceRealize parent_realize;
      DeviceUnrealize parent_unrealize;
      AddressSpace *(*get_iocsr_as)(CPUState *cpu);
 -    CPUState *(*cpu_by_arch_id)(int64_t id);
 +    int (*cpu_by_arch_id)(LoongsonIPICommonState *lics, int64_t id,
 +                          int *index, CPUState **pcs);
  };
  MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
 --
-.43.5
+.31.1

-[PULL 6/8] hw/intc/loongarch_ipi: Remove property num-cpu
+[PULL v2 3/9] hw/loongarch: Load FDT table into dram memory space
-Since cpu number can be acquired from possible_cpu_arch_ids(),
+From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
 num-cpu property is not necessary. Here remove num-cpu property
 for object TYPE_LOONGARCH_IPI object.
-Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+Load FDT table into dram memory space, and the addr is 2 MiB.
-Reviewed-by: Bibo Mao <maobibo@loongson.cn>
+Since lowmem region starts from 0, FDT base address is located
 at 2 MiB to avoid NULL pointer access.
 Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
 Acked-by: Song Gao <gaosong@loongson.cn>
 Message-Id: <20221028014007.2718352-2-yangxiaojuan@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
- hw/intc/loongarch_ipi.c | 5 -----
+ hw/loongarch/virt.c         | 18 +++++++++++-------
- hw/loongarch/virt.c     | 1 -
+ include/hw/loongarch/virt.h |  3 ---
-files changed, 6 deletions(-)
+files changed, 11 insertions(+), 10 deletions(-)
-diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/loongarch_ipi.c
-+++ b/hw/intc/loongarch_ipi.c
-@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
-     }
- }
--static const Property loongarch_ipi_properties[] = {
--    DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1),
--};
--
- static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
- {
-     LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
-@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
-     device_class_set_parent_realize(dc, loongarch_ipi_realize,
-                                     &lic->parent_realize);
--    device_class_set_props(dc, loongarch_ipi_properties);
-     licc->get_iocsr_as = get_iocsr_as;
-     licc->cpu_by_arch_id = loongarch_cpu_by_arch_id;
- }
 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/loongarch/virt.c
 +++ b/hw/loongarch/virt.c
-@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
+@@ -XXX,XX +XXX,XX @@ static void fdt_add_pcie_node(const LoongArchMachineState *lams)
+, FDT_PCI_RANGE_MMIO, 2, base_mmio,
-     /* Create IPI device */
+, base_mmio, 2, size_mmio);
-     ipi = qdev_new(TYPE_LOONGARCH_IPI);
+     g_free(nodename);
--    qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus);
+-    qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size);
-     sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
+ }
-     /* IPI iocsr memory region */
+ static void fdt_add_irqchip_node(LoongArchMachineState *lams)
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
      MemoryRegion *address_space_mem = get_system_memory();
      LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
      int i;
 +    hwaddr fdt_base;
      if (!cpu_model) {
          cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
      lams->machine_done.notify = virt_machine_done;
      qemu_add_machine_init_done_notifier(&lams->machine_done);
      fdt_add_pcie_node(lams);
 -
 -    /* load fdt */
 -    MemoryRegion *fdt_rom = g_new(MemoryRegion, 1);
 -    memory_region_init_rom(fdt_rom, NULL, "fdt", VIRT_FDT_SIZE, &error_fatal);
 -    memory_region_add_subregion(get_system_memory(), VIRT_FDT_BASE, fdt_rom);
 -    rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, VIRT_FDT_BASE);
 +    /*
 +     * Since lowmem region starts from 0, FDT base address is located
 +     * at 2 MiB to avoid NULL pointer access.
 +     *
 +     * Put the FDT into the memory map as a ROM image: this will ensure
 +     * the FDT is copied again upon reset, even if addr points into RAM.
 +     */
 +    fdt_base = 2 * MiB;
 +    qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size);
 +    rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base);
  }
  bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)
 diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/loongarch/virt.h
 +++ b/include/hw/loongarch/virt.h
@@ -XXX,XX +XXX,XX @@
  #define VIRT_GED_MEM_ADDR       (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN)
  #define VIRT_GED_REG_ADDR       (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN)
 -#define VIRT_FDT_BASE           0x1c400000
 -#define VIRT_FDT_SIZE           0x100000
 -
  struct LoongArchMachineState {
      /*< private >*/
      MachineState parent_obj;
 --
-.43.5
+.31.1

-[PULL 2/8] hw/intc/loongarch_ipi: Implement realize interface
+[PULL v2 4/9] hw/loongarch: Improve fdt for LoongArch virt machine
-Add realize interface for loongarch ipi device.
+From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
-Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+Add new items into LoongArch FDT, including rtc and uart info.
-Reviewed-by: Bibo Mao <maobibo@loongson.cn>
 Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
 Reviewed-by: Song Gao <gaosong@loongson.cn>
 Message-Id: <20221028014007.2718352-3-yangxiaojuan@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
- hw/intc/loongarch_ipi.c         | 19 +++++++++++++++++++
+ hw/loongarch/virt.c        | 31 +++++++++++++++++++++++++++++++
- include/hw/intc/loongarch_ipi.h |  1 +
+ include/hw/pci-host/ls7a.h |  1 +
-files changed, 20 insertions(+)
+files changed, 32 insertions(+)
-diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
+diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/loongarch_ipi.c
+--- a/hw/loongarch/virt.c
-+++ b/hw/intc/loongarch_ipi.c
++++ b/hw/loongarch/virt.c
 @@ -XXX,XX +XXX,XX @@
+ #include "hw/display/ramfb.h"
- #include "qemu/osdep.h"
+ #include "hw/mem/pc-dimm.h"
- #include "hw/boards.h"
-+#include "qapi/error.h"
++static void fdt_add_rtc_node(LoongArchMachineState *lams)
  #include "hw/intc/loongarch_ipi.h"
  #include "target/loongarch/cpu.h"
@@ -XXX,XX +XXX,XX @@ static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id)
      return NULL;
  }
 +static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
 +{
-+    LoongarchIPIClass *lic = LOONGARCH_IPI_GET_CLASS(dev);
++    char *nodename;
-+    Error *local_err = NULL;
++    hwaddr base = VIRT_RTC_REG_BASE;
 +    hwaddr size = VIRT_RTC_LEN;
 +    MachineState *ms = MACHINE(lams);
 +
-+    lic->parent_realize(dev, &local_err);
++    nodename = g_strdup_printf("/rtc@%" PRIx64, base);
-+    if (local_err) {
++    qemu_fdt_add_subnode(ms->fdt, nodename);
-+        error_propagate(errp, local_err);
++    qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc");
-+        return;
++    qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 0x0, base, size);
-+    }
++    g_free(nodename);
 +}
 +
- static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
++static void fdt_add_uart_node(LoongArchMachineState *lams)
 +{
 +    char *nodename;
 +    hwaddr base = VIRT_UART_BASE;
 +    hwaddr size = VIRT_UART_SIZE;
 +    MachineState *ms = MACHINE(lams);
 +
 +    nodename = g_strdup_printf("/serial@%" PRIx64, base);
 +    qemu_fdt_add_subnode(ms->fdt, nodename);
 +    qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a");
 +    qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size);
 +    qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000);
 +    g_free(nodename);
 +}
 +
  static void create_fdt(LoongArchMachineState *lams)
  {
-     LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
+     MachineState *ms = MACHINE(lams);
-+    LoongarchIPIClass *lic = LOONGARCH_IPI_CLASS(klass);
+@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
-+    DeviceClass *dc = DEVICE_CLASS(klass);
+                    qdev_get_gpio_in(pch_pic,
+                                     VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET),
-+    device_class_set_parent_realize(dc, loongarch_ipi_realize,
+, serial_hd(0), DEVICE_LITTLE_ENDIAN);
-+                                    &lic->parent_realize);
++    fdt_add_uart_node(lams);
-     licc->get_iocsr_as = get_iocsr_as;
-     licc->cpu_by_arch_id = loongarch_cpu_by_arch_id;
+     /* Network init */
- }
+     for (i = 0; i < nb_nics; i++) {
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo loongarch_ipi_types[] = {
+@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
-     {
+     sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
-         .name               = TYPE_LOONGARCH_IPI,
+                          qdev_get_gpio_in(pch_pic,
-         .parent             = TYPE_LOONGSON_IPI_COMMON,
+                          VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET));
-+        .instance_size      = sizeof(LoongarchIPIState),
++    fdt_add_rtc_node(lams);
-+        .class_size         = sizeof(LoongarchIPIClass),
-         .class_init         = loongarch_ipi_class_init,
+     pm_mem = g_new(MemoryRegion, 1);
-     }
+     memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops,
- };
+diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
 diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/intc/loongarch_ipi.h
+--- a/include/hw/pci-host/ls7a.h
-+++ b/include/hw/intc/loongarch_ipi.h
++++ b/include/hw/pci-host/ls7a.h
-@@ -XXX,XX +XXX,XX @@ struct LoongarchIPIState {
+@@ -XXX,XX +XXX,XX @@
+ #define VIRT_PCI_IRQS            48
- struct LoongarchIPIClass {
+ #define VIRT_UART_IRQ            (PCH_PIC_IRQ_OFFSET + 2)
-     LoongsonIPICommonClass parent_class;
+ #define VIRT_UART_BASE           0x1fe001e0
-+    DeviceRealize parent_realize;
++#define VIRT_UART_SIZE           0X100
- };
+ #define VIRT_RTC_IRQ             (PCH_PIC_IRQ_OFFSET + 3)
+ #define VIRT_MISC_REG_BASE       (VIRT_PCH_REG_BASE + 0x00080000)
- #endif
+ #define VIRT_RTC_REG_BASE        (VIRT_MISC_REG_BASE + 0x00050100)
 --
-.43.5
+.31.1

-[PULL 3/8] hw/intc/loongson_ipi: Remove num_cpu from loongson_ipi_common
+[PULL v2 5/9] hw/loongarch: Add TPM device for LoongArch virt machine
-With mips64 loongson ipi, num_cpu property is used. With loongarch
+From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
 ipi, num_cpu can be acquired from possible_cpu_arch_ids.
-Here remove num_cpu setting from loongson_ipi_common, and this piece
+Add TPM device for LoongArch virt machine, including
-of code is put into loongson and loongarch ipi separately.
+establish TPM acpi info and add TYPE_TPM_TIS_SYSBUS
 to dynamic_sysbus_devices list.
-Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
-Reviewed-by: Bibo Mao <maobibo@loongson.cn>
+Reviewed-by: Song Gao <gaosong@loongson.cn>
 Message-Id: <20221028014007.2718352-4-yangxiaojuan@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
- hw/intc/loongarch_ipi.c       | 13 +++++++++++++
+ hw/loongarch/acpi-build.c | 51 ++++++++++++++++++++++++++++++++++++++-
- hw/intc/loongson_ipi.c        | 14 +++++++++++++-
+ hw/loongarch/virt.c       |  4 +++
- hw/intc/loongson_ipi_common.c | 14 --------------
+files changed, 54 insertions(+), 1 deletion(-)
 files changed, 26 insertions(+), 15 deletions(-)
-diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
+diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/loongarch_ipi.c
+--- a/hw/loongarch/acpi-build.c
-+++ b/hw/intc/loongarch_ipi.c
++++ b/hw/loongarch/acpi-build.c
-@@ -XXX,XX +XXX,XX @@ static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id)
+@@ -XXX,XX +XXX,XX @@
- static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
+ #include "hw/acpi/generic_event_device.h"
- {
+ #include "hw/pci-host/gpex.h"
-+    LoongsonIPICommonState *lics = LOONGSON_IPI_COMMON(dev);
++#include "sysemu/tpm.h"
-     LoongarchIPIClass *lic = LOONGARCH_IPI_GET_CLASS(dev);
++#include "hw/platform-bus.h"
-     Error *local_err = NULL;
++#include "hw/acpi/aml-build.h"
-+    int i;
+ #define ACPI_BUILD_ALIGN_SIZE             0x1000
-     lic->parent_realize(dev, &local_err);
+ #define ACPI_BUILD_TABLE_SIZE             0x20000
-     if (local_err) {
+@@ -XXX,XX +XXX,XX @@ static void build_pci_device_aml(Aml *scope, LoongArchMachineState *lams)
-         error_propagate(errp, local_err);
+     acpi_dsdt_add_gpex(scope, &cfg);
-         return;
+ }
-     }
 +#ifdef CONFIG_TPM
 +static void acpi_dsdt_add_tpm(Aml *scope, LoongArchMachineState *vms)
 +{
 +    PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
 +    hwaddr pbus_base = VIRT_PLATFORM_BUS_BASEADDRESS;
 +    SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());
 +    MemoryRegion *sbdev_mr;
 +    hwaddr tpm_base;
 +
-+    if (lics->num_cpu == 0) {
++    if (!sbdev) {
 +        error_setg(errp, "num-cpu must be at least 1");
 +        return;
 +    }
 +
-+    lics->cpu = g_new0(IPICore, lics->num_cpu);
++    tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
-+    for (i = 0; i < lics->num_cpu; i++) {
++    assert(tpm_base != -1);
-+        lics->cpu[i].ipi = lics;
++
-+        qdev_init_gpio_out(dev, &lics->cpu[i].irq, 1);
++    tpm_base += pbus_base;
 +
 +    sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
 +
 +    Aml *dev = aml_device("TPM0");
 +    aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
 +    aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
 +    aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 +
 +    Aml *crs = aml_resource_template();
 +    aml_append(crs,
 +               aml_memory32_fixed(tpm_base,
 +                                  (uint32_t)memory_region_size(sbdev_mr),
 +                                  AML_READ_WRITE));
 +    aml_append(dev, aml_name_decl("_CRS", crs));
 +    aml_append(scope, dev);
 +}
 +#endif
 +
  /* build DSDT */
  static void
  build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
      build_uart_device_aml(dsdt);
      build_pci_device_aml(dsdt, lams);
      build_la_ged_aml(dsdt, machine);
 -
 +#ifdef CONFIG_TPM
 +    acpi_dsdt_add_tpm(dsdt, lams);
 +#endif
      /* System State Package */
      scope = aml_scope("\\");
      pkg = aml_package(4);
@@ -XXX,XX +XXX,XX @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
                     lams->oem_table_id);
      }
 +#ifdef CONFIG_TPM
 +    /* TPM info */
 +    if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
 +        acpi_add_table(table_offsets, tables_blob);
 +        build_tpm2(tables_blob, tables->linker,
 +                   tables->tcpalog, lams->oem_id,
 +                   lams->oem_table_id);
 +    }
++#endif
+     /* Add tables supplied by user (if any) */
+     for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
+         unsigned len = acpi_table_len(u);
+diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/loongarch/virt.c
++++ b/hw/loongarch/virt.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/platform-bus.h"
+ #include "hw/display/ramfb.h"
+ #include "hw/mem/pc-dimm.h"
++#include "sysemu/tpm.h"
+ static void fdt_add_rtc_node(LoongArchMachineState *lams)
+ {
+@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
+     object_class_property_set_description(oc, "acpi",
+         "Enable ACPI");
+     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
++#ifdef CONFIG_TPM
++    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
++#endif
  }
- static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
+ static const TypeInfo loongarch_machine_types[] = {
 diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/loongson_ipi.c
 +++ b/hw/intc/loongson_ipi.c
@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp)
      LoongsonIPIClass *lic = LOONGSON_IPI_GET_CLASS(dev);
      SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
      Error *local_err = NULL;
 +    int i;
      lic->parent_realize(dev, &local_err);
      if (local_err) {
@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp)
          return;
      }
 +    if (sc->num_cpu == 0) {
 +        error_setg(errp, "num-cpu must be at least 1");
 +        return;
 +    }
 +
 +    sc->cpu = g_new0(IPICore, sc->num_cpu);
 +    for (i = 0; i < sc->num_cpu; i++) {
 +        sc->cpu[i].ipi = sc;
 +        qdev_init_gpio_out(dev, &sc->cpu[i].irq, 1);
 +    }
 +
      s->ipi_mmio_mem = g_new0(MemoryRegion, sc->num_cpu);
 -    for (unsigned i = 0; i < sc->num_cpu; i++) {
 +    for (i = 0; i < sc->num_cpu; i++) {
          g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i);
          memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev),
 diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/loongson_ipi_common.c
 +++ b/hw/intc/loongson_ipi_common.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/intc/loongson_ipi_common.h"
  #include "hw/irq.h"
  #include "hw/qdev-properties.h"
 -#include "qapi/error.h"
  #include "qemu/log.h"
  #include "migration/vmstate.h"
  #include "trace.h"
@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
  {
      LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev);
      SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 -    int i;
 -
 -    if (s->num_cpu == 0) {
 -        error_setg(errp, "num-cpu must be at least 1");
 -        return;
 -    }
      memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev),
                            &loongson_ipi_iocsr_ops,
@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
                            &loongson_ipi64_ops,
                            s, "loongson_ipi64_iocsr", 0x118);
      sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem);
 -
 -    s->cpu = g_new0(IPICore, s->num_cpu);
 -    for (i = 0; i < s->num_cpu; i++) {
 -        s->cpu[i].ipi = s;
 -
 -        qdev_init_gpio_out(dev, &s->cpu[i].irq, 1);
 -    }
  }
  static void loongson_ipi_common_unrealize(DeviceState *dev)
 --
-.43.5
+.31.1

-New patch
+[PULL v2 6/9] target/loongarch: Add exception subcode
+We need subcodes to distinguish the same excode cs->exception_indexs,
+such as EXCCODE_ADEF/EXCCODE_ADEM.
+Signed-off-by: Song Gao <gaosong@loongson.cn>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20221101073210.3934280-1-gaosong@loongson.cn>
+---
+ target/loongarch/cpu.c |  7 +++--
+ target/loongarch/cpu.h | 58 ++++++++++++++++++++++--------------------
+files changed, 36 insertions(+), 29 deletions(-)
+diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/loongarch/cpu.c
++++ b/target/loongarch/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
+         env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
+                                       PC, (env->pc >> 2));
+     } else {
+-        env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause);
++        env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE,
++                                    EXCODE_MCODE(cause));
++        env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE,
++                                    EXCODE_SUBCODE(cause));
+         env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
+                                    FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
+         env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
+@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
+             env->pc = env->CSR_TLBRENTRY;
+         } else {
+             env->pc = env->CSR_EENTRY;
+-            env->pc += cause * vec_size;
++            env->pc += EXCODE_MCODE(cause) * vec_size;
+         }
+         qemu_log_mask(CPU_LOG_INT,
+                       "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
+diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/loongarch/cpu.h
++++ b/target/loongarch/cpu.h
+@@ -XXX,XX +XXX,XX @@ FIELD(FCSR0, CAUSE, 24, 5)
+ #define FP_DIV0           8
+ #define FP_INVALID        16
+-#define  EXCCODE_EXTERNAL_INT   64   /* plus external interrupt number */
+-#define  EXCCODE_INT                 0
+-#define  EXCCODE_PIL                 1
+-#define  EXCCODE_PIS                 2
+-#define  EXCCODE_PIF                 3
+-#define  EXCCODE_PME                 4
+-#define  EXCCODE_PNR                 5
+-#define  EXCCODE_PNX                 6
+-#define  EXCCODE_PPI                 7
+-#define  EXCCODE_ADEF                8 /* Different exception subcode */
+-#define  EXCCODE_ADEM                8
+-#define  EXCCODE_ALE                 9
+-#define  EXCCODE_BCE                 10
+-#define  EXCCODE_SYS                 11
+-#define  EXCCODE_BRK                 12
+-#define  EXCCODE_INE                 13
+-#define  EXCCODE_IPE                 14
+-#define  EXCCODE_FPD                 15
+-#define  EXCCODE_SXD                 16
+-#define  EXCCODE_ASXD                17
+-#define  EXCCODE_FPE                 18 /* Different exception subcode */
+-#define  EXCCODE_VFPE                18
+-#define  EXCCODE_WPEF                19 /* Different exception subcode */
+-#define  EXCCODE_WPEM                19
+-#define  EXCCODE_BTD                 20
+-#define  EXCCODE_BTE                 21
+-#define  EXCCODE_DBP                 26 /* Reserved subcode used for debug */
++#define EXCODE(code, subcode) ( ((subcode) << 6) | (code) )
++#define EXCODE_MCODE(code)    ( (code) & 0x3f )
++#define EXCODE_SUBCODE(code)  ( (code) >> 6 )
++
++#define  EXCCODE_EXTERNAL_INT        64   /* plus external interrupt number */
++#define  EXCCODE_INT                 EXCODE(0, 0)
++#define  EXCCODE_PIL                 EXCODE(1, 0)
++#define  EXCCODE_PIS                 EXCODE(2, 0)
++#define  EXCCODE_PIF                 EXCODE(3, 0)
++#define  EXCCODE_PME                 EXCODE(4, 0)
++#define  EXCCODE_PNR                 EXCODE(5, 0)
++#define  EXCCODE_PNX                 EXCODE(6, 0)
++#define  EXCCODE_PPI                 EXCODE(7, 0)
++#define  EXCCODE_ADEF                EXCODE(8, 0) /* Different exception subcode */
++#define  EXCCODE_ADEM                EXCODE(8, 1)
++#define  EXCCODE_ALE                 EXCODE(9, 0)
++#define  EXCCODE_BCE                 EXCODE(10, 0)
++#define  EXCCODE_SYS                 EXCODE(11, 0)
++#define  EXCCODE_BRK                 EXCODE(12, 0)
++#define  EXCCODE_INE                 EXCODE(13, 0)
++#define  EXCCODE_IPE                 EXCODE(14, 0)
++#define  EXCCODE_FPD                 EXCODE(15, 0)
++#define  EXCCODE_SXD                 EXCODE(16, 0)
++#define  EXCCODE_ASXD                EXCODE(17, 0)
++#define  EXCCODE_FPE                 EXCODE(18, 0) /* Different exception subcode */
++#define  EXCCODE_VFPE                EXCODE(18, 1)
++#define  EXCCODE_WPEF                EXCODE(19, 0) /* Different exception subcode */
++#define  EXCCODE_WPEM                EXCODE(19, 1)
++#define  EXCCODE_BTD                 EXCODE(20, 0)
++#define  EXCCODE_BTE                 EXCODE(21, 0)
++#define  EXCCODE_DBP                 EXCODE(26, 0) /* Reserved subcode used for debug */
+ /* cpucfg[0] bits */
+ FIELD(CPUCFG0, PRID, 0, 32)
+--
+.31.1

-[PULL 1/8] target/loongarch: Add page table walker support for debugger usage
+[PULL v2 7/9] target/loongarch: Fix raise_mmu_exception() set wrong exception_index
-From: Miao Hao <haomiao23s@ict.ac.cn>
+When the address is invalid address, We should set exception_index
 according to MMUAccessType, and EXCCODE_ADEF need't update badinstr.
 Otherwise, The system enters an infinite loop. e.g:
 run test.c on system mode
 test.c:
     #include<stdio.h>
-When dump memory content with gva address, software page table walker is
+    void (*func)(int *);
 necessary to get responding gpa address.
-Here page table walker is added for debugger usage.
+    int main()
     {
         int i = 8;
         void *ptr = (void *)0x4000000000000000;
         func = ptr;
         func(&i);
         return 0;
     }
-Signed-off-by: Miao Hao <haomiao23s@ict.ac.cn>
+Signed-off-by: Song Gao <gaosong@loongson.cn>
-Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Bibo Mao <maobibo@loongson.cn>
+Message-ID: <20221101073210.3934280-2-gaosong@loongson.cn>
 ---
- target/loongarch/cpu_helper.c     | 94 +++++++++++++++++++++++++++++--
+ target/loongarch/cpu.c        | 1 +
- target/loongarch/internals.h      |  4 +-
+ target/loongarch/tlb_helper.c | 5 +++--
- target/loongarch/tcg/tlb_helper.c |  4 +-
+files changed, 4 insertions(+), 2 deletions(-)
 files changed, 94 insertions(+), 8 deletions(-)
-diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
+diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/loongarch/cpu_helper.c
+--- a/target/loongarch/cpu.c
-+++ b/target/loongarch/cpu_helper.c
++++ b/target/loongarch/cpu.c
-@@ -XXX,XX +XXX,XX @@ bool loongarch_tlb_search(CPULoongArchState *env, target_ulong vaddr,
+@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
-     return false;
+         }
- }
+         QEMU_FALLTHROUGH;
+     case EXCCODE_PIF:
-+static int loongarch_page_table_walker(CPULoongArchState *env, hwaddr *physical,
++    case EXCCODE_ADEF:
-+                                 int *prot, target_ulong address)
+         cause = cs->exception_index;
-+{
+         update_badinstr = 0;
-+    CPUState *cs = env_cpu(env);
+         break;
-+    target_ulong index, phys;
+diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
-+    uint64_t dir_base, dir_width;
+index XXXXXXX..XXXXXXX 100644
-+    uint64_t base;
+--- a/target/loongarch/tlb_helper.c
-+    int level;
++++ b/target/loongarch/tlb_helper.c
-+
+@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
-+    if ((address >> 63) & 0x1) {
+     switch (tlb_error) {
-+        base = env->CSR_PGDH;
+     default:
-+    } else {
+     case TLBRET_BADADDR:
-+        base = env->CSR_PGDL;
+-        cs->exception_index = EXCCODE_ADEM;
-+    }
++        cs->exception_index = access_type == MMU_INST_FETCH
-+    base &= TARGET_PHYS_MASK;
++                              ? EXCCODE_ADEF : EXCCODE_ADEM;
-+
+         break;
-+    for (level = 4; level > 0; level--) {
+     case TLBRET_NOMATCH:
-+        get_dir_base_width(env, &dir_base, &dir_width, level);
+         /* No TLB match for a mapped address */
-+
+@@ -XXX,XX +XXX,XX @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-+        if (dir_width == 0) {
+     CPULoongArchState *env = &cpu->env;
-+            continue;
+     hwaddr physical;
 +        }
 +
 +        /* get next level page directory */
 +        index = (address >> dir_base) & ((1 << dir_width) - 1);
 +        phys = base | index << 3;
 +        base = ldq_phys(cs->as, phys) & TARGET_PHYS_MASK;
 +        if (FIELD_EX64(base, TLBENTRY, HUGE)) {
 +            /* base is a huge pte */
 +            break;
 +        }
 +    }
 +
 +    /* pte */
 +    if (FIELD_EX64(base, TLBENTRY, HUGE)) {
 +        /* Huge Page. base is pte */
 +        base = FIELD_DP64(base, TLBENTRY, LEVEL, 0);
 +        base = FIELD_DP64(base, TLBENTRY, HUGE, 0);
 +        if (FIELD_EX64(base, TLBENTRY, HGLOBAL)) {
 +            base = FIELD_DP64(base, TLBENTRY, HGLOBAL, 0);
 +            base = FIELD_DP64(base, TLBENTRY, G, 1);
 +        }
 +    } else {
 +        /* Normal Page. base points to pte */
 +        get_dir_base_width(env, &dir_base, &dir_width, 0);
 +        index = (address >> dir_base) & ((1 << dir_width) - 1);
 +        phys = base | index << 3;
 +        base = ldq_phys(cs->as, phys);
 +    }
 +
 +    /* TODO: check plv and other bits? */
 +
 +    /* base is pte, in normal pte format */
 +    if (!FIELD_EX64(base, TLBENTRY, V)) {
 +        return TLBRET_NOMATCH;
 +    }
 +
 +    if (!FIELD_EX64(base, TLBENTRY, D)) {
 +        *prot = PAGE_READ;
 +    } else {
 +        *prot = PAGE_READ | PAGE_WRITE;
 +    }
 +
 +    /* get TARGET_PAGE_SIZE aligned physical address */
 +    base += (address & TARGET_PHYS_MASK) & ((1 << dir_base) - 1);
 +    /* mask RPLV, NX, NR bits */
 +    base = FIELD_DP64(base, TLBENTRY_64, RPLV, 0);
 +    base = FIELD_DP64(base, TLBENTRY_64, NX, 0);
 +    base = FIELD_DP64(base, TLBENTRY_64, NR, 0);
 +    /* mask other attribute bits */
 +    *physical = base & TARGET_PAGE_MASK;
 +
 +    return 0;
 +}
 +
  static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
                                   int *prot, target_ulong address,
 -                                 MMUAccessType access_type, int mmu_idx)
 +                                 MMUAccessType access_type, int mmu_idx,
 +                                 int is_debug)
  {
      int index, match;
@@ -XXX,XX +XXX,XX @@ static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
      if (match) {
          return loongarch_map_tlb_entry(env, physical, prot,
                                         address, access_type, index, mmu_idx);
 +    } else if (is_debug) {
 +        /*
 +         * For debugger memory access, we want to do the map when there is a
 +         * legal mapping, even if the mapping is not yet in TLB. return 0 if
 +         * there is a valid map, else none zero.
 +         */
 +        return loongarch_page_table_walker(env, physical, prot, address);
      }
      return TLBRET_NOMATCH;
@@ -XXX,XX +XXX,XX @@ static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
  #else
  static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
                                   int *prot, target_ulong address,
 -                                 MMUAccessType access_type, int mmu_idx)
 +                                 MMUAccessType access_type, int mmu_idx,
 +                                 int is_debug)
  {
      return TLBRET_NOMATCH;
  }
@@ -XXX,XX +XXX,XX @@ static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va,
  int get_physical_address(CPULoongArchState *env, hwaddr *physical,
                           int *prot, target_ulong address,
 -                         MMUAccessType access_type, int mmu_idx)
 +                         MMUAccessType access_type, int mmu_idx, int is_debug)
  {
      int user_mode = mmu_idx == MMU_USER_IDX;
      int kernel_mode = mmu_idx == MMU_KERNEL_IDX;
@@ -XXX,XX +XXX,XX @@ int get_physical_address(CPULoongArchState *env, hwaddr *physical,
      /* Mapped address */
      return loongarch_map_address(env, physical, prot, address,
 -                                 access_type, mmu_idx);
 +                                 access_type, mmu_idx, is_debug);
  }
  hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
@@ -XXX,XX +XXX,XX @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
      int prot;
+-    int ret = TLBRET_BADADDR;
-     if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD,
++    int ret;
 -                             cpu_mmu_index(cs, false)) != 0) {
 +                             cpu_mmu_index(cs, false), 1) != 0) {
          return -1;
      }
      return phys_addr;
 diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/internals.h
 +++ b/target/loongarch/internals.h
@@ -XXX,XX +XXX,XX @@ bool loongarch_tlb_search(CPULoongArchState *env, target_ulong vaddr,
                            int *index);
  int get_physical_address(CPULoongArchState *env, hwaddr *physical,
                           int *prot, target_ulong address,
 -                         MMUAccessType access_type, int mmu_idx);
 +                         MMUAccessType access_type, int mmu_idx, int is_debug);
 +void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
 +                               uint64_t *dir_width, target_ulong level);
  hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
  #ifdef CONFIG_TCG
 diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/tcg/tlb_helper.c
 +++ b/target/loongarch/tcg/tlb_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/log.h"
  #include "cpu-csr.h"
 -static void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
 +void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
                                 uint64_t *dir_width, target_ulong level)
  {
      switch (level) {
@@ -XXX,XX +XXX,XX @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
      /* Data access */
      ret = get_physical_address(env, &physical, &prot, address,
--                               access_type, mmu_idx);
-+                               access_type, mmu_idx, 0);
-     if (ret == TLBRET_MATCH) {
-         tlb_set_page(cs, address & TARGET_PAGE_MASK,
 --
-.43.5
+.31.1

-[PULL 8/8] hw/intc/loongarch_ipi: Use alternative implemation for cpu_by_arch_id
+[PULL v2 8/9] target/loongarch: Adjust the layout of hardware flags bit fields
-There is arch_id and CPUState pointer in IPICore object. With function
+From: Rui Wang <wangrui@loongson.cn>
 cpu_by_arch_id() it can be implemented by parsing IPICore array inside,
 rather than possible_cpus array.
-Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Bibo Mao <maobibo@loongson.cn>
+Reviewed-by: Song Gao <gaosong@loongson.cn>
 Signed-off-by: Rui Wang <wangrui@loongson.cn>
 Message-Id: <20221104040517.222059-2-wangrui@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
- hw/intc/loongarch_ipi.c | 36 +++++++++++-------------------------
+ target/loongarch/cpu.h                             | 9 ++++++++-
-file changed, 11 insertions(+), 25 deletions(-)
+ target/loongarch/insn_trans/trans_privileged.c.inc | 2 +-
  target/loongarch/translate.c                       | 6 +++++-
 files changed, 14 insertions(+), 3 deletions(-)
-diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
+diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/loongarch_ipi.c
+--- a/target/loongarch/cpu.h
-+++ b/hw/intc/loongarch_ipi.c
++++ b/target/loongarch/cpu.h
-@@ -XXX,XX +XXX,XX @@ static AddressSpace *get_iocsr_as(CPUState *cpu)
+@@ -XXX,XX +XXX,XX @@
-     return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
+ #include "qemu/timer.h"
  #include "exec/memory.h"
  #include "hw/sysbus.h"
 +#include "cpu-csr.h"
  #define IOCSRF_TEMP             0
  #define IOCSRF_NODECNT          1
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
  #endif
  }
--static int archid_cmp(const void *a, const void *b)
++/*
-+static int loongarch_ipi_cmp(const void *a, const void *b)
++ * LoongArch CPUs hardware flags.
 + */
 +#define HW_FLAGS_PLV_MASK   R_CSR_CRMD_PLV_MASK  /* 0x03 */
 +#define HW_FLAGS_CRMD_PG    R_CSR_CRMD_PG_MASK   /* 0x10 */
 +
  static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
                                          target_ulong *pc,
                                          target_ulong *cs_base,
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
  {
--   CPUArchId *archid_a = (CPUArchId *)a;
+     *pc = env->pc;
--   CPUArchId *archid_b = (CPUArchId *)b;
+     *cs_base = 0;
-+   IPICore *ipi_a = (IPICore *)a;
+-    *flags = cpu_mmu_index(env, false);
-+   IPICore *ipi_b = (IPICore *)b;
++    *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
 -   return archid_a->arch_id - archid_b->arch_id;
 -}
 -
 -static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
 -{
 -    CPUArchId apic_id, *found_cpu;
 -
 -    apic_id.arch_id = id;
 -    found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
 -                        ms->possible_cpus->len,
 -                        sizeof(*ms->possible_cpus->cpus),
 -                        archid_cmp);
 -
 -    return found_cpu;
 +   return ipi_a->arch_id - ipi_b->arch_id;
  }
- static int loongarch_cpu_by_arch_id(LoongsonIPICommonState *lics,
+ void loongarch_cpu_list(void);
-                                     int64_t arch_id, int *index, CPUState **pcs)
+diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/insn_trans/trans_privileged.c.inc
 +++ b/target/loongarch/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static const CSRInfo csr_info[] = {
  static bool check_plv(DisasContext *ctx)
  {
--    MachineState *machine = MACHINE(qdev_get_machine());
+-    if (ctx->base.tb->flags == MMU_USER_IDX) {
--    CPUArchId *archid;
++    if (ctx->mem_idx == MMU_USER_IDX) {
--    CPUState *cs;
+         generate_exception(ctx, EXCCODE_IPE);
-+    IPICore ipi, *found;
+         return true;
+     }
--    archid = find_cpu_by_archid(machine, arch_id);
+diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
--    if (archid && archid->cpu) {
+index XXXXXXX..XXXXXXX 100644
--        cs = archid->cpu;
+--- a/target/loongarch/translate.c
-+    ipi.arch_id = arch_id;
++++ b/target/loongarch/translate.c
-+    found = bsearch(&ipi, lics->cpu, lics->num_cpu, sizeof(IPICore),
+@@ -XXX,XX +XXX,XX @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
-+                    loongarch_ipi_cmp);
+     DisasContext *ctx = container_of(dcbase, DisasContext, base);
-+    if (found && found->cpu) {
-         if (index) {
+     ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
--            *index = cs->cpu_index;
+-    ctx->mem_idx = ctx->base.tb->flags;
-+            *index = found - lics->cpu;
++    if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) {
-         }
++        ctx->mem_idx = ctx->base.tb->flags & HW_FLAGS_PLV_MASK;
++    } else {
-         if (pcs) {
++        ctx->mem_idx = MMU_DA_IDX;
--            *pcs = cs;
++    }
-+            *pcs = found->cpu;
-         }
+     /* Bound the number of insns to execute to those left on the page.  */
+     bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
          return MEMTX_OK;
 --
-.43.5
+.31.1

-[PULL 5/8] hw/intc/loongarch_ipi: Get cpu number from possible_cpu_arch_ids
+[PULL v2 9/9] target/loongarch: Fix emulation of float-point disable exception
-Supported CPU number can be acquired from function
+From: Rui Wang <wangrui@loongson.cn>
 possible_cpu_arch_ids(), cpu-num property is not necessary and can
 be removed.
-Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+We need to emulate it to generate a floating point disable exception
-Reviewed-by: Bibo Mao <maobibo@loongson.cn>
+when CSR.EUEN.FPE is zero.
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Song Gao <gaosong@loongson.cn>
 Signed-off-by: Rui Wang <wangrui@loongson.cn>
 Message-Id: <20221104040517.222059-3-wangrui@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
- hw/intc/loongarch_ipi.c               | 13 ++++++++-----
+ target/loongarch/cpu.c                        |  2 ++
- include/hw/intc/loongson_ipi_common.h |  2 ++
+ target/loongarch/cpu.h                        |  2 ++
-files changed, 10 insertions(+), 5 deletions(-)
+ .../loongarch/insn_trans/trans_farith.c.inc   | 30 ++++++++++++++++
  target/loongarch/insn_trans/trans_fcmp.c.inc  | 11 ++++--
  .../loongarch/insn_trans/trans_fmemory.c.inc  | 34 +++++++++++++++----
  target/loongarch/insn_trans/trans_fmov.c.inc  | 29 ++++++++++++++--
 files changed, 97 insertions(+), 11 deletions(-)
-diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
+diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/loongarch_ipi.c
+--- a/target/loongarch/cpu.c
-+++ b/hw/intc/loongarch_ipi.c
++++ b/target/loongarch/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static const char * const excp_names[] = {
- {
+     [EXCCODE_BRK] = "Break",
-     LoongsonIPICommonState *lics = LOONGSON_IPI_COMMON(dev);
+     [EXCCODE_INE] = "Instruction Non-Existent",
-     LoongarchIPIClass *lic = LOONGARCH_IPI_GET_CLASS(dev);
+     [EXCCODE_IPE] = "Instruction privilege error",
-+    MachineState *machine = MACHINE(qdev_get_machine());
++    [EXCCODE_FPD] = "Floating Point Disabled",
-+    MachineClass *mc = MACHINE_GET_CLASS(machine);
+     [EXCCODE_FPE] = "Floating Point Exception",
-+    const CPUArchIdList *id_list;
+     [EXCCODE_DBP] = "Debug breakpoint",
-     Error *local_err = NULL;
+     [EXCCODE_BCE] = "Bound Check Exception",
-     int i;
+@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
+     case EXCCODE_BRK:
-@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
+     case EXCCODE_INE:
-         return;
+     case EXCCODE_IPE:
-     }
++    case EXCCODE_FPD:
+     case EXCCODE_FPE:
--    if (lics->num_cpu == 0) {
+     case EXCCODE_BCE:
--        error_setg(errp, "num-cpu must be at least 1");
+         env->CSR_BADV = env->pc;
--        return;
+diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
--    }
+index XXXXXXX..XXXXXXX 100644
--
+--- a/target/loongarch/cpu.h
-+    assert(mc->possible_cpu_arch_ids);
++++ b/target/loongarch/cpu.h
-+    id_list = mc->possible_cpu_arch_ids(machine);
+@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
-+    lics->num_cpu = id_list->len;
+  */
-     lics->cpu = g_new0(IPICore, lics->num_cpu);
+ #define HW_FLAGS_PLV_MASK   R_CSR_CRMD_PLV_MASK  /* 0x03 */
-     for (i = 0; i < lics->num_cpu; i++) {
+ #define HW_FLAGS_CRMD_PG    R_CSR_CRMD_PG_MASK   /* 0x10 */
-+        lics->cpu[i].arch_id = id_list->cpus[i].arch_id;
++#define HW_FLAGS_EUEN_FPE   0x04
-+        lics->cpu[i].cpu = CPU(id_list->cpus[i].cpu);
-         lics->cpu[i].ipi = lics;
+ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
-         qdev_init_gpio_out(dev, &lics->cpu[i].irq, 1);
+                                         target_ulong *pc,
-     }
+@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
-diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h
+     *pc = env->pc;
-index XXXXXXX..XXXXXXX 100644
+     *cs_base = 0;
---- a/include/hw/intc/loongson_ipi_common.h
+     *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
-+++ b/include/hw/intc/loongson_ipi_common.h
++    *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
-@@ -XXX,XX +XXX,XX @@ typedef struct IPICore {
+ }
-     /* 64bit buf divide into 2 32-bit buf */
-     uint32_t buf[IPI_MBX_NUM * 2];
+ void loongarch_cpu_list(void);
-     qemu_irq irq;
+diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loongarch/insn_trans/trans_farith.c.inc
-+    uint64_t arch_id;
+index XXXXXXX..XXXXXXX 100644
-+    CPUState *cpu;
+--- a/target/loongarch/insn_trans/trans_farith.c.inc
- } IPICore;
++++ b/target/loongarch/insn_trans/trans_farith.c.inc
+@@ -XXX,XX +XXX,XX @@
- struct LoongsonIPICommonState {
+  * Copyright (c) 2021 Loongson Technology Corporation Limited
   */
 +#ifndef CONFIG_USER_ONLY
 +#define CHECK_FPE do { \
 +    if ((ctx->base.tb->flags & HW_FLAGS_EUEN_FPE) == 0) { \
 +        generate_exception(ctx, EXCCODE_FPD); \
 +        return false; \
 +    } \
 +} while (0)
 +#else
 +#define CHECK_FPE
 +#endif
 +
  static bool gen_fff(DisasContext *ctx, arg_fff *a,
                      void (*func)(TCGv, TCGv_env, TCGv, TCGv))
  {
 +    CHECK_FPE;
 +
      func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk]);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool gen_fff(DisasContext *ctx, arg_fff *a,
  static bool gen_ff(DisasContext *ctx, arg_ff *a,
                     void (*func)(TCGv, TCGv_env, TCGv))
  {
 +    CHECK_FPE;
 +
      func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj]);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool gen_muladd(DisasContext *ctx, arg_ffff *a,
                         int flag)
  {
      TCGv_i32 tflag = tcg_constant_i32(flag);
 +
 +    CHECK_FPE;
 +
      func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj],
           cpu_fpr[a->fk], cpu_fpr[a->fa], tflag);
      return true;
@@ -XXX,XX +XXX,XX @@ static bool gen_muladd(DisasContext *ctx, arg_ffff *a,
  static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a)
  {
 +    CHECK_FPE;
 +
      tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0, 31);
      return true;
  }
  static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a)
  {
 +    CHECK_FPE;
 +
      tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0, 63);
      return true;
  }
  static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a)
  {
 +    CHECK_FPE;
 +
      tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 31));
      gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
      return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a)
  static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a)
  {
 +    CHECK_FPE;
 +
      tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 63));
      return true;
  }
  static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a)
  {
 +    CHECK_FPE;
 +
      tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x80000000);
      gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
      return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a)
  static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a)
  {
 +    CHECK_FPE;
 +
      tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x8000000000000000LL);
      return true;
  }
 diff --git a/target/loongarch/insn_trans/trans_fcmp.c.inc b/target/loongarch/insn_trans/trans_fcmp.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/insn_trans/trans_fcmp.c.inc
 +++ b/target/loongarch/insn_trans/trans_fcmp.c.inc
@@ -XXX,XX +XXX,XX @@ static uint32_t get_fcmp_flags(int cond)
  static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
  {
 -    TCGv var = tcg_temp_new();
 +    TCGv var;
      uint32_t flags;
      void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
 +    CHECK_FPE;
 +
 +    var = tcg_temp_new();
      fn = (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s);
      flags = get_fcmp_flags(a->fcond >> 1);
@@ -XXX,XX +XXX,XX @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
  static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a)
  {
 -    TCGv var = tcg_temp_new();
 +    TCGv var;
      uint32_t flags;
      void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
 +
 +    CHECK_FPE;
 +
 +    var = tcg_temp_new();
      fn = (a->fcond & 1 ? gen_helper_fcmp_s_d : gen_helper_fcmp_c_d);
      flags = get_fcmp_flags(a->fcond >> 1);
 diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loongarch/insn_trans/trans_fmemory.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/insn_trans/trans_fmemory.c.inc
 +++ b/target/loongarch/insn_trans/trans_fmemory.c.inc
@@ -XXX,XX +XXX,XX @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
      TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
      TCGv temp = NULL;
 +    CHECK_FPE;
 +
      if (a->imm) {
          temp = tcg_temp_new();
          tcg_gen_addi_tl(temp, addr, a->imm);
@@ -XXX,XX +XXX,XX @@ static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
      TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
      TCGv temp = NULL;
 +    CHECK_FPE;
 +
      if (a->imm) {
          temp = tcg_temp_new();
          tcg_gen_addi_tl(temp, addr, a->imm);
@@ -XXX,XX +XXX,XX @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, MemOp mop)
  {
      TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
      TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
 -    TCGv addr = tcg_temp_new();
 +    TCGv addr;
 +    CHECK_FPE;
 +
 +    addr = tcg_temp_new();
      tcg_gen_add_tl(addr, src1, src2);
      tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
      maybe_nanbox_load(cpu_fpr[a->fd], mop);
@@ -XXX,XX +XXX,XX @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, MemOp mop)
  {
      TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
      TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
 -    TCGv addr = tcg_temp_new();
 +    TCGv addr;
 +
 +    CHECK_FPE;
 +    addr = tcg_temp_new();
      tcg_gen_add_tl(addr, src1, src2);
      tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
      tcg_temp_free(addr);
@@ -XXX,XX +XXX,XX @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
  {
      TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
      TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
 -    TCGv addr = tcg_temp_new();
 +    TCGv addr;
 +    CHECK_FPE;
 +
 +    addr = tcg_temp_new();
      gen_helper_asrtgt_d(cpu_env, src1, src2);
      tcg_gen_add_tl(addr, src1, src2);
      tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
@@ -XXX,XX +XXX,XX @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
  {
      TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
      TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
 -    TCGv addr = tcg_temp_new();
 +    TCGv addr;
 +
 +    CHECK_FPE;
 +    addr = tcg_temp_new();
      gen_helper_asrtgt_d(cpu_env, src1, src2);
      tcg_gen_add_tl(addr, src1, src2);
      tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
@@ -XXX,XX +XXX,XX @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a, MemOp mop)
  {
      TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
      TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
 -    TCGv addr = tcg_temp_new();
 +    TCGv addr;
 +    CHECK_FPE;
 +
 +    addr = tcg_temp_new();
      gen_helper_asrtle_d(cpu_env, src1, src2);
      tcg_gen_add_tl(addr, src1, src2);
      tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
@@ -XXX,XX +XXX,XX @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop)
  {
      TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
      TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
 -    TCGv addr = tcg_temp_new();
 +    TCGv addr;
 +
 +    CHECK_FPE;
 +    addr = tcg_temp_new();
      gen_helper_asrtle_d(cpu_env, src1, src2);
      tcg_gen_add_tl(addr, src1, src2);
      tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
 diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarch/insn_trans/trans_fmov.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/insn_trans/trans_fmov.c.inc
 +++ b/target/loongarch/insn_trans/trans_fmov.c.inc
@@ -XXX,XX +XXX,XX @@ static const uint32_t fcsr_mask[4] = {
  static bool trans_fsel(DisasContext *ctx, arg_fsel *a)
  {
      TCGv zero = tcg_constant_tl(0);
 -    TCGv cond = tcg_temp_new();
 +    TCGv cond;
 +    CHECK_FPE;
 +
 +    cond = tcg_temp_new();
      tcg_gen_ld8u_tl(cond, cpu_env, offsetof(CPULoongArchState, cf[a->ca]));
      tcg_gen_movcond_tl(TCG_COND_EQ, cpu_fpr[a->fd], cond, zero,
                         cpu_fpr[a->fj], cpu_fpr[a->fk]);
@@ -XXX,XX +XXX,XX @@ static bool gen_f2f(DisasContext *ctx, arg_ff *a,
      TCGv dest = cpu_fpr[a->fd];
      TCGv src = cpu_fpr[a->fj];
 +    CHECK_FPE;
 +
      func(dest, src);
      if (nanbox) {
          gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
@@ -XXX,XX +XXX,XX @@ static bool gen_r2f(DisasContext *ctx, arg_fr *a,
  {
      TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
 +    CHECK_FPE;
 +
      func(cpu_fpr[a->fd], src);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool gen_f2r(DisasContext *ctx, arg_rf *a,
  {
      TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
 +    CHECK_FPE;
 +
      func(dest, cpu_fpr[a->fj]);
      gen_set_gpr(a->rd, dest, EXT_NONE);
@@ -XXX,XX +XXX,XX @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr2fcsr *a)
      uint32_t mask = fcsr_mask[a->fcsrd];
      TCGv Rj = gpr_src(ctx, a->rj, EXT_NONE);
 +    CHECK_FPE;
 +
      if (mask == UINT32_MAX) {
          tcg_gen_st32_i64(Rj, cpu_env, offsetof(CPULoongArchState, fcsr0));
      } else {
@@ -XXX,XX +XXX,XX @@ static bool trans_movfcsr2gr(DisasContext *ctx, arg_movfcsr2gr *a)
  {
      TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
 +    CHECK_FPE;
 +
      tcg_gen_ld32u_i64(dest, cpu_env, offsetof(CPULoongArchState, fcsr0));
      tcg_gen_andi_i64(dest, dest, fcsr_mask[a->fcsrs]);
      gen_set_gpr(a->rd, dest, EXT_NONE);
@@ -XXX,XX +XXX,XX @@ static void gen_movfrh2gr_s(TCGv dest, TCGv src)
  static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a)
  {
 -    TCGv t0 = tcg_temp_new();
 +    TCGv t0;
 +
 +    CHECK_FPE;
 +    t0 = tcg_temp_new();
      tcg_gen_andi_tl(t0, cpu_fpr[a->fj], 0x1);
      tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
      tcg_temp_free(t0);
@@ -XXX,XX +XXX,XX @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a)
  static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a)
  {
 +    CHECK_FPE;
 +
      tcg_gen_ld8u_tl(cpu_fpr[a->fd], cpu_env,
                      offsetof(CPULoongArchState, cf[a->cj & 0x7]));
      return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a)
  static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a)
  {
 -    TCGv t0 = tcg_temp_new();
 +    TCGv t0;
 +    CHECK_FPE;
 +
 +    t0 = tcg_temp_new();
      tcg_gen_andi_tl(t0, gpr_src(ctx, a->rj, EXT_NONE), 0x1);
      tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
      tcg_temp_free(t0);
@@ -XXX,XX +XXX,XX @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a)
  static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)
  {
 +    CHECK_FPE;
 +
      tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), cpu_env,
                      offsetof(CPULoongArchState, cf[a->cj & 0x7]));
      return true;
 --
-.43.5
+.31.1

The following changes since commit 7433709a147706ad7d1956b15669279933d0f82b:

Merge tag 'hw-misc-20250113' of https://github.com/philmd/qemu into staging (2025-01-14 12:46:56 -0500)

are available in the Git repository at:

https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20250116

for you to fetch changes up to bb81f237401b5f89f6bba21d9d4f50e0073372a6:

hw/intc/loongarch_ipi: Use alternative implemation for cpu_by_arch_id (2025-01-15 14:36:19 +0800)

----------------------------------------------------------------
pull-loongarch-20250116 queue

----------------------------------------------------------------
Bibo Mao (7):
      hw/intc/loongarch_ipi: Implement realize interface
      hw/intc/loongson_ipi: Remove num_cpu from loongson_ipi_common
      hw/intc/loongson_ipi: Remove property num_cpu from loongson_ipi_common
      hw/intc/loongarch_ipi: Get cpu number from possible_cpu_arch_ids
      hw/intc/loongarch_ipi: Remove property num-cpu
      hw/intc/loongson_ipi: Add more input parameter for cpu_by_arch_id
      hw/intc/loongarch_ipi: Use alternative implemation for cpu_by_arch_id

Miao Hao (1):
      target/loongarch: Add page table walker support for debugger usage

hw/intc/loongarch_ipi.c               | 69 ++++++++++++++++++-------
 hw/intc/loongson_ipi.c                | 43 +++++++++++++++-
 hw/intc/loongson_ipi_common.c         | 41 +++++----------
 hw/loongarch/virt.c                   |  1 -
 include/hw/intc/loongarch_ipi.h       |  1 +
 include/hw/intc/loongson_ipi_common.h |  5 +-
 target/loongarch/cpu_helper.c         | 94 +++++++++++++++++++++++++++++++++--
 target/loongarch/internals.h          |  4 +-
 target/loongarch/tcg/tlb_helper.c     |  4 +-
 9 files changed, 203 insertions(+), 59 deletions(-)

From: Miao Hao <haomiao23s@ict.ac.cn>

When dump memory content with gva address, software page table walker is
necessary to get responding gpa address.

Here page table walker is added for debugger usage.

Signed-off-by: Miao Hao <haomiao23s@ict.ac.cn>
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/cpu_helper.c     | 94 +++++++++++++++++++++++++++++--
 target/loongarch/internals.h      |  4 +-
 target/loongarch/tcg/tlb_helper.c |  4 +-
 3 files changed, 94 insertions(+), 8 deletions(-)

diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool loongarch_tlb_search(CPULoongArchState *env, target_ulong vaddr,
     return false;
 }
 
+static int loongarch_page_table_walker(CPULoongArchState *env, hwaddr *physical,
+                                 int *prot, target_ulong address)
+{
+    CPUState *cs = env_cpu(env);
+    target_ulong index, phys;
+    uint64_t dir_base, dir_width;
+    uint64_t base;
+    int level;
+
+    if ((address >> 63) & 0x1) {
+        base = env->CSR_PGDH;
+    } else {
+        base = env->CSR_PGDL;
+    }
+    base &= TARGET_PHYS_MASK;
+
+    for (level = 4; level > 0; level--) {
+        get_dir_base_width(env, &dir_base, &dir_width, level);
+
+        if (dir_width == 0) {
+            continue;
+        }
+
+        /* get next level page directory */
+        index = (address >> dir_base) & ((1 << dir_width) - 1);
+        phys = base | index << 3;
+        base = ldq_phys(cs->as, phys) & TARGET_PHYS_MASK;
+        if (FIELD_EX64(base, TLBENTRY, HUGE)) {
+            /* base is a huge pte */
+            break;
+        }
+    }
+
+    /* pte */
+    if (FIELD_EX64(base, TLBENTRY, HUGE)) {
+        /* Huge Page. base is pte */
+        base = FIELD_DP64(base, TLBENTRY, LEVEL, 0);
+        base = FIELD_DP64(base, TLBENTRY, HUGE, 0);
+        if (FIELD_EX64(base, TLBENTRY, HGLOBAL)) {
+            base = FIELD_DP64(base, TLBENTRY, HGLOBAL, 0);
+            base = FIELD_DP64(base, TLBENTRY, G, 1);
+        }
+    } else {
+        /* Normal Page. base points to pte */
+        get_dir_base_width(env, &dir_base, &dir_width, 0);
+        index = (address >> dir_base) & ((1 << dir_width) - 1);
+        phys = base | index << 3;
+        base = ldq_phys(cs->as, phys);
+    }
+
+    /* TODO: check plv and other bits? */
+
+    /* base is pte, in normal pte format */
+    if (!FIELD_EX64(base, TLBENTRY, V)) {
+        return TLBRET_NOMATCH;
+    }
+
+    if (!FIELD_EX64(base, TLBENTRY, D)) {
+        *prot = PAGE_READ;
+    } else {
+        *prot = PAGE_READ | PAGE_WRITE;
+    }
+
+    /* get TARGET_PAGE_SIZE aligned physical address */
+    base += (address & TARGET_PHYS_MASK) & ((1 << dir_base) - 1);
+    /* mask RPLV, NX, NR bits */
+    base = FIELD_DP64(base, TLBENTRY_64, RPLV, 0);
+    base = FIELD_DP64(base, TLBENTRY_64, NX, 0);
+    base = FIELD_DP64(base, TLBENTRY_64, NR, 0);
+    /* mask other attribute bits */
+    *physical = base & TARGET_PAGE_MASK;
+
+    return 0;
+}
+
 static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
                                  int *prot, target_ulong address,
-                                 MMUAccessType access_type, int mmu_idx)
+                                 MMUAccessType access_type, int mmu_idx,
+                                 int is_debug)
 {
     int index, match;
 
@@ -XXX,XX +XXX,XX @@ static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
     if (match) {
         return loongarch_map_tlb_entry(env, physical, prot,
                                        address, access_type, index, mmu_idx);
+    } else if (is_debug) {
+        /*
+         * For debugger memory access, we want to do the map when there is a
+         * legal mapping, even if the mapping is not yet in TLB. return 0 if
+         * there is a valid map, else none zero.
+         */
+        return loongarch_page_table_walker(env, physical, prot, address);
     }
 
     return TLBRET_NOMATCH;
@@ -XXX,XX +XXX,XX @@ static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
 #else
 static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
                                  int *prot, target_ulong address,
-                                 MMUAccessType access_type, int mmu_idx)
+                                 MMUAccessType access_type, int mmu_idx,
+                                 int is_debug)
 {
     return TLBRET_NOMATCH;
 }
@@ -XXX,XX +XXX,XX @@ static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va,
 
 int get_physical_address(CPULoongArchState *env, hwaddr *physical,
                          int *prot, target_ulong address,
-                         MMUAccessType access_type, int mmu_idx)
+                         MMUAccessType access_type, int mmu_idx, int is_debug)
 {
     int user_mode = mmu_idx == MMU_USER_IDX;
     int kernel_mode = mmu_idx == MMU_KERNEL_IDX;
@@ -XXX,XX +XXX,XX @@ int get_physical_address(CPULoongArchState *env, hwaddr *physical,
 
     /* Mapped address */
     return loongarch_map_address(env, physical, prot, address,
-                                 access_type, mmu_idx);
+                                 access_type, mmu_idx, is_debug);
 }
 
 hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
@@ -XXX,XX +XXX,XX @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     int prot;
 
     if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD,
-                             cpu_mmu_index(cs, false)) != 0) {
+                             cpu_mmu_index(cs, false), 1) != 0) {
         return -1;
     }
     return phys_addr;
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -XXX,XX +XXX,XX @@ bool loongarch_tlb_search(CPULoongArchState *env, target_ulong vaddr,
                           int *index);
 int get_physical_address(CPULoongArchState *env, hwaddr *physical,
                          int *prot, target_ulong address,
-                         MMUAccessType access_type, int mmu_idx);
+                         MMUAccessType access_type, int mmu_idx, int is_debug);
+void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
+                               uint64_t *dir_width, target_ulong level);
 hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 
 #ifdef CONFIG_TCG
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/log.h"
 #include "cpu-csr.h"
 
-static void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
+void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
                                uint64_t *dir_width, target_ulong level)
 {
     switch (level) {
@@ -XXX,XX +XXX,XX @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
     /* Data access */
     ret = get_physical_address(env, &physical, &prot, address,
-                               access_type, mmu_idx);
+                               access_type, mmu_idx, 0);
 
     if (ret == TLBRET_MATCH) {
         tlb_set_page(cs, address & TARGET_PAGE_MASK,
-- 
2.43.5

Add realize interface for loongarch ipi device.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
---
 hw/intc/loongarch_ipi.c         | 19 +++++++++++++++++++
 include/hw/intc/loongarch_ipi.h |  1 +
 2 files changed, 20 insertions(+)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "hw/boards.h"
+#include "qapi/error.h"
 #include "hw/intc/loongarch_ipi.h"
 #include "target/loongarch/cpu.h"
 
@@ -XXX,XX +XXX,XX @@ static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id)
     return NULL;
 }
 
+static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
+{
+    LoongarchIPIClass *lic = LOONGARCH_IPI_GET_CLASS(dev);
+    Error *local_err = NULL;
+
+    lic->parent_realize(dev, &local_err);
+    if (local_err) {
+        error_propagate(errp, local_err);
+        return;
+    }
+}
+
 static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
 {
     LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
+    LoongarchIPIClass *lic = LOONGARCH_IPI_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
 
+    device_class_set_parent_realize(dc, loongarch_ipi_realize,
+                                    &lic->parent_realize);
     licc->get_iocsr_as = get_iocsr_as;
     licc->cpu_by_arch_id = loongarch_cpu_by_arch_id;
 }
@@ -XXX,XX +XXX,XX @@ static const TypeInfo loongarch_ipi_types[] = {
     {
         .name               = TYPE_LOONGARCH_IPI,
         .parent             = TYPE_LOONGSON_IPI_COMMON,
+        .instance_size      = sizeof(LoongarchIPIState),
+        .class_size         = sizeof(LoongarchIPIClass),
         .class_init         = loongarch_ipi_class_init,
     }
 };
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongarch_ipi.h
+++ b/include/hw/intc/loongarch_ipi.h
@@ -XXX,XX +XXX,XX @@ struct LoongarchIPIState {
 
 struct LoongarchIPIClass {
     LoongsonIPICommonClass parent_class;
+    DeviceRealize parent_realize;
 };
 
 #endif
-- 
2.43.5

With mips64 loongson ipi, num_cpu property is used. With loongarch
ipi, num_cpu can be acquired from possible_cpu_arch_ids.

Here remove num_cpu setting from loongson_ipi_common, and this piece
of code is put into loongson and loongarch ipi separately.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
---
 hw/intc/loongarch_ipi.c       | 13 +++++++++++++
 hw/intc/loongson_ipi.c        | 14 +++++++++++++-
 hw/intc/loongson_ipi_common.c | 14 --------------
 3 files changed, 26 insertions(+), 15 deletions(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -XXX,XX +XXX,XX @@ static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id)
 
 static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
 {
+    LoongsonIPICommonState *lics = LOONGSON_IPI_COMMON(dev);
     LoongarchIPIClass *lic = LOONGARCH_IPI_GET_CLASS(dev);
     Error *local_err = NULL;
+    int i;
 
     lic->parent_realize(dev, &local_err);
     if (local_err) {
         error_propagate(errp, local_err);
         return;
     }
+
+    if (lics->num_cpu == 0) {
+        error_setg(errp, "num-cpu must be at least 1");
+        return;
+    }
+
+    lics->cpu = g_new0(IPICore, lics->num_cpu);
+    for (i = 0; i < lics->num_cpu; i++) {
+        lics->cpu[i].ipi = lics;
+        qdev_init_gpio_out(dev, &lics->cpu[i].irq, 1);
+    }
 }
 
 static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp)
     LoongsonIPIClass *lic = LOONGSON_IPI_GET_CLASS(dev);
     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
     Error *local_err = NULL;
+    int i;
 
     lic->parent_realize(dev, &local_err);
     if (local_err) {
@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp)
         return;
     }
 
+    if (sc->num_cpu == 0) {
+        error_setg(errp, "num-cpu must be at least 1");
+        return;
+    }
+
+    sc->cpu = g_new0(IPICore, sc->num_cpu);
+    for (i = 0; i < sc->num_cpu; i++) {
+        sc->cpu[i].ipi = sc;
+        qdev_init_gpio_out(dev, &sc->cpu[i].irq, 1);
+    }
+
     s->ipi_mmio_mem = g_new0(MemoryRegion, sc->num_cpu);
-    for (unsigned i = 0; i < sc->num_cpu; i++) {
+    for (i = 0; i < sc->num_cpu; i++) {
         g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i);
 
         memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev),
diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongson_ipi_common.c
+++ b/hw/intc/loongson_ipi_common.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/intc/loongson_ipi_common.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
-#include "qapi/error.h"
 #include "qemu/log.h"
 #include "migration/vmstate.h"
 #include "trace.h"
@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
 {
     LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev);
     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
-    int i;
-
-    if (s->num_cpu == 0) {
-        error_setg(errp, "num-cpu must be at least 1");
-        return;
-    }
 
     memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev),
                           &loongson_ipi_iocsr_ops,
@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
                           &loongson_ipi64_ops,
                           s, "loongson_ipi64_iocsr", 0x118);
     sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem);
-
-    s->cpu = g_new0(IPICore, s->num_cpu);
-    for (i = 0; i < s->num_cpu; i++) {
-        s->cpu[i].ipi = s;
-
-        qdev_init_gpio_out(dev, &s->cpu[i].irq, 1);
-    }
 }
 
 static void loongson_ipi_common_unrealize(DeviceState *dev)
-- 
2.43.5

With mips64 loongson ipi, num_cpu property is used. With loongarch
ipi, num_cpu can be acquired from possible_cpu_arch_ids.

Here remove property num_cpu from loongson_ipi_common, and put it into
loongson and loongarch ipi separately.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
---
 hw/intc/loongarch_ipi.c       | 6 ++++++
 hw/intc/loongson_ipi.c        | 6 ++++++
 hw/intc/loongson_ipi_common.c | 6 ------
 3 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "qapi/error.h"
 #include "hw/intc/loongarch_ipi.h"
+#include "hw/qdev-properties.h"
 #include "target/loongarch/cpu.h"
 
 static AddressSpace *get_iocsr_as(CPUState *cpu)
@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
     }
 }
 
+static const Property loongarch_ipi_properties[] = {
+    DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1),
+};
+
 static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
 {
     LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
 
     device_class_set_parent_realize(dc, loongarch_ipi_realize,
                                     &lic->parent_realize);
+    device_class_set_props(dc, loongarch_ipi_properties);
     licc->get_iocsr_as = get_iocsr_as;
     licc->cpu_by_arch_id = loongarch_cpu_by_arch_id;
 }
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "hw/intc/loongson_ipi.h"
+#include "hw/qdev-properties.h"
 #include "qapi/error.h"
 #include "target/mips/cpu.h"
 
@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_unrealize(DeviceState *dev)
     k->parent_unrealize(dev);
 }
 
+static const Property loongson_ipi_properties[] = {
+    DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1),
+};
+
 static void loongson_ipi_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data)
                                     &lic->parent_realize);
     device_class_set_parent_unrealize(dc, loongson_ipi_unrealize,
                                       &lic->parent_unrealize);
+    device_class_set_props(dc, loongson_ipi_properties);
     licc->get_iocsr_as = get_iocsr_as;
     licc->cpu_by_arch_id = cpu_by_arch_id;
 }
diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongson_ipi_common.c
+++ b/hw/intc/loongson_ipi_common.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/intc/loongson_ipi_common.h"
 #include "hw/irq.h"
-#include "hw/qdev-properties.h"
 #include "qemu/log.h"
 #include "migration/vmstate.h"
 #include "trace.h"
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongson_ipi_common = {
     }
 };
 
-static const Property ipi_common_properties[] = {
-    DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1),
-};
-
 static void loongson_ipi_common_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_common_class_init(ObjectClass *klass, void *data)
                                     &licc->parent_realize);
     device_class_set_parent_unrealize(dc, loongson_ipi_common_unrealize,
                                       &licc->parent_unrealize);
-    device_class_set_props(dc, ipi_common_properties);
     dc->vmsd = &vmstate_loongson_ipi_common;
 }
 
-- 
2.43.5

Supported CPU number can be acquired from function
possible_cpu_arch_ids(), cpu-num property is not necessary and can
be removed.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
---
 hw/intc/loongarch_ipi.c               | 13 ++++++++-----
 include/hw/intc/loongson_ipi_common.h |  2 ++
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
 {
     LoongsonIPICommonState *lics = LOONGSON_IPI_COMMON(dev);
     LoongarchIPIClass *lic = LOONGARCH_IPI_GET_CLASS(dev);
+    MachineState *machine = MACHINE(qdev_get_machine());
+    MachineClass *mc = MACHINE_GET_CLASS(machine);
+    const CPUArchIdList *id_list;
     Error *local_err = NULL;
     int i;
 
@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
         return;
     }
 
-    if (lics->num_cpu == 0) {
-        error_setg(errp, "num-cpu must be at least 1");
-        return;
-    }
-
+    assert(mc->possible_cpu_arch_ids);
+    id_list = mc->possible_cpu_arch_ids(machine);
+    lics->num_cpu = id_list->len;
     lics->cpu = g_new0(IPICore, lics->num_cpu);
     for (i = 0; i < lics->num_cpu; i++) {
+        lics->cpu[i].arch_id = id_list->cpus[i].arch_id;
+        lics->cpu[i].cpu = CPU(id_list->cpus[i].cpu);
         lics->cpu[i].ipi = lics;
         qdev_init_gpio_out(dev, &lics->cpu[i].irq, 1);
     }
diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -XXX,XX +XXX,XX @@ typedef struct IPICore {
     /* 64bit buf divide into 2 32-bit buf */
     uint32_t buf[IPI_MBX_NUM * 2];
     qemu_irq irq;
+    uint64_t arch_id;
+    CPUState *cpu;
 } IPICore;
 
 struct LoongsonIPICommonState {
-- 
2.43.5

Since cpu number can be acquired from possible_cpu_arch_ids(),
num-cpu property is not necessary. Here remove num-cpu property
for object TYPE_LOONGARCH_IPI object.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
---
 hw/intc/loongarch_ipi.c | 5 -----
 hw/loongarch/virt.c     | 1 -
 2 files changed, 6 deletions(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
     }
 }
 
-static const Property loongarch_ipi_properties[] = {
-    DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1),
-};
-
 static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
 {
     LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
 
     device_class_set_parent_realize(dc, loongarch_ipi_realize,
                                     &lic->parent_realize);
-    device_class_set_props(dc, loongarch_ipi_properties);
     licc->get_iocsr_as = get_iocsr_as;
     licc->cpu_by_arch_id = loongarch_cpu_by_arch_id;
 }
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
 
     /* Create IPI device */
     ipi = qdev_new(TYPE_LOONGARCH_IPI);
-    qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
 
     /* IPI iocsr memory region */
-- 
2.43.5

Add logic cpu index input parameter for function cpu_by_arch_id,
CPUState::cpu_index is logic cpu slot index for possible_cpus.

At the same time it is logic index with LoongsonIPICommonState::IPICore,
here hide access for CPUState::cpu_index directly, it comes from
function cpu_by_arch_id().

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
---
 hw/intc/loongarch_ipi.c               | 19 +++++++++++++++----
 hw/intc/loongson_ipi.c                | 23 ++++++++++++++++++++++-
 hw/intc/loongson_ipi_common.c         | 21 ++++++++++++---------
 include/hw/intc/loongson_ipi_common.h |  3 ++-
 4 files changed, 51 insertions(+), 15 deletions(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -XXX,XX +XXX,XX @@ static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
     return found_cpu;
 }
 
-static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id)
+static int loongarch_cpu_by_arch_id(LoongsonIPICommonState *lics,
+                                    int64_t arch_id, int *index, CPUState **pcs)
 {
     MachineState *machine = MACHINE(qdev_get_machine());
     CPUArchId *archid;
+    CPUState *cs;
 
     archid = find_cpu_by_archid(machine, arch_id);
-    if (archid) {
-        return CPU(archid->cpu);
+    if (archid && archid->cpu) {
+        cs = archid->cpu;
+        if (index) {
+            *index = cs->cpu_index;
+        }
+
+        if (pcs) {
+            *pcs = cs;
+        }
+
+        return MEMTX_OK;
     }
 
-    return NULL;
+    return MEMTX_ERROR;
 }
 
 static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -XXX,XX +XXX,XX @@ static AddressSpace *get_iocsr_as(CPUState *cpu)
     return NULL;
 }
 
+static int loongson_cpu_by_arch_id(LoongsonIPICommonState *lics,
+                                   int64_t arch_id, int *index, CPUState **pcs)
+{
+    CPUState *cs;
+
+    cs = cpu_by_arch_id(arch_id);
+    if (cs == NULL) {
+        return MEMTX_ERROR;
+    }
+
+    if (index) {
+        *index = cs->cpu_index;
+    }
+
+    if (pcs) {
+        *pcs = cs;
+    }
+
+    return MEMTX_OK;
+}
+
 static const MemoryRegionOps loongson_ipi_core_ops = {
     .read_with_attrs = loongson_ipi_core_readl,
     .write_with_attrs = loongson_ipi_core_writel,
@@ -XXX,XX +XXX,XX @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data)
                                       &lic->parent_unrealize);
     device_class_set_props(dc, loongson_ipi_properties);
     licc->get_iocsr_as = get_iocsr_as;
-    licc->cpu_by_arch_id = cpu_by_arch_id;
+    licc->cpu_by_arch_id = loongson_cpu_by_arch_id;
 }
 
 static const TypeInfo loongson_ipi_types[] = {
diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongson_ipi_common.c
+++ b/hw/intc/loongson_ipi_common.c
@@ -XXX,XX +XXX,XX @@ static MemTxResult mail_send(LoongsonIPICommonState *ipi,
     uint32_t cpuid;
     hwaddr addr;
     CPUState *cs;
+    int cpu, ret;
 
     cpuid = extract32(val, 16, 10);
-    cs = licc->cpu_by_arch_id(cpuid);
-    if (cs == NULL) {
+    ret = licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs);
+    if (ret != MEMTX_OK) {
         return MEMTX_DECODE_ERROR;
     }
 
     /* override requester_id */
     addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
-    attrs.requester_id = cs->cpu_index;
+    attrs.requester_id = cpu;
     return send_ipi_data(ipi, cs, val, addr, attrs);
 }
 
@@ -XXX,XX +XXX,XX @@ static MemTxResult any_send(LoongsonIPICommonState *ipi,
     uint32_t cpuid;
     hwaddr addr;
     CPUState *cs;
+    int cpu, ret;
 
     cpuid = extract32(val, 16, 10);
-    cs = licc->cpu_by_arch_id(cpuid);
-    if (cs == NULL) {
+    ret = licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs);
+    if (ret != MEMTX_OK) {
         return MEMTX_DECODE_ERROR;
     }
 
     /* override requester_id */
     addr = val & 0xffff;
-    attrs.requester_id = cs->cpu_index;
+    attrs.requester_id = cpu;
     return send_ipi_data(ipi, cs, val, addr, attrs);
 }
 
@@ -XXX,XX +XXX,XX @@ MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
     uint32_t cpuid;
     uint8_t vector;
     CPUState *cs;
+    int cpu, ret;
 
     addr &= 0xff;
     trace_loongson_ipi_write(size, (uint64_t)addr, val);
@@ -XXX,XX +XXX,XX @@ MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
         cpuid = extract32(val, 16, 10);
         /* IPI status vector */
         vector = extract8(val, 0, 5);
-        cs = licc->cpu_by_arch_id(cpuid);
-        if (cs == NULL || cs->cpu_index >= ipi->num_cpu) {
+        ret = licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs);
+        if (ret != MEMTX_OK || cpu >= ipi->num_cpu) {
             return MEMTX_DECODE_ERROR;
         }
-        loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF,
+        loongson_ipi_core_writel(&ipi->cpu[cpu], CORE_SET_OFF,
                                  BIT(vector), 4, attrs);
         break;
     default:
diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -XXX,XX +XXX,XX @@ struct LoongsonIPICommonClass {
     DeviceRealize parent_realize;
     DeviceUnrealize parent_unrealize;
     AddressSpace *(*get_iocsr_as)(CPUState *cpu);
-    CPUState *(*cpu_by_arch_id)(int64_t id);
+    int (*cpu_by_arch_id)(LoongsonIPICommonState *lics, int64_t id,
+                          int *index, CPUState **pcs);
 };
 
 MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
-- 
2.43.5

There is arch_id and CPUState pointer in IPICore object. With function
cpu_by_arch_id() it can be implemented by parsing IPICore array inside,
rather than possible_cpus array.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
---
 hw/intc/loongarch_ipi.c | 36 +++++++++++-------------------------
 1 file changed, 11 insertions(+), 25 deletions(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -XXX,XX +XXX,XX @@ static AddressSpace *get_iocsr_as(CPUState *cpu)
     return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
 }
 
-static int archid_cmp(const void *a, const void *b)
+static int loongarch_ipi_cmp(const void *a, const void *b)
 {
-   CPUArchId *archid_a = (CPUArchId *)a;
-   CPUArchId *archid_b = (CPUArchId *)b;
+   IPICore *ipi_a = (IPICore *)a;
+   IPICore *ipi_b = (IPICore *)b;
 
-   return archid_a->arch_id - archid_b->arch_id;
-}
-
-static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
-{
-    CPUArchId apic_id, *found_cpu;
-
-    apic_id.arch_id = id;
-    found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
-                        ms->possible_cpus->len,
-                        sizeof(*ms->possible_cpus->cpus),
-                        archid_cmp);
-
-    return found_cpu;
+   return ipi_a->arch_id - ipi_b->arch_id;
 }
 
 static int loongarch_cpu_by_arch_id(LoongsonIPICommonState *lics,
                                     int64_t arch_id, int *index, CPUState **pcs)
 {
-    MachineState *machine = MACHINE(qdev_get_machine());
-    CPUArchId *archid;
-    CPUState *cs;
+    IPICore ipi, *found;
 
-    archid = find_cpu_by_archid(machine, arch_id);
-    if (archid && archid->cpu) {
-        cs = archid->cpu;
+    ipi.arch_id = arch_id;
+    found = bsearch(&ipi, lics->cpu, lics->num_cpu, sizeof(IPICore),
+                    loongarch_ipi_cmp);
+    if (found && found->cpu) {
         if (index) {
-            *index = cs->cpu_index;
+            *index = found - lics->cpu;
         }
 
         if (pcs) {
-            *pcs = cs;
+            *pcs = found->cpu;
         }
 
         return MEMTX_OK;
-- 
2.43.5

The following changes since commit ece5f8374d0416a339f0c0a9399faa2c42d4ad6f:

Merge tag 'linux-user-for-7.2-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2022-11-03 10:55:05 -0400)

are available in the Git repository at:

https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20221104

for you to fetch changes up to 2419978cb09e11bc53a07d4de5621424d2a6a86d:

target/loongarch: Fix emulation of float-point disable exception (2022-11-04 17:10:53 +0800)

----------------------------------------------------------------
pull-loongarch-20221104

v2:
 - fix win32/win64 complie error;
 - Add Rui Wang' patches.

----------------------------------------------------------------
Rui Wang (2):
      target/loongarch: Adjust the layout of hardware flags bit fields
      target/loongarch: Fix emulation of float-point disable exception

Song Gao (2):
      target/loongarch: Add exception subcode
      target/loongarch: Fix raise_mmu_exception() set wrong exception_index

Xiaojuan Yang (5):
      hw/intc: Convert the memops to with_attrs in LoongArch extioi
      hw/intc: Fix LoongArch extioi coreisr accessing
      hw/loongarch: Load FDT table into dram memory space
      hw/loongarch: Improve fdt for LoongArch virt machine
      hw/loongarch: Add TPM device for LoongArch virt machine

hw/intc/loongarch_extioi.c                         | 41 +++++++------
 hw/intc/trace-events                               |  3 +-
 hw/loongarch/acpi-build.c                          | 51 +++++++++++++++-
 hw/loongarch/virt.c                                | 53 ++++++++++++++---
 include/hw/loongarch/virt.h                        |  3 -
 include/hw/pci-host/ls7a.h                         |  1 +
 target/loongarch/cpu.c                             | 10 +++-
 target/loongarch/cpu.h                             | 69 +++++++++++++---------
 target/loongarch/insn_trans/trans_farith.c.inc     | 30 ++++++++++
 target/loongarch/insn_trans/trans_fcmp.c.inc       | 11 +++-
 target/loongarch/insn_trans/trans_fmemory.c.inc    | 34 +++++++++--
 target/loongarch/insn_trans/trans_fmov.c.inc       | 29 ++++++++-
 target/loongarch/insn_trans/trans_privileged.c.inc |  2 +-
 target/loongarch/iocsr_helper.c                    | 19 +++---
 target/loongarch/tlb_helper.c                      |  5 +-
 target/loongarch/translate.c                       |  6 +-
 16 files changed, 283 insertions(+), 84 deletions(-)

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Converting the MemoryRegionOps read/write handlers to
with_attrs in LoongArch extioi emulation.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221021015307.2570844-2-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/intc/loongarch_extioi.c | 31 +++++++++++++++++--------------
 hw/intc/trace-events       |  3 +--
 2 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_extioi.c
+++ b/hw/intc/loongarch_extioi.c
@@ -XXX,XX +XXX,XX @@ static void extioi_setirq(void *opaque, int irq, int level)
     extioi_update_irq(s, irq, level);
 }
 
-static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size)
+static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
+                                unsigned size, MemTxAttrs attrs)
 {
     LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
     unsigned long offset = addr & 0xffff;
-    uint32_t index, cpu, ret = 0;
+    uint32_t index, cpu;
 
     switch (offset) {
     case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
         index = (offset - EXTIOI_NODETYPE_START) >> 2;
-        ret = s->nodetype[index];
+        *data = s->nodetype[index];
         break;
     case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
         index = (offset - EXTIOI_IPMAP_START) >> 2;
-        ret = s->ipmap[index];
+        *data = s->ipmap[index];
         break;
     case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
         index = (offset - EXTIOI_ENABLE_START) >> 2;
-        ret = s->enable[index];
+        *data = s->enable[index];
         break;
     case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:
         index = (offset - EXTIOI_BOUNCE_START) >> 2;
-        ret = s->bounce[index];
+        *data = s->bounce[index];
         break;
     case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
         index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
         cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
-        ret = s->coreisr[cpu][index];
+        *data = s->coreisr[cpu][index];
         break;
     case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
         index = (offset - EXTIOI_COREMAP_START) >> 2;
-        ret = s->coremap[index];
+        *data = s->coremap[index];
         break;
     default:
         break;
     }
 
-    trace_loongarch_extioi_readw(addr, ret);
-    return ret;
+    trace_loongarch_extioi_readw(addr, *data);
+    return MEMTX_OK;
 }
 
 static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
@@ -XXX,XX +XXX,XX @@ static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
     }
 }
 
-static void extioi_writew(void *opaque, hwaddr addr,
-                          uint64_t val, unsigned size)
+static MemTxResult extioi_writew(void *opaque, hwaddr addr,
+                          uint64_t val, unsigned size,
+                          MemTxAttrs attrs)
 {
     LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
     int i, cpu, index, old_data, irq;
@@ -XXX,XX +XXX,XX @@ static void extioi_writew(void *opaque, hwaddr addr,
     default:
         break;
     }
+    return MEMTX_OK;
 }
 
 static const MemoryRegionOps extioi_ops = {
-    .read = extioi_readw,
-    .write = extioi_writew,
+    .read_with_attrs = extioi_readw,
+    .write_with_attrs = extioi_writew,
     .impl.min_access_size = 4,
     .impl.max_access_size = 4,
     .valid.min_access_size = 4,
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -XXX,XX +XXX,XX @@ loongarch_msi_set_irq(int irq_num) "set msi irq %d"
 
 # loongarch_extioi.c
 loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d"
-loongarch_extioi_readw(uint64_t addr, uint32_t val) "addr: 0x%"PRIx64 "val: 0x%x"
+loongarch_extioi_readw(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
 loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
-
-- 
2.31.1

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

1. When cpu read or write extioi COREISR reg, it should access
the reg belonged to itself, so the cpu index of 's->coreisr'
is current cpu number. Using MemTxAttrs' requester_id to get
the cpu index.
2. it need not to mask 0x1f when calculate the coreisr array index.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221021015307.2570844-3-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/intc/loongarch_extioi.c      | 10 ++++++----
 target/loongarch/iocsr_helper.c | 19 +++++++++++--------
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_extioi.c
+++ b/hw/intc/loongarch_extioi.c
@@ -XXX,XX +XXX,XX @@ static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
         *data = s->bounce[index];
         break;
     case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
-        index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
-        cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
+        index = (offset - EXTIOI_COREISR_START) >> 2;
+        /* using attrs to get current cpu index */
+        cpu = attrs.requester_id;
         *data = s->coreisr[cpu][index];
         break;
     case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
@@ -XXX,XX +XXX,XX @@ static MemTxResult extioi_writew(void *opaque, hwaddr addr,
         s->bounce[index] = val;
         break;
     case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
-        index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
-        cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
+        index = (offset - EXTIOI_COREISR_START) >> 2;
+        /* using attrs to get current cpu index */
+        cpu = attrs.requester_id;
         old_data = s->coreisr[cpu][index];
         s->coreisr[cpu][index] = old_data & ~val;
         /* write 1 to clear interrrupt */
diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/iocsr_helper.c
+++ b/target/loongarch/iocsr_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/cpu_ldst.h"
 #include "tcg/tcg-ldst.h"
 
+#define GET_MEMTXATTRS(cas) \
+        ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})
+
 uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
 {
     return address_space_ldub(&env->address_space_iocsr, r_addr,
-                              MEMTXATTRS_UNSPECIFIED, NULL);
+                              GET_MEMTXATTRS(env), NULL);
 }
 
 uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
 {
     return address_space_lduw(&env->address_space_iocsr, r_addr,
-                              MEMTXATTRS_UNSPECIFIED, NULL);
+                              GET_MEMTXATTRS(env), NULL);
 }
 
 uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
 {
     return address_space_ldl(&env->address_space_iocsr, r_addr,
-                             MEMTXATTRS_UNSPECIFIED, NULL);
+                             GET_MEMTXATTRS(env), NULL);
 }
 
 uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)
 {
     return address_space_ldq(&env->address_space_iocsr, r_addr,
-                             MEMTXATTRS_UNSPECIFIED, NULL);
+                             GET_MEMTXATTRS(env), NULL);
 }
 
 void helper_iocsrwr_b(CPULoongArchState *env, target_ulong w_addr,
                       target_ulong val)
 {
     address_space_stb(&env->address_space_iocsr, w_addr,
-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
+                      val, GET_MEMTXATTRS(env), NULL);
 }
 
 void helper_iocsrwr_h(CPULoongArchState *env, target_ulong w_addr,
                       target_ulong val)
 {
     address_space_stw(&env->address_space_iocsr, w_addr,
-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
+                      val, GET_MEMTXATTRS(env), NULL);
 }
 
 void helper_iocsrwr_w(CPULoongArchState *env, target_ulong w_addr,
                       target_ulong val)
 {
     address_space_stl(&env->address_space_iocsr, w_addr,
-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
+                      val, GET_MEMTXATTRS(env), NULL);
 }
 
 void helper_iocsrwr_d(CPULoongArchState *env, target_ulong w_addr,
                       target_ulong val)
 {
     address_space_stq(&env->address_space_iocsr, w_addr,
-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
+                      val, GET_MEMTXATTRS(env), NULL);
 }
-- 
2.31.1

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Load FDT table into dram memory space, and the addr is 2 MiB.
Since lowmem region starts from 0, FDT base address is located
at 2 MiB to avoid NULL pointer access.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221028014007.2718352-2-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/loongarch/virt.c         | 18 +++++++++++-------
 include/hw/loongarch/virt.h |  3 ---
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pcie_node(const LoongArchMachineState *lams)
                                  1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
                                  2, base_mmio, 2, size_mmio);
     g_free(nodename);
-    qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size);
 }
 
 static void fdt_add_irqchip_node(LoongArchMachineState *lams)
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
     MemoryRegion *address_space_mem = get_system_memory();
     LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
     int i;
+    hwaddr fdt_base;
 
     if (!cpu_model) {
         cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
     lams->machine_done.notify = virt_machine_done;
     qemu_add_machine_init_done_notifier(&lams->machine_done);
     fdt_add_pcie_node(lams);
-
-    /* load fdt */
-    MemoryRegion *fdt_rom = g_new(MemoryRegion, 1);
-    memory_region_init_rom(fdt_rom, NULL, "fdt", VIRT_FDT_SIZE, &error_fatal);
-    memory_region_add_subregion(get_system_memory(), VIRT_FDT_BASE, fdt_rom);
-    rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, VIRT_FDT_BASE);
+    /*
+     * Since lowmem region starts from 0, FDT base address is located
+     * at 2 MiB to avoid NULL pointer access.
+     *
+     * Put the FDT into the memory map as a ROM image: this will ensure
+     * the FDT is copied again upon reset, even if addr points into RAM.
+     */
+    fdt_base = 2 * MiB;
+    qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size);
+    rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base);
 }
 
 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/loongarch/virt.h
+++ b/include/hw/loongarch/virt.h
@@ -XXX,XX +XXX,XX @@
 #define VIRT_GED_MEM_ADDR       (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN)
 #define VIRT_GED_REG_ADDR       (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN)
 
-#define VIRT_FDT_BASE           0x1c400000
-#define VIRT_FDT_SIZE           0x100000
-
 struct LoongArchMachineState {
     /*< private >*/
     MachineState parent_obj;
-- 
2.31.1

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Add new items into LoongArch FDT, including rtc and uart info.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221028014007.2718352-3-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/loongarch/virt.c        | 31 +++++++++++++++++++++++++++++++
 include/hw/pci-host/ls7a.h |  1 +
 2 files changed, 32 insertions(+)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/display/ramfb.h"
 #include "hw/mem/pc-dimm.h"
 
+static void fdt_add_rtc_node(LoongArchMachineState *lams)
+{
+    char *nodename;
+    hwaddr base = VIRT_RTC_REG_BASE;
+    hwaddr size = VIRT_RTC_LEN;
+    MachineState *ms = MACHINE(lams);
+
+    nodename = g_strdup_printf("/rtc@%" PRIx64, base);
+    qemu_fdt_add_subnode(ms->fdt, nodename);
+    qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc");
+    qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 0x0, base, size);
+    g_free(nodename);
+}
+
+static void fdt_add_uart_node(LoongArchMachineState *lams)
+{
+    char *nodename;
+    hwaddr base = VIRT_UART_BASE;
+    hwaddr size = VIRT_UART_SIZE;
+    MachineState *ms = MACHINE(lams);
+
+    nodename = g_strdup_printf("/serial@%" PRIx64, base);
+    qemu_fdt_add_subnode(ms->fdt, nodename);
+    qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a");
+    qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size);
+    qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000);
+    g_free(nodename);
+}
+
 static void create_fdt(LoongArchMachineState *lams)
 {
     MachineState *ms = MACHINE(lams);
@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
                    qdev_get_gpio_in(pch_pic,
                                     VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET),
                    115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
+    fdt_add_uart_node(lams);
 
     /* Network init */
     for (i = 0; i < nb_nics; i++) {
@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
     sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
                          qdev_get_gpio_in(pch_pic,
                          VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET));
+    fdt_add_rtc_node(lams);
 
     pm_mem = g_new(MemoryRegion, 1);
     memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops,
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/pci-host/ls7a.h
+++ b/include/hw/pci-host/ls7a.h
@@ -XXX,XX +XXX,XX @@
 #define VIRT_PCI_IRQS            48
 #define VIRT_UART_IRQ            (PCH_PIC_IRQ_OFFSET + 2)
 #define VIRT_UART_BASE           0x1fe001e0
+#define VIRT_UART_SIZE           0X100
 #define VIRT_RTC_IRQ             (PCH_PIC_IRQ_OFFSET + 3)
 #define VIRT_MISC_REG_BASE       (VIRT_PCH_REG_BASE + 0x00080000)
 #define VIRT_RTC_REG_BASE        (VIRT_MISC_REG_BASE + 0x00050100)
-- 
2.31.1

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Add TPM device for LoongArch virt machine, including
establish TPM acpi info and add TYPE_TPM_TIS_SYSBUS
to dynamic_sysbus_devices list.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221028014007.2718352-4-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/loongarch/acpi-build.c | 51 ++++++++++++++++++++++++++++++++++++++-
 hw/loongarch/virt.c       |  4 +++
 2 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/acpi-build.c
+++ b/hw/loongarch/acpi-build.c
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/acpi/generic_event_device.h"
 #include "hw/pci-host/gpex.h"
+#include "sysemu/tpm.h"
+#include "hw/platform-bus.h"
+#include "hw/acpi/aml-build.h"
 
 #define ACPI_BUILD_ALIGN_SIZE             0x1000
 #define ACPI_BUILD_TABLE_SIZE             0x20000
@@ -XXX,XX +XXX,XX @@ static void build_pci_device_aml(Aml *scope, LoongArchMachineState *lams)
     acpi_dsdt_add_gpex(scope, &cfg);
 }
 
+#ifdef CONFIG_TPM
+static void acpi_dsdt_add_tpm(Aml *scope, LoongArchMachineState *vms)
+{
+    PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
+    hwaddr pbus_base = VIRT_PLATFORM_BUS_BASEADDRESS;
+    SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());
+    MemoryRegion *sbdev_mr;
+    hwaddr tpm_base;
+
+    if (!sbdev) {
+        return;
+    }
+
+    tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
+    assert(tpm_base != -1);
+
+    tpm_base += pbus_base;
+
+    sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
+
+    Aml *dev = aml_device("TPM0");
+    aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
+    aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
+    aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+    Aml *crs = aml_resource_template();
+    aml_append(crs,
+               aml_memory32_fixed(tpm_base,
+                                  (uint32_t)memory_region_size(sbdev_mr),
+                                  AML_READ_WRITE));
+    aml_append(dev, aml_name_decl("_CRS", crs));
+    aml_append(scope, dev);
+}
+#endif
+
 /* build DSDT */
 static void
 build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
     build_uart_device_aml(dsdt);
     build_pci_device_aml(dsdt, lams);
     build_la_ged_aml(dsdt, machine);
-
+#ifdef CONFIG_TPM
+    acpi_dsdt_add_tpm(dsdt, lams);
+#endif
     /* System State Package */
     scope = aml_scope("\\");
     pkg = aml_package(4);
@@ -XXX,XX +XXX,XX @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
                    lams->oem_table_id);
     }
 
+#ifdef CONFIG_TPM
+    /* TPM info */
+    if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
+        acpi_add_table(table_offsets, tables_blob);
+        build_tpm2(tables_blob, tables->linker,
+                   tables->tcpalog, lams->oem_id,
+                   lams->oem_table_id);
+    }
+#endif
     /* Add tables supplied by user (if any) */
     for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
         unsigned len = acpi_table_len(u);
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/platform-bus.h"
 #include "hw/display/ramfb.h"
 #include "hw/mem/pc-dimm.h"
+#include "sysemu/tpm.h"
 
 static void fdt_add_rtc_node(LoongArchMachineState *lams)
 {
@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
     object_class_property_set_description(oc, "acpi",
         "Enable ACPI");
     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
+#ifdef CONFIG_TPM
+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
+#endif
 }
 
 static const TypeInfo loongarch_machine_types[] = {
-- 
2.31.1

We need subcodes to distinguish the same excode cs->exception_indexs,
such as EXCCODE_ADEF/EXCCODE_ADEM.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20221101073210.3934280-1-gaosong@loongson.cn>
---
 target/loongarch/cpu.c |  7 +++--
 target/loongarch/cpu.h | 58 ++++++++++++++++++++++--------------------
 2 files changed, 36 insertions(+), 29 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
         env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
                                       PC, (env->pc >> 2));
     } else {
-        env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause);
+        env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE,
+                                    EXCODE_MCODE(cause));
+        env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE,
+                                    EXCODE_SUBCODE(cause));
         env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
                                    FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
         env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
             env->pc = env->CSR_TLBRENTRY;
         } else {
             env->pc = env->CSR_EENTRY;
-            env->pc += cause * vec_size;
+            env->pc += EXCODE_MCODE(cause) * vec_size;
         }
         qemu_log_mask(CPU_LOG_INT,
                       "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(FCSR0, CAUSE, 24, 5)
 #define FP_DIV0           8
 #define FP_INVALID        16
 
-#define  EXCCODE_EXTERNAL_INT   64   /* plus external interrupt number */
-#define  EXCCODE_INT                 0
-#define  EXCCODE_PIL                 1
-#define  EXCCODE_PIS                 2
-#define  EXCCODE_PIF                 3
-#define  EXCCODE_PME                 4
-#define  EXCCODE_PNR                 5
-#define  EXCCODE_PNX                 6
-#define  EXCCODE_PPI                 7
-#define  EXCCODE_ADEF                8 /* Different exception subcode */
-#define  EXCCODE_ADEM                8
-#define  EXCCODE_ALE                 9
-#define  EXCCODE_BCE                 10
-#define  EXCCODE_SYS                 11
-#define  EXCCODE_BRK                 12
-#define  EXCCODE_INE                 13
-#define  EXCCODE_IPE                 14
-#define  EXCCODE_FPD                 15
-#define  EXCCODE_SXD                 16
-#define  EXCCODE_ASXD                17
-#define  EXCCODE_FPE                 18 /* Different exception subcode */
-#define  EXCCODE_VFPE                18
-#define  EXCCODE_WPEF                19 /* Different exception subcode */
-#define  EXCCODE_WPEM                19
-#define  EXCCODE_BTD                 20
-#define  EXCCODE_BTE                 21
-#define  EXCCODE_DBP                 26 /* Reserved subcode used for debug */
+#define EXCODE(code, subcode) ( ((subcode) << 6) | (code) )
+#define EXCODE_MCODE(code)    ( (code) & 0x3f )
+#define EXCODE_SUBCODE(code)  ( (code) >> 6 )
+
+#define  EXCCODE_EXTERNAL_INT        64   /* plus external interrupt number */
+#define  EXCCODE_INT                 EXCODE(0, 0)
+#define  EXCCODE_PIL                 EXCODE(1, 0)
+#define  EXCCODE_PIS                 EXCODE(2, 0)
+#define  EXCCODE_PIF                 EXCODE(3, 0)
+#define  EXCCODE_PME                 EXCODE(4, 0)
+#define  EXCCODE_PNR                 EXCODE(5, 0)
+#define  EXCCODE_PNX                 EXCODE(6, 0)
+#define  EXCCODE_PPI                 EXCODE(7, 0)
+#define  EXCCODE_ADEF                EXCODE(8, 0) /* Different exception subcode */
+#define  EXCCODE_ADEM                EXCODE(8, 1)
+#define  EXCCODE_ALE                 EXCODE(9, 0)
+#define  EXCCODE_BCE                 EXCODE(10, 0)
+#define  EXCCODE_SYS                 EXCODE(11, 0)
+#define  EXCCODE_BRK                 EXCODE(12, 0)
+#define  EXCCODE_INE                 EXCODE(13, 0)
+#define  EXCCODE_IPE                 EXCODE(14, 0)
+#define  EXCCODE_FPD                 EXCODE(15, 0)
+#define  EXCCODE_SXD                 EXCODE(16, 0)
+#define  EXCCODE_ASXD                EXCODE(17, 0)
+#define  EXCCODE_FPE                 EXCODE(18, 0) /* Different exception subcode */
+#define  EXCCODE_VFPE                EXCODE(18, 1)
+#define  EXCCODE_WPEF                EXCODE(19, 0) /* Different exception subcode */
+#define  EXCCODE_WPEM                EXCODE(19, 1)
+#define  EXCCODE_BTD                 EXCODE(20, 0)
+#define  EXCCODE_BTE                 EXCODE(21, 0)
+#define  EXCCODE_DBP                 EXCODE(26, 0) /* Reserved subcode used for debug */
 
 /* cpucfg[0] bits */
 FIELD(CPUCFG0, PRID, 0, 32)
-- 
2.31.1

When the address is invalid address, We should set exception_index
according to MMUAccessType, and EXCCODE_ADEF need't update badinstr.
Otherwise, The system enters an infinite loop. e.g:
run test.c on system mode
test.c:
    #include<stdio.h>

void (*func)(int *);

int main()
    {
        int i = 8;
        void *ptr = (void *)0x4000000000000000;
        func = ptr;
        func(&i);
        return 0;
    }

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20221101073210.3934280-2-gaosong@loongson.cn>
---
 target/loongarch/cpu.c        | 1 +
 target/loongarch/tlb_helper.c | 5 +++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
         }
         QEMU_FALLTHROUGH;
     case EXCCODE_PIF:
+    case EXCCODE_ADEF:
         cause = cs->exception_index;
         update_badinstr = 0;
         break;
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
     switch (tlb_error) {
     default:
     case TLBRET_BADADDR:
-        cs->exception_index = EXCCODE_ADEM;
+        cs->exception_index = access_type == MMU_INST_FETCH
+                              ? EXCCODE_ADEF : EXCCODE_ADEM;
         break;
     case TLBRET_NOMATCH:
         /* No TLB match for a mapped address */
@@ -XXX,XX +XXX,XX @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     CPULoongArchState *env = &cpu->env;
     hwaddr physical;
     int prot;
-    int ret = TLBRET_BADADDR;
+    int ret;
 
     /* Data access */
     ret = get_physical_address(env, &physical, &prot, address,
-- 
2.31.1

From: Rui Wang <wangrui@loongson.cn>

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Rui Wang <wangrui@loongson.cn>
Message-Id: <20221104040517.222059-2-wangrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/cpu.h                             | 9 ++++++++-
 target/loongarch/insn_trans/trans_privileged.c.inc | 2 +-
 target/loongarch/translate.c                       | 6 +++++-
 3 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -XXX,XX +XXX,XX @@
 #include "qemu/timer.h"
 #include "exec/memory.h"
 #include "hw/sysbus.h"
+#include "cpu-csr.h"
 
 #define IOCSRF_TEMP             0
 #define IOCSRF_NODECNT          1
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
 #endif
 }
 
+/*
+ * LoongArch CPUs hardware flags.
+ */
+#define HW_FLAGS_PLV_MASK   R_CSR_CRMD_PLV_MASK  /* 0x03 */
+#define HW_FLAGS_CRMD_PG    R_CSR_CRMD_PG_MASK   /* 0x10 */
+
 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
                                         target_ulong *pc,
                                         target_ulong *cs_base,
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
 {
     *pc = env->pc;
     *cs_base = 0;
-    *flags = cpu_mmu_index(env, false);
+    *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
 }
 
 void loongarch_cpu_list(void);
diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static const CSRInfo csr_info[] = {
 
 static bool check_plv(DisasContext *ctx)
 {
-    if (ctx->base.tb->flags == MMU_USER_IDX) {
+    if (ctx->mem_idx == MMU_USER_IDX) {
         generate_exception(ctx, EXCCODE_IPE);
         return true;
     }
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 
     ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
-    ctx->mem_idx = ctx->base.tb->flags;
+    if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) {
+        ctx->mem_idx = ctx->base.tb->flags & HW_FLAGS_PLV_MASK;
+    } else {
+        ctx->mem_idx = MMU_DA_IDX;
+    }
 
     /* Bound the number of insns to execute to those left on the page.  */
     bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
-- 
2.31.1

From: Rui Wang <wangrui@loongson.cn>

We need to emulate it to generate a floating point disable exception
when CSR.EUEN.FPE is zero.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Rui Wang <wangrui@loongson.cn>
Message-Id: <20221104040517.222059-3-wangrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/cpu.c                        |  2 ++
 target/loongarch/cpu.h                        |  2 ++
 .../loongarch/insn_trans/trans_farith.c.inc   | 30 ++++++++++++++++
 target/loongarch/insn_trans/trans_fcmp.c.inc  | 11 ++++--
 .../loongarch/insn_trans/trans_fmemory.c.inc  | 34 +++++++++++++++----
 target/loongarch/insn_trans/trans_fmov.c.inc  | 29 ++++++++++++++--
 6 files changed, 97 insertions(+), 11 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -XXX,XX +XXX,XX @@ static const char * const excp_names[] = {
     [EXCCODE_BRK] = "Break",
     [EXCCODE_INE] = "Instruction Non-Existent",
     [EXCCODE_IPE] = "Instruction privilege error",
+    [EXCCODE_FPD] = "Floating Point Disabled",
     [EXCCODE_FPE] = "Floating Point Exception",
     [EXCCODE_DBP] = "Debug breakpoint",
     [EXCCODE_BCE] = "Bound Check Exception",
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
     case EXCCODE_BRK:
     case EXCCODE_INE:
     case EXCCODE_IPE:
+    case EXCCODE_FPD:
     case EXCCODE_FPE:
     case EXCCODE_BCE:
         env->CSR_BADV = env->pc;
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
  */
 #define HW_FLAGS_PLV_MASK   R_CSR_CRMD_PLV_MASK  /* 0x03 */
 #define HW_FLAGS_CRMD_PG    R_CSR_CRMD_PG_MASK   /* 0x10 */
+#define HW_FLAGS_EUEN_FPE   0x04
 
 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
                                         target_ulong *pc,
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
     *pc = env->pc;
     *cs_base = 0;
     *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
+    *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
 }
 
 void loongarch_cpu_list(void);
diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loongarch/insn_trans/trans_farith.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/insn_trans/trans_farith.c.inc
+++ b/target/loongarch/insn_trans/trans_farith.c.inc
@@ -XXX,XX +XXX,XX @@
  * Copyright (c) 2021 Loongson Technology Corporation Limited
  */
 
+#ifndef CONFIG_USER_ONLY
+#define CHECK_FPE do { \
+    if ((ctx->base.tb->flags & HW_FLAGS_EUEN_FPE) == 0) { \
+        generate_exception(ctx, EXCCODE_FPD); \
+        return false; \
+    } \
+} while (0)
+#else
+#define CHECK_FPE
+#endif
+
 static bool gen_fff(DisasContext *ctx, arg_fff *a,
                     void (*func)(TCGv, TCGv_env, TCGv, TCGv))
 {
+    CHECK_FPE;
+
     func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk]);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool gen_fff(DisasContext *ctx, arg_fff *a,
 static bool gen_ff(DisasContext *ctx, arg_ff *a,
                    void (*func)(TCGv, TCGv_env, TCGv))
 {
+    CHECK_FPE;
+
     func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj]);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool gen_muladd(DisasContext *ctx, arg_ffff *a,
                        int flag)
 {
     TCGv_i32 tflag = tcg_constant_i32(flag);
+
+    CHECK_FPE;
+
     func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj],
          cpu_fpr[a->fk], cpu_fpr[a->fa], tflag);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool gen_muladd(DisasContext *ctx, arg_ffff *a,
 
 static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a)
 {
+    CHECK_FPE;
+
     tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0, 31);
     return true;
 }
 
 static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a)
 {
+    CHECK_FPE;
+
     tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0, 63);
     return true;
 }
 
 static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a)
 {
+    CHECK_FPE;
+
     tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 31));
     gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a)
 
 static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a)
 {
+    CHECK_FPE;
+
     tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 63));
     return true;
 }
 
 static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a)
 {
+    CHECK_FPE;
+
     tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x80000000);
     gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a)
 
 static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a)
 {
+    CHECK_FPE;
+
     tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x8000000000000000LL);
     return true;
 }
diff --git a/target/loongarch/insn_trans/trans_fcmp.c.inc b/target/loongarch/insn_trans/trans_fcmp.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/insn_trans/trans_fcmp.c.inc
+++ b/target/loongarch/insn_trans/trans_fcmp.c.inc
@@ -XXX,XX +XXX,XX @@ static uint32_t get_fcmp_flags(int cond)
 
 static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
 {
-    TCGv var = tcg_temp_new();
+    TCGv var;
     uint32_t flags;
     void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
 
+    CHECK_FPE;
+
+    var = tcg_temp_new();
     fn = (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s);
     flags = get_fcmp_flags(a->fcond >> 1);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
 
 static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a)
 {
-    TCGv var = tcg_temp_new();
+    TCGv var;
     uint32_t flags;
     void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
+
+    CHECK_FPE;
+
+    var = tcg_temp_new();
     fn = (a->fcond & 1 ? gen_helper_fcmp_s_d : gen_helper_fcmp_c_d);
     flags = get_fcmp_flags(a->fcond >> 1);
 
diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loongarch/insn_trans/trans_fmemory.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/insn_trans/trans_fmemory.c.inc
+++ b/target/loongarch/insn_trans/trans_fmemory.c.inc
@@ -XXX,XX +XXX,XX @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
     TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv temp = NULL;
 
+    CHECK_FPE;
+
     if (a->imm) {
         temp = tcg_temp_new();
         tcg_gen_addi_tl(temp, addr, a->imm);
@@ -XXX,XX +XXX,XX @@ static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
     TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv temp = NULL;
 
+    CHECK_FPE;
+
     if (a->imm) {
         temp = tcg_temp_new();
         tcg_gen_addi_tl(temp, addr, a->imm);
@@ -XXX,XX +XXX,XX @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, MemOp mop)
 {
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
-    TCGv addr = tcg_temp_new();
+    TCGv addr;
 
+    CHECK_FPE;
+
+    addr = tcg_temp_new();
     tcg_gen_add_tl(addr, src1, src2);
     tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
     maybe_nanbox_load(cpu_fpr[a->fd], mop);
@@ -XXX,XX +XXX,XX @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, MemOp mop)
 {
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
-    TCGv addr = tcg_temp_new();
+    TCGv addr;
+
+    CHECK_FPE;
 
+    addr = tcg_temp_new();
     tcg_gen_add_tl(addr, src1, src2);
     tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
     tcg_temp_free(addr);
@@ -XXX,XX +XXX,XX @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
 {
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
-    TCGv addr = tcg_temp_new();
+    TCGv addr;
 
+    CHECK_FPE;
+
+    addr = tcg_temp_new();
     gen_helper_asrtgt_d(cpu_env, src1, src2);
     tcg_gen_add_tl(addr, src1, src2);
     tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
@@ -XXX,XX +XXX,XX @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
 {
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
-    TCGv addr = tcg_temp_new();
+    TCGv addr;
+
+    CHECK_FPE;
 
+    addr = tcg_temp_new();
     gen_helper_asrtgt_d(cpu_env, src1, src2);
     tcg_gen_add_tl(addr, src1, src2);
     tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
@@ -XXX,XX +XXX,XX @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a, MemOp mop)
 {
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
-    TCGv addr = tcg_temp_new();
+    TCGv addr;
 
+    CHECK_FPE;
+
+    addr = tcg_temp_new();
     gen_helper_asrtle_d(cpu_env, src1, src2);
     tcg_gen_add_tl(addr, src1, src2);
     tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
@@ -XXX,XX +XXX,XX @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop)
 {
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
-    TCGv addr = tcg_temp_new();
+    TCGv addr;
+
+    CHECK_FPE;
 
+    addr = tcg_temp_new();
     gen_helper_asrtle_d(cpu_env, src1, src2);
     tcg_gen_add_tl(addr, src1, src2);
     tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarch/insn_trans/trans_fmov.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/insn_trans/trans_fmov.c.inc
+++ b/target/loongarch/insn_trans/trans_fmov.c.inc
@@ -XXX,XX +XXX,XX @@ static const uint32_t fcsr_mask[4] = {
 static bool trans_fsel(DisasContext *ctx, arg_fsel *a)
 {
     TCGv zero = tcg_constant_tl(0);
-    TCGv cond = tcg_temp_new();
+    TCGv cond;
 
+    CHECK_FPE;
+
+    cond = tcg_temp_new();
     tcg_gen_ld8u_tl(cond, cpu_env, offsetof(CPULoongArchState, cf[a->ca]));
     tcg_gen_movcond_tl(TCG_COND_EQ, cpu_fpr[a->fd], cond, zero,
                        cpu_fpr[a->fj], cpu_fpr[a->fk]);
@@ -XXX,XX +XXX,XX @@ static bool gen_f2f(DisasContext *ctx, arg_ff *a,
     TCGv dest = cpu_fpr[a->fd];
     TCGv src = cpu_fpr[a->fj];
 
+    CHECK_FPE;
+
     func(dest, src);
     if (nanbox) {
         gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
@@ -XXX,XX +XXX,XX @@ static bool gen_r2f(DisasContext *ctx, arg_fr *a,
 {
     TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
 
+    CHECK_FPE;
+
     func(cpu_fpr[a->fd], src);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool gen_f2r(DisasContext *ctx, arg_rf *a,
 {
     TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
 
+    CHECK_FPE;
+
     func(dest, cpu_fpr[a->fj]);
     gen_set_gpr(a->rd, dest, EXT_NONE);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr2fcsr *a)
     uint32_t mask = fcsr_mask[a->fcsrd];
     TCGv Rj = gpr_src(ctx, a->rj, EXT_NONE);
 
+    CHECK_FPE;
+
     if (mask == UINT32_MAX) {
         tcg_gen_st32_i64(Rj, cpu_env, offsetof(CPULoongArchState, fcsr0));
     } else {
@@ -XXX,XX +XXX,XX @@ static bool trans_movfcsr2gr(DisasContext *ctx, arg_movfcsr2gr *a)
 {
     TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
 
+    CHECK_FPE;
+
     tcg_gen_ld32u_i64(dest, cpu_env, offsetof(CPULoongArchState, fcsr0));
     tcg_gen_andi_i64(dest, dest, fcsr_mask[a->fcsrs]);
     gen_set_gpr(a->rd, dest, EXT_NONE);
@@ -XXX,XX +XXX,XX @@ static void gen_movfrh2gr_s(TCGv dest, TCGv src)
 
 static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a)
 {
-    TCGv t0 = tcg_temp_new();
+    TCGv t0;
+
+    CHECK_FPE;
 
+    t0 = tcg_temp_new();
     tcg_gen_andi_tl(t0, cpu_fpr[a->fj], 0x1);
     tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
     tcg_temp_free(t0);
@@ -XXX,XX +XXX,XX @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a)
 
 static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a)
 {
+    CHECK_FPE;
+
     tcg_gen_ld8u_tl(cpu_fpr[a->fd], cpu_env,
                     offsetof(CPULoongArchState, cf[a->cj & 0x7]));
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a)
 
 static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a)
 {
-    TCGv t0 = tcg_temp_new();
+    TCGv t0;
 
+    CHECK_FPE;
+
+    t0 = tcg_temp_new();
     tcg_gen_andi_tl(t0, gpr_src(ctx, a->rj, EXT_NONE), 0x1);
     tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
     tcg_temp_free(t0);
@@ -XXX,XX +XXX,XX @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a)
 
 static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)
 {
+    CHECK_FPE;
+
     tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), cpu_env,
                     offsetof(CPULoongArchState, cf[a->cj & 0x7]));
     return true;
-- 
2.31.1