Hi,

This version implements changes based on Drew's feedback from v1.

Most notable change is the addition of zifencei in RVA23S64 that I
somehow missed in v1.

Patches based on alistair/riscv-to-apply.next.

Changes from v1:
- patch 2:
  - do not remove zba/zbb/zbs from the extension list
- patch 3:
  - fixed commit msg
  - treat supm as an extension rather than a named feature
- patch 4:
  - add zifencei
  - treat ssnpm as a extension rather than a named feature
v1 link: https://lore.kernel.org/qemu-riscv/20250114132012.1224941-1-dbarboza@ventanamicro.com/

Daniel Henrique Barboza (4):
  target/riscv: add ssu64xl
  target/riscv: use RVB in RVA22U64
  target/riscv: add RVA23U64 profile
  target/riscv: add RVA23S64 profile

 target/riscv/cpu-qom.h            |   2 +
 target/riscv/cpu.c                |  77 +++++++++++++++++++++++++++++-
 tests/data/acpi/riscv64/virt/RHCT | Bin 390 -> 400 bytes
 3 files changed, 78 insertions(+), 1 deletion(-)

-- 
2.47.1