Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_write_u64() function.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/mips/bootloader.h | 3 ++-
 hw/mips/bootloader.c         | 9 +++++----
 hw/mips/boston.c             | 6 +++---
 3 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h
index cc2ffe3ab2c..946580f6f5c 100644
--- a/include/hw/mips/bootloader.h
+++ b/include/hw/mips/bootloader.h
@@ -24,6 +24,7 @@ void bl_gen_write_ulong(const MIPSCPU *cpu, void **ptr,
                         target_ulong addr, target_ulong val);
 void bl_gen_write_u32(const MIPSCPU *cpu, void **ptr,
                       target_ulong addr, uint32_t val);
-void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val);
+void bl_gen_write_u64(const MIPSCPU *cpu, void **ptr,
+                      target_ulong addr, uint64_t val);
 
 #endif
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 6f0222faf48..c5bad03b528 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -303,9 +303,10 @@ void bl_gen_write_u32(const MIPSCPU *cpu, void **p,
     bl_gen_sw(&cpu->env, p, BL_REG_K0, BL_REG_K1, 0x0);
 }
 
-void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val)
+void bl_gen_write_u64(const MIPSCPU *cpu, void **p,
+                      target_ulong addr, uint64_t val)
 {
-    bl_gen_dli(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, val);
-    bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_K1, addr);
-    bl_gen_sd(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, BL_REG_K1, 0x0);
+    bl_gen_dli(&cpu->env, p, BL_REG_K0, val);
+    bl_gen_load_ulong(&cpu->env, p, BL_REG_K1, addr);
+    bl_gen_sd(&cpu->env, p, BL_REG_K0, BL_REG_K1, 0x0);
 }
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 3a06b776fe8..09c4dfade12 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -329,19 +329,19 @@ static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr)
 
     /* Move CM GCRs */
     regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS),
-    bl_gen_write_u64(&p, regaddr,
+    bl_gen_write_u64(MIPS_CPU(first_cpu), &p, regaddr,
                      boston_memmap[BOSTON_CM].base);
 
     /* Move & enable GIC GCRs */
     regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base
                                            + GCR_GIC_BASE_OFS),
-    bl_gen_write_u64(&p, regaddr,
+    bl_gen_write_u64(MIPS_CPU(first_cpu), &p, regaddr,
                      boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK);
 
     /* Move & enable CPC GCRs */
     regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base
                                            + GCR_CPC_BASE_OFS),
-    bl_gen_write_u64(&p, regaddr,
+    bl_gen_write_u64(MIPS_CPU(first_cpu), &p, regaddr,
                      boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK);
 
     /*
-- 
2.47.1