The ARMv7MState object is not simply a CPU, it also
contains the NVIC, SysTick timer, and various MemoryRegions.
Rename the field as 'armv7m', like other Cortex-M boards.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/arm/nrf51_soc.h | 2 +-
hw/arm/nrf51_soc.c | 18 +++++++++---------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
index e52a56e75e0..f88ab1b7d3e 100644
--- a/include/hw/arm/nrf51_soc.h
+++ b/include/hw/arm/nrf51_soc.h
@@ -30,7 +30,7 @@ struct NRF51State {
SysBusDevice parent_obj;
/*< public >*/
- ARMv7MState cpu;
+ ARMv7MState armv7m;
NRF51UARTState uart;
NRF51RNGState rng;
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index 37dd4cf5f40..dee06ab5654 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -76,16 +76,16 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
}
/* This clock doesn't need migration because it is fixed-frequency */
clock_set_hz(s->sysclk, HCLK_FRQ);
- qdev_connect_clock_in(DEVICE(&s->cpu), "cpuclk", s->sysclk);
+ qdev_connect_clock_in(DEVICE(&s->armv7m), "cpuclk", s->sysclk);
/*
* This SoC has no systick device, so don't connect refclk.
* TODO: model the lack of systick (currently the armv7m object
* will always provide one).
*/
- object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
+ object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(&s->container),
&error_abort);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
return;
}
@@ -104,7 +104,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
- qdev_get_gpio_in(DEVICE(&s->cpu),
+ qdev_get_gpio_in(DEVICE(&s->armv7m),
BASE_TO_IRQ(NRF51_UART_BASE)));
/* RNG */
@@ -115,7 +115,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
- qdev_get_gpio_in(DEVICE(&s->cpu),
+ qdev_get_gpio_in(DEVICE(&s->armv7m),
BASE_TO_IRQ(NRF51_RNG_BASE)));
/* UICR, FICR, NVMC, FLASH */
@@ -161,7 +161,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->cpu),
+ qdev_get_gpio_in(DEVICE(&s->armv7m),
BASE_TO_IRQ(base_addr)));
}
@@ -185,10 +185,10 @@ static void nrf51_soc_init(Object *obj)
memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
- object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);
- qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
+ object_initialize_child(OBJECT(s), "armv6m", &s->armv7m, TYPE_ARMV7M);
+ qdev_prop_set_string(DEVICE(&s->armv7m), "cpu-type",
ARM_CPU_TYPE_NAME("cortex-m0"));
- qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
+ qdev_prop_set_uint32(DEVICE(&s->armv7m), "num-irq", 32);
object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);
object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");
--
2.47.1
On Mon, Jan 13, 2025 at 8:57 AM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> The ARMv7MState object is not simply a CPU, it also
> contains the NVIC, SysTick timer, and various MemoryRegions.
>
> Rename the field as 'armv7m', like other Cortex-M boards.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/arm/nrf51_soc.h | 2 +-
> hw/arm/nrf51_soc.c | 18 +++++++++---------
> 2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
> index e52a56e75e0..f88ab1b7d3e 100644
> --- a/include/hw/arm/nrf51_soc.h
> +++ b/include/hw/arm/nrf51_soc.h
> @@ -30,7 +30,7 @@ struct NRF51State {
> SysBusDevice parent_obj;
>
> /*< public >*/
> - ARMv7MState cpu;
> + ARMv7MState armv7m;
>
> NRF51UARTState uart;
> NRF51RNGState rng;
> diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
> index 37dd4cf5f40..dee06ab5654 100644
> --- a/hw/arm/nrf51_soc.c
> +++ b/hw/arm/nrf51_soc.c
> @@ -76,16 +76,16 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
> }
> /* This clock doesn't need migration because it is fixed-frequency */
> clock_set_hz(s->sysclk, HCLK_FRQ);
> - qdev_connect_clock_in(DEVICE(&s->cpu), "cpuclk", s->sysclk);
> + qdev_connect_clock_in(DEVICE(&s->armv7m), "cpuclk", s->sysclk);
> /*
> * This SoC has no systick device, so don't connect refclk.
> * TODO: model the lack of systick (currently the armv7m object
> * will always provide one).
> */
>
> - object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
> + object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(&s->container),
> &error_abort);
> - if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
> return;
> }
>
> @@ -104,7 +104,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
> mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
> memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
> - qdev_get_gpio_in(DEVICE(&s->cpu),
> + qdev_get_gpio_in(DEVICE(&s->armv7m),
> BASE_TO_IRQ(NRF51_UART_BASE)));
>
> /* RNG */
> @@ -115,7 +115,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
> mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
> memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
> - qdev_get_gpio_in(DEVICE(&s->cpu),
> + qdev_get_gpio_in(DEVICE(&s->armv7m),
> BASE_TO_IRQ(NRF51_RNG_BASE)));
>
> /* UICR, FICR, NVMC, FLASH */
> @@ -161,7 +161,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
>
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
> - qdev_get_gpio_in(DEVICE(&s->cpu),
> + qdev_get_gpio_in(DEVICE(&s->armv7m),
> BASE_TO_IRQ(base_addr)));
> }
>
> @@ -185,10 +185,10 @@ static void nrf51_soc_init(Object *obj)
>
> memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
>
> - object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);
> - qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
> + object_initialize_child(OBJECT(s), "armv6m", &s->armv7m, TYPE_ARMV7M);
> + qdev_prop_set_string(DEVICE(&s->armv7m), "cpu-type",
> ARM_CPU_TYPE_NAME("cortex-m0"));
> - qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
> + qdev_prop_set_uint32(DEVICE(&s->armv7m), "num-irq", 32);
>
> object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);
> object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");
> --
> 2.47.1
>
>
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