Since the 405 CPU family was phased out, these instructions have no
users anymore.

Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 target/ppc/cpu.h       |  6 +-----
 target/ppc/translate.c | 11 -----------
 2 files changed, 1 insertion(+), 16 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 504924f10561..f83f01a62a12 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2234,9 +2234,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
 #define SPR_L3CR              (0x3FA)
 #define SPR_750_TDCH          (0x3FA)
 #define SPR_IABR2             (0x3FA)
-#define SPR_40x_DCCR          (0x3FA)
 #define SPR_ICTC              (0x3FB)
-#define SPR_40x_ICCR          (0x3FB)
 #define SPR_THRM1             (0x3FC)
 #define SPR_403_PBL1          (0x3FC)
 #define SPR_SP                (0x3FD)
@@ -2408,8 +2406,6 @@ enum {
     PPC_TLBIVAX        = 0x0080000000000000ULL,
     /* PowerPC 4xx dedicated instructions                                    */
     PPC_4xx_COMMON     = 0x0100000000000000ULL,
-    /* PowerPC 40x ibct instructions                                         */
-    PPC_40x_ICBT       = 0x0200000000000000ULL,
     /* rfmci is not implemented in all BookE PowerPC                         */
     PPC_RFMCI          = 0x0400000000000000ULL,
     /* rfdi instruction                                                      */
@@ -2440,7 +2436,7 @@ enum {
                         | PPC_SLBI | PPC_WRTEE \
                         | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
                         | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
-                        | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
+                        | PPC_4xx_COMMON | PPC_RFMCI \
                         | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_POPCNTWD \
                         | PPC_CILDST)
 
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ea5eff7cf0f8..779103c0472d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5042,16 +5042,6 @@ static void gen_dcread(DisasContext *ctx)
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
-/* icbt */
-static void gen_icbt_40x(DisasContext *ctx)
-{
-    /*
-     * interpreted as no-op
-     * XXX: specification say this is treated as a load by the MMU but
-     *      does not generate any exception
-     */
-}
-
 /* iccci */
 static void gen_iccci(DisasContext *ctx)
 {
@@ -5884,7 +5874,6 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
-GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
-- 
2.47.1

On 10/1/25 15:17, Cédric Le Goater wrote:
> Since the 405 CPU family was phased out, these instructions have no
> users anymore.
> 
> Signed-off-by: Cédric Le Goater <clg@redhat.com>
> ---
>   target/ppc/cpu.h       |  6 +-----
>   target/ppc/translate.c | 11 -----------
>   2 files changed, 1 insertion(+), 16 deletions(-)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 504924f10561..f83f01a62a12 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -2234,9 +2234,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
>   #define SPR_L3CR              (0x3FA)
>   #define SPR_750_TDCH          (0x3FA)
>   #define SPR_IABR2             (0x3FA)
> -#define SPR_40x_DCCR          (0x3FA)
>   #define SPR_ICTC              (0x3FB)
> -#define SPR_40x_ICCR          (0x3FB)
>   #define SPR_THRM1             (0x3FC)
>   #define SPR_403_PBL1          (0x3FC)
>   #define SPR_SP                (0x3FD)

Belong to patch #3?

On 1/10/25 17:09, Philippe Mathieu-Daudé wrote:
> On 10/1/25 15:17, Cédric Le Goater wrote:
>> Since the 405 CPU family was phased out, these instructions have no
>> users anymore.
>>
>> Signed-off-by: Cédric Le Goater <clg@redhat.com>
>> ---
>>   target/ppc/cpu.h       |  6 +-----
>>   target/ppc/translate.c | 11 -----------
>>   2 files changed, 1 insertion(+), 16 deletions(-)
>>
>> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
>> index 504924f10561..f83f01a62a12 100644
>> --- a/target/ppc/cpu.h
>> +++ b/target/ppc/cpu.h
>> @@ -2234,9 +2234,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
>>   #define SPR_L3CR              (0x3FA)
>>   #define SPR_750_TDCH          (0x3FA)
>>   #define SPR_IABR2             (0x3FA)
>> -#define SPR_40x_DCCR          (0x3FA)
>>   #define SPR_ICTC              (0x3FB)
>> -#define SPR_40x_ICCR          (0x3FB)
>>   #define SPR_THRM1             (0x3FC)
>>   #define SPR_403_PBL1          (0x3FC)
>>   #define SPR_SP                (0x3FD)
> 
> Belong to patch #3?
> 

It could. These are the Data and Instruction Cache Cachability
Register, so they could stay in this patch too.


Thanks,

C.