target/i386: Add the immediate form MSR access instruction support

[PATCH v1 0/3] target/i386: Add the immediate form MSR access instruction support

Posted by Xin Li (Intel) 1 year, 1 month ago

The immediate form of MSR access instructions are primarily motivated by
performance, not code size: by having the MSR number in an immediate, it
is available *much* earlier in the pipeline, which allows the hardware
much more leeway about how a particular MSR is handled.

This new CPU feature is advertised through bit 5 of CPUID.7.1.ECX, which
needs to be added as a new CPU feature word.

WRMSRNS doesn't become a required feature for FERD, and Linux has removed
the dependency, as such remove the dependency from Qemu.


Xin Li (Intel) (3):
  target/i386: Remove FRED dependency on WRMSRNS
  target/i386: Add a new CPU feature word for CPUID.7.1.ECX
  target/i386: Add the immediate form MSR access instruction support

 target/i386/cpu.c | 27 ++++++++++++++++++++++-----
 target/i386/cpu.h |  4 ++++
 2 files changed, 26 insertions(+), 5 deletions(-)


base-commit: 1ada452efc7d8f8bf42cd5e8a2af1b4ac9167a1f
-- 
2.47.1

Re: [PATCH v1 0/3] target/i386: Add the immediate form MSR access instruction support

Posted by Xin Li 9 months, 3 weeks ago

On 1/3/2025 12:48 AM, Xin Li (Intel) wrote:
> The immediate form of MSR access instructions are primarily motivated by
> performance, not code size: by having the MSR number in an immediate, it
> is available *much* earlier in the pipeline, which allows the hardware
> much more leeway about how a particular MSR is handled.
> 
> This new CPU feature is advertised through bit 5 of CPUID.7.1.ECX, which
> needs to be added as a new CPU feature word.

gentle ping!

> 
> WRMSRNS doesn't become a required feature for FERD, and Linux has removed
> the dependency, as such remove the dependency from Qemu.
> 

Maybe this should be sent out as a separate patch?

> 
> Xin Li (Intel) (3):
>    target/i386: Remove FRED dependency on WRMSRNS
>    target/i386: Add a new CPU feature word for CPUID.7.1.ECX
>    target/i386: Add the immediate form MSR access instruction support
> 
>   target/i386/cpu.c | 27 ++++++++++++++++++++++-----
>   target/i386/cpu.h |  4 ++++
>   2 files changed, 26 insertions(+), 5 deletions(-)
> 
> 
> base-commit: 1ada452efc7d8f8bf42cd5e8a2af1b4ac9167a1f

Re: [PATCH v1 0/3] target/i386: Add the immediate form MSR access instruction support

Posted by Xin Li 8 months, 2 weeks ago

On 4/15/2025 8:25 PM, Xin Li wrote:
> On 1/3/2025 12:48 AM, Xin Li (Intel) wrote:
>> The immediate form of MSR access instructions are primarily motivated by
>> performance, not code size: by having the MSR number in an immediate, it
>> is available *much* earlier in the pipeline, which allows the hardware
>> much more leeway about how a particular MSR is handled.
>>
>> This new CPU feature is advertised through bit 5 of CPUID.7.1.ECX, which
>> needs to be added as a new CPU feature word.
> 
> gentle ping!
> 
>>
>> WRMSRNS doesn't become a required feature for FERD, and Linux has removed
>> the dependency, as such remove the dependency from Qemu.
>>
> 
> Maybe this should be sent out as a separate patch?
> 
>>
>> Xin Li (Intel) (3):
>>    target/i386: Remove FRED dependency on WRMSRNS
>>    target/i386: Add a new CPU feature word for CPUID.7.1.ECX
>>    target/i386: Add the immediate form MSR access instruction support
>>
>>   target/i386/cpu.c | 27 ++++++++++++++++++++++-----
>>   target/i386/cpu.h |  4 ++++
>>   2 files changed, 26 insertions(+), 5 deletions(-)
>>
>>
>> base-commit: 1ada452efc7d8f8bf42cd5e8a2af1b4ac9167a1f

Another ping :)