[PULL v2 0/6] loongarch-to-apply queue
[PULL v3 0/7] loongarch-to-apply queue
1
The following changes since commit 38d0939b86e2eef6f6a622c6f1f7befda0146595:
1
The following changes since commit ece5f8374d0416a339f0c0a9399faa2c42d4ad6f:
2
2
3
Merge tag 'pull-vfio-20241226' of https://github.com/legoater/qemu into staging (2024-12-26 04:38:38 -0500)
3
Merge tag 'linux-user-for-7.2-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2022-11-03 10:55:05 -0400)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20241227
7
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20221105
8
8
9
for you to fetch changes up to 5e360dabedb1ab1f15cce27a134ccbe4b8e18424:
9
for you to fetch changes up to 6a284614d485f36af6467ce0925df0042aca7a1f:
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10
11
target/loongarch: Use auto method with LASX feature (2024-12-27 11:33:06 +0800)
11
target/loongarch: Fix raise_mmu_exception() set wrong exception_index (2022-11-05 10:52:19 +0800)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
pull-loongarch-20241227
14
pull-loongarch-20221105
15
v1 ... v2
15
16
1. Modify patch auther inconsistent with SOB
16
V3:
17
- According to Richard's latest comments, drop patch 8, 9.
18
19
v2:
20
- fix win32/win64 complie error;
21
- Add Rui Wang' patches.
17
22
18
----------------------------------------------------------------
23
----------------------------------------------------------------
19
Bibo Mao (5):
24
Song Gao (2):
20
target/loongarch: Use actual operand size with vbsrl check
25
target/loongarch: Add exception subcode
21
hw/loongarch/virt: Create fdt table on machine creation done notification
26
target/loongarch: Fix raise_mmu_exception() set wrong exception_index
22
hw/loongarch/virt: Improve fdt table creation for CPU object
23
target/loongarch: Use auto method with LSX feature
24
target/loongarch: Use auto method with LASX feature
25
27
26
Guo Hongyu (1):
28
Xiaojuan Yang (5):
27
target/loongarch: Fix vldi inst
29
hw/intc: Convert the memops to with_attrs in LoongArch extioi
30
hw/intc: Fix LoongArch extioi coreisr accessing
31
hw/loongarch: Load FDT table into dram memory space
32
hw/loongarch: Improve fdt for LoongArch virt machine
33
hw/loongarch: Add TPM device for LoongArch virt machine
28
34
29
hw/loongarch/virt.c | 142 ++++++++++++++----------
35
hw/intc/loongarch_extioi.c | 41 ++++++++++++++++-------------
30
target/loongarch/cpu.c | 86 ++++++++------
36
hw/intc/trace-events | 3 +--
31
target/loongarch/cpu.h | 4 +
37
hw/loongarch/acpi-build.c | 51 +++++++++++++++++++++++++++++++++++-
32
target/loongarch/kvm/kvm.c | 107 ++++++++++++++++++
38
hw/loongarch/virt.c | 53 ++++++++++++++++++++++++++++++++-----
33
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 4 +-
39
include/hw/loongarch/virt.h | 3 ---
34
5 files changed, 249 insertions(+), 94 deletions(-)
40
include/hw/pci-host/ls7a.h | 1 +
41
target/loongarch/cpu.c | 8 ++++--
42
target/loongarch/cpu.h | 58 ++++++++++++++++++++++-------------------
43
target/loongarch/iocsr_helper.c | 19 ++++++++------
44
target/loongarch/tlb_helper.c | 5 ++--
45
10 files changed, 172 insertions(+), 70 deletions(-)
diff view generated by jsdifflib
[PULL v2 2/6] target/loongarch: Use actual operand size with vbsrl check
[PULL v3 1/7] hw/intc: Convert the memops to with_attrs in LoongArch extioi
1
Hardcoded 32 bytes is used for vbsrl emulation check, there is
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
problem when options lsx=on,lasx=off is used for vbsrl.v instruction
3
in TCG mode. It injects LASX exception rather LSX exception.
4
2
5
Here actual operand size is used.
3
Converting the MemoryRegionOps read/write handlers to
4
with_attrs in LoongArch extioi emulation.
6
5
7
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
8
Fixes: df97f338076 ("target/loongarch: Implement xvreplve xvinsve0 xvpickve")
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-Id: <20221021015307.2570844-2-yangxiaojuan@loongson.cn>
10
Signed-off-by: Song Gao <gaosong@loongson.cn>
12
---
11
---
13
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +-
12
hw/intc/loongarch_extioi.c | 31 +++++++++++++++++--------------
14
1 file changed, 1 insertion(+), 1 deletion(-)
13
hw/intc/trace-events | 3 +--
14
2 files changed, 18 insertions(+), 16 deletions(-)
15
15
16
diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
16
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc
18
--- a/hw/intc/loongarch_extioi.c
19
+++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
19
+++ b/hw/intc/loongarch_extioi.c
20
@@ -XXX,XX +XXX,XX @@ static bool do_vbsrl_v(DisasContext *ctx, arg_vv_i *a, uint32_t oprsz)
20
@@ -XXX,XX +XXX,XX @@ static void extioi_setirq(void *opaque, int irq, int level)
21
extioi_update_irq(s, irq, level);
22
}
23
24
-static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size)
25
+static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
26
+ unsigned size, MemTxAttrs attrs)
21
{
27
{
22
int i, ofs;
28
LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
23
29
unsigned long offset = addr & 0xffff;
24
- if (!check_vec(ctx, 32)) {
30
- uint32_t index, cpu, ret = 0;
25
+ if (!check_vec(ctx, oprsz)) {
31
+ uint32_t index, cpu;
26
return true;
32
33
switch (offset) {
34
case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
35
index = (offset - EXTIOI_NODETYPE_START) >> 2;
36
- ret = s->nodetype[index];
37
+ *data = s->nodetype[index];
38
break;
39
case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
40
index = (offset - EXTIOI_IPMAP_START) >> 2;
41
- ret = s->ipmap[index];
42
+ *data = s->ipmap[index];
43
break;
44
case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
45
index = (offset - EXTIOI_ENABLE_START) >> 2;
46
- ret = s->enable[index];
47
+ *data = s->enable[index];
48
break;
49
case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:
50
index = (offset - EXTIOI_BOUNCE_START) >> 2;
51
- ret = s->bounce[index];
52
+ *data = s->bounce[index];
53
break;
54
case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
55
index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
56
cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
57
- ret = s->coreisr[cpu][index];
58
+ *data = s->coreisr[cpu][index];
59
break;
60
case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
61
index = (offset - EXTIOI_COREMAP_START) >> 2;
62
- ret = s->coremap[index];
63
+ *data = s->coremap[index];
64
break;
65
default:
66
break;
27
}
67
}
28
68
69
- trace_loongarch_extioi_readw(addr, ret);
70
- return ret;
71
+ trace_loongarch_extioi_readw(addr, *data);
72
+ return MEMTX_OK;
73
}
74
75
static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
76
@@ -XXX,XX +XXX,XX @@ static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
77
}
78
}
79
80
-static void extioi_writew(void *opaque, hwaddr addr,
81
- uint64_t val, unsigned size)
82
+static MemTxResult extioi_writew(void *opaque, hwaddr addr,
83
+ uint64_t val, unsigned size,
84
+ MemTxAttrs attrs)
85
{
86
LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
87
int i, cpu, index, old_data, irq;
88
@@ -XXX,XX +XXX,XX @@ static void extioi_writew(void *opaque, hwaddr addr,
89
default:
90
break;
91
}
92
+ return MEMTX_OK;
93
}
94
95
static const MemoryRegionOps extioi_ops = {
96
- .read = extioi_readw,
97
- .write = extioi_writew,
98
+ .read_with_attrs = extioi_readw,
99
+ .write_with_attrs = extioi_writew,
100
.impl.min_access_size = 4,
101
.impl.max_access_size = 4,
102
.valid.min_access_size = 4,
103
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
104
index XXXXXXX..XXXXXXX 100644
105
--- a/hw/intc/trace-events
106
+++ b/hw/intc/trace-events
107
@@ -XXX,XX +XXX,XX @@ loongarch_msi_set_irq(int irq_num) "set msi irq %d"
108
109
# loongarch_extioi.c
110
loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d"
111
-loongarch_extioi_readw(uint64_t addr, uint32_t val) "addr: 0x%"PRIx64 "val: 0x%x"
112
+loongarch_extioi_readw(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
113
loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
114
-
29
--
115
--
30
2.43.5
116
2.31.1
31
117
32
118
diff view generated by jsdifflib
New patch
[PULL v3 2/7] hw/intc: Fix LoongArch extioi coreisr accessing
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
1
2
3
1. When cpu read or write extioi COREISR reg, it should access
4
the reg belonged to itself, so the cpu index of 's->coreisr'
5
is current cpu number. Using MemTxAttrs' requester_id to get
6
the cpu index.
7
2. it need not to mask 0x1f when calculate the coreisr array index.
8
9
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-Id: <20221021015307.2570844-3-yangxiaojuan@loongson.cn>
12
Signed-off-by: Song Gao <gaosong@loongson.cn>
13
---
14
hw/intc/loongarch_extioi.c | 10 ++++++----
15
target/loongarch/iocsr_helper.c | 19 +++++++++++--------
16
2 files changed, 17 insertions(+), 12 deletions(-)
17
18
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/intc/loongarch_extioi.c
21
+++ b/hw/intc/loongarch_extioi.c
22
@@ -XXX,XX +XXX,XX @@ static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
23
*data = s->bounce[index];
24
break;
25
case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
26
- index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
27
- cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
28
+ index = (offset - EXTIOI_COREISR_START) >> 2;
29
+ /* using attrs to get current cpu index */
30
+ cpu = attrs.requester_id;
31
*data = s->coreisr[cpu][index];
32
break;
33
case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
34
@@ -XXX,XX +XXX,XX @@ static MemTxResult extioi_writew(void *opaque, hwaddr addr,
35
s->bounce[index] = val;
36
break;
37
case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
38
- index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
39
- cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
40
+ index = (offset - EXTIOI_COREISR_START) >> 2;
41
+ /* using attrs to get current cpu index */
42
+ cpu = attrs.requester_id;
43
old_data = s->coreisr[cpu][index];
44
s->coreisr[cpu][index] = old_data & ~val;
45
/* write 1 to clear interrrupt */
46
diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/loongarch/iocsr_helper.c
49
+++ b/target/loongarch/iocsr_helper.c
50
@@ -XXX,XX +XXX,XX @@
51
#include "exec/cpu_ldst.h"
52
#include "tcg/tcg-ldst.h"
53
54
+#define GET_MEMTXATTRS(cas) \
55
+ ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})
56
+
57
uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
58
{
59
return address_space_ldub(&env->address_space_iocsr, r_addr,
60
- MEMTXATTRS_UNSPECIFIED, NULL);
61
+ GET_MEMTXATTRS(env), NULL);
62
}
63
64
uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
65
{
66
return address_space_lduw(&env->address_space_iocsr, r_addr,
67
- MEMTXATTRS_UNSPECIFIED, NULL);
68
+ GET_MEMTXATTRS(env), NULL);
69
}
70
71
uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
72
{
73
return address_space_ldl(&env->address_space_iocsr, r_addr,
74
- MEMTXATTRS_UNSPECIFIED, NULL);
75
+ GET_MEMTXATTRS(env), NULL);
76
}
77
78
uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)
79
{
80
return address_space_ldq(&env->address_space_iocsr, r_addr,
81
- MEMTXATTRS_UNSPECIFIED, NULL);
82
+ GET_MEMTXATTRS(env), NULL);
83
}
84
85
void helper_iocsrwr_b(CPULoongArchState *env, target_ulong w_addr,
86
target_ulong val)
87
{
88
address_space_stb(&env->address_space_iocsr, w_addr,
89
- val, MEMTXATTRS_UNSPECIFIED, NULL);
90
+ val, GET_MEMTXATTRS(env), NULL);
91
}
92
93
void helper_iocsrwr_h(CPULoongArchState *env, target_ulong w_addr,
94
target_ulong val)
95
{
96
address_space_stw(&env->address_space_iocsr, w_addr,
97
- val, MEMTXATTRS_UNSPECIFIED, NULL);
98
+ val, GET_MEMTXATTRS(env), NULL);
99
}
100
101
void helper_iocsrwr_w(CPULoongArchState *env, target_ulong w_addr,
102
target_ulong val)
103
{
104
address_space_stl(&env->address_space_iocsr, w_addr,
105
- val, MEMTXATTRS_UNSPECIFIED, NULL);
106
+ val, GET_MEMTXATTRS(env), NULL);
107
}
108
109
void helper_iocsrwr_d(CPULoongArchState *env, target_ulong w_addr,
110
target_ulong val)
111
{
112
address_space_stq(&env->address_space_iocsr, w_addr,
113
- val, MEMTXATTRS_UNSPECIFIED, NULL);
114
+ val, GET_MEMTXATTRS(env), NULL);
115
}
116
--
117
2.31.1
diff view generated by jsdifflib
[PULL v2 3/6] hw/loongarch/virt: Create fdt table on machine creation done notification
[PULL v3 3/7] hw/loongarch: Load FDT table into dram memory space
1
The same with ACPI table, fdt table is created on machine done
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
notification. Some objects like CPU objects can be created with cold-plug
3
method with command such as -smp x, -device la464-loongarch-cpu, so all
4
objects finish to create when machine is done.
5
2
6
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
3
Load FDT table into dram memory space, and the addr is 2 MiB.
7
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
4
Since lowmem region starts from 0, FDT base address is located
5
at 2 MiB to avoid NULL pointer access.
6
7
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
8
Acked-by: Song Gao <gaosong@loongson.cn>
9
Message-Id: <20221028014007.2718352-2-yangxiaojuan@loongson.cn>
10
Signed-off-by: Song Gao <gaosong@loongson.cn>
8
---
11
---
9
hw/loongarch/virt.c | 103 ++++++++++++++++++++++++--------------------
12
hw/loongarch/virt.c | 18 +++++++++++-------
10
1 file changed, 57 insertions(+), 46 deletions(-)
13
include/hw/loongarch/virt.h | 3 ---
14
2 files changed, 11 insertions(+), 10 deletions(-)
11
15
12
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
16
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
13
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/loongarch/virt.c
18
--- a/hw/loongarch/virt.c
15
+++ b/hw/loongarch/virt.c
19
+++ b/hw/loongarch/virt.c
16
@@ -XXX,XX +XXX,XX @@ static void virt_build_smbios(LoongArchVirtMachineState *lvms)
20
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pcie_node(const LoongArchMachineState *lams)
17
}
21
1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
22
2, base_mmio, 2, size_mmio);
23
g_free(nodename);
24
- qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size);
18
}
25
}
19
26
20
+static void virt_fdt_setup(LoongArchVirtMachineState *lvms)
27
static void fdt_add_irqchip_node(LoongArchMachineState *lams)
21
+{
28
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
22
+ MachineState *machine = MACHINE(lvms);
29
MemoryRegion *address_space_mem = get_system_memory();
23
+ uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle;
30
LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
24
+ int i;
31
int i;
25
+
32
+ hwaddr fdt_base;
26
+ create_fdt(lvms);
33
27
+ fdt_add_cpu_nodes(lvms);
34
if (!cpu_model) {
28
+ fdt_add_memory_nodes(machine);
35
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
29
+ fdt_add_fw_cfg_node(lvms);
36
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
30
+ fdt_add_flash_node(lvms);
37
lams->machine_done.notify = virt_machine_done;
31
+
38
qemu_add_machine_init_done_notifier(&lams->machine_done);
32
+ /* Add cpu interrupt-controller */
39
fdt_add_pcie_node(lams);
33
+ fdt_add_cpuic_node(lvms, &cpuintc_phandle);
40
-
34
+ /* Add Extend I/O Interrupt Controller node */
41
- /* load fdt */
35
+ fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
42
- MemoryRegion *fdt_rom = g_new(MemoryRegion, 1);
36
+ /* Add PCH PIC node */
43
- memory_region_init_rom(fdt_rom, NULL, "fdt", VIRT_FDT_SIZE, &error_fatal);
37
+ fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle);
44
- memory_region_add_subregion(get_system_memory(), VIRT_FDT_BASE, fdt_rom);
38
+ /* Add PCH MSI node */
45
- rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, VIRT_FDT_BASE);
39
+ fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle);
40
+ /* Add pcie node */
41
+ fdt_add_pcie_node(lvms, &pch_pic_phandle, &pch_msi_phandle);
42
+
43
+ /*
46
+ /*
44
+ * Create uart fdt node in reverse order so that they appear
47
+ * Since lowmem region starts from 0, FDT base address is located
45
+ * in the finished device tree lowest address first
48
+ * at 2 MiB to avoid NULL pointer access.
46
+ */
49
+ *
47
+ for (i = VIRT_UART_COUNT; i-- > 0;) {
48
+ hwaddr base = VIRT_UART_BASE + i * VIRT_UART_SIZE;
49
+ int irq = VIRT_UART_IRQ + i - VIRT_GSI_BASE;
50
+ fdt_add_uart_node(lvms, &pch_pic_phandle, base, irq, i == 0);
51
+ }
52
+
53
+ fdt_add_rtc_node(lvms, &pch_pic_phandle);
54
+ fdt_add_ged_reset(lvms);
55
+ platform_bus_add_all_fdt_nodes(machine->fdt, "/platic",
56
+ VIRT_PLATFORM_BUS_BASEADDRESS,
57
+ VIRT_PLATFORM_BUS_SIZE,
58
+ VIRT_PLATFORM_BUS_IRQ);
59
+
60
+ /*
61
+ * Since lowmem region starts from 0 and Linux kernel legacy start address
62
+ * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer
63
+ * access. FDT size limit with 1 MiB.
64
+ * Put the FDT into the memory map as a ROM image: this will ensure
50
+ * Put the FDT into the memory map as a ROM image: this will ensure
65
+ * the FDT is copied again upon reset, even if addr points into RAM.
51
+ * the FDT is copied again upon reset, even if addr points into RAM.
66
+ */
52
+ */
67
+ qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size);
53
+ fdt_base = 2 * MiB;
68
+ rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE,
54
+ qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size);
69
+ &address_space_memory);
55
+ rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base);
70
+ qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
71
+ rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size));
72
+}
73
+
74
static void virt_done(Notifier *notifier, void *data)
75
{
76
LoongArchVirtMachineState *lvms = container_of(notifier,
77
LoongArchVirtMachineState, machine_done);
78
virt_build_smbios(lvms);
79
loongarch_acpi_setup(lvms);
80
+ virt_fdt_setup(lvms);
81
}
56
}
82
57
83
static void virt_powerdown_req(Notifier *notifier, void *opaque)
58
bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)
84
@@ -XXX,XX +XXX,XX @@ static DeviceState *create_platform_bus(DeviceState *pch_pic)
59
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
85
}
60
index XXXXXXX..XXXXXXX 100644
86
61
--- a/include/hw/loongarch/virt.h
87
static void virt_devices_init(DeviceState *pch_pic,
62
+++ b/include/hw/loongarch/virt.h
88
- LoongArchVirtMachineState *lvms,
63
@@ -XXX,XX +XXX,XX @@
89
- uint32_t *pch_pic_phandle,
64
#define VIRT_GED_MEM_ADDR (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN)
90
- uint32_t *pch_msi_phandle)
65
#define VIRT_GED_REG_ADDR (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN)
91
+ LoongArchVirtMachineState *lvms)
66
92
{
67
-#define VIRT_FDT_BASE 0x1c400000
93
MachineClass *mc = MACHINE_GET_CLASS(lvms);
68
-#define VIRT_FDT_SIZE 0x100000
94
DeviceState *gpex_dev;
95
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
96
gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);
97
}
98
99
- /* Add pcie node */
100
- fdt_add_pcie_node(lvms, pch_pic_phandle, pch_msi_phandle);
101
-
69
-
102
/*
70
struct LoongArchMachineState {
103
* Create uart fdt node in reverse order so that they appear
71
/*< private >*/
104
* in the finished device tree lowest address first
72
MachineState parent_obj;
105
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
106
serial_mm_init(get_system_memory(), base, 0,
107
qdev_get_gpio_in(pch_pic, irq),
108
115200, serial_hd(i), DEVICE_LITTLE_ENDIAN);
109
- fdt_add_uart_node(lvms, pch_pic_phandle, base, irq, i == 0);
110
}
111
112
/* Network init */
113
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
114
sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
115
qdev_get_gpio_in(pch_pic,
116
VIRT_RTC_IRQ - VIRT_GSI_BASE));
117
- fdt_add_rtc_node(lvms, pch_pic_phandle);
118
- fdt_add_ged_reset(lvms);
119
120
/* acpi ged */
121
lvms->acpi_ged = create_acpi_ged(pch_pic, lvms);
122
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
123
CPULoongArchState *env;
124
CPUState *cpu_state;
125
int cpu, pin, i, start, num;
126
- uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle;
127
128
/*
129
* Extended IRQ model.
130
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
131
memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR,
132
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
133
134
- /* Add cpu interrupt-controller */
135
- fdt_add_cpuic_node(lvms, &cpuintc_phandle);
136
-
137
for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
138
cpu_state = qemu_get_cpu(cpu);
139
cpudev = DEVICE(cpu_state);
140
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
141
}
142
}
143
144
- /* Add Extend I/O Interrupt Controller node */
145
- fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
146
-
147
pch_pic = qdev_new(TYPE_LOONGARCH_PIC);
148
num = VIRT_PCH_PIC_IRQ_NUM;
149
qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
150
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
151
qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
152
}
153
154
- /* Add PCH PIC node */
155
- fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle);
156
-
157
pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
158
start = num;
159
num = EXTIOI_IRQS - start;
160
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
161
qdev_get_gpio_in(extioi, i + start));
162
}
163
164
- /* Add PCH MSI node */
165
- fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle);
166
-
167
- virt_devices_init(pch_pic, lvms, &pch_pic_phandle, &pch_msi_phandle);
168
+ virt_devices_init(pch_pic, lvms);
169
}
170
171
static void virt_firmware_init(LoongArchVirtMachineState *lvms)
172
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
173
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
174
}
175
176
- create_fdt(lvms);
177
-
178
/* Create IOCSR space */
179
memory_region_init_io(&lvms->system_iocsr, OBJECT(machine), NULL,
180
machine, "iocsr", UINT64_MAX);
181
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
182
lacpu = LOONGARCH_CPU(cpu);
183
lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id;
184
}
185
- fdt_add_cpu_nodes(lvms);
186
- fdt_add_memory_nodes(machine);
187
fw_cfg_add_memory(machine);
188
189
/* Node0 memory */
190
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
191
memmap_table,
192
sizeof(struct memmap_entry) * (memmap_entries));
193
}
194
- fdt_add_fw_cfg_node(lvms);
195
- fdt_add_flash_node(lvms);
196
197
/* Initialize the IO interrupt subsystem */
198
virt_irq_init(lvms);
199
- platform_bus_add_all_fdt_nodes(machine->fdt, "/platic",
200
- VIRT_PLATFORM_BUS_BASEADDRESS,
201
- VIRT_PLATFORM_BUS_SIZE,
202
- VIRT_PLATFORM_BUS_IRQ);
203
lvms->machine_done.notify = virt_done;
204
qemu_add_machine_init_done_notifier(&lvms->machine_done);
205
/* connect powerdown request */
206
lvms->powerdown_notifier.notify = virt_powerdown_req;
207
qemu_register_powerdown_notifier(&lvms->powerdown_notifier);
208
209
- /*
210
- * Since lowmem region starts from 0 and Linux kernel legacy start address
211
- * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer
212
- * access. FDT size limit with 1 MiB.
213
- * Put the FDT into the memory map as a ROM image: this will ensure
214
- * the FDT is copied again upon reset, even if addr points into RAM.
215
- */
216
- qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size);
217
- rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE,
218
- &address_space_memory);
219
- qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
220
- rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size));
221
-
222
lvms->bootinfo.ram_size = ram_size;
223
loongarch_load_kernel(machine, &lvms->bootinfo);
224
}
225
--
73
--
226
2.43.5
74
2.31.1
diff view generated by jsdifflib
[PULL v2 1/6] target/loongarch: Fix vldi inst
[PULL v3 4/7] hw/loongarch: Improve fdt for LoongArch virt machine
1
From: Guo Hongyu <guohongyu24@mails.ucas.ac.cn>
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
2
3
Refer to the link below for a description of the vldi instructions:
3
Add new items into LoongArch FDT, including rtc and uart info.
4
https://jia.je/unofficial-loongarch-intrinsics-guide/lsx/misc/#synopsis_88
5
Fixed errors in vldi instruction implementation.
6
4
7
Signed-off-by: Guo Hongyu <guohongyu24@mails.ucas.ac.cn>
5
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
8
Tested-by: Xianglai Li <lixianglai@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
9
Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
7
Message-Id: <20221028014007.2718352-3-yangxiaojuan@loongson.cn>
10
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
8
Signed-off-by: Song Gao <gaosong@loongson.cn>
11
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
12
---
9
---
13
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +-
10
hw/loongarch/virt.c | 31 +++++++++++++++++++++++++++++++
14
1 file changed, 1 insertion(+), 1 deletion(-)
11
include/hw/pci-host/ls7a.h | 1 +
12
2 files changed, 32 insertions(+)
15
13
16
diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
14
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc
16
--- a/hw/loongarch/virt.c
19
+++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
17
+++ b/hw/loongarch/virt.c
20
@@ -XXX,XX +XXX,XX @@ static uint64_t vldi_get_value(DisasContext *ctx, uint32_t imm)
18
@@ -XXX,XX +XXX,XX @@
21
break;
19
#include "hw/display/ramfb.h"
22
case 1:
20
#include "hw/mem/pc-dimm.h"
23
/* data: {2{16'0, imm[7:0], 8'0}} */
21
24
- data = (t << 24) | (t << 8);
22
+static void fdt_add_rtc_node(LoongArchMachineState *lams)
25
+ data = (t << 40) | (t << 8);
23
+{
26
break;
24
+ char *nodename;
27
case 2:
25
+ hwaddr base = VIRT_RTC_REG_BASE;
28
/* data: {2{8'0, imm[7:0], 16'0}} */
26
+ hwaddr size = VIRT_RTC_LEN;
27
+ MachineState *ms = MACHINE(lams);
28
+
29
+ nodename = g_strdup_printf("/rtc@%" PRIx64, base);
30
+ qemu_fdt_add_subnode(ms->fdt, nodename);
31
+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc");
32
+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 0x0, base, size);
33
+ g_free(nodename);
34
+}
35
+
36
+static void fdt_add_uart_node(LoongArchMachineState *lams)
37
+{
38
+ char *nodename;
39
+ hwaddr base = VIRT_UART_BASE;
40
+ hwaddr size = VIRT_UART_SIZE;
41
+ MachineState *ms = MACHINE(lams);
42
+
43
+ nodename = g_strdup_printf("/serial@%" PRIx64, base);
44
+ qemu_fdt_add_subnode(ms->fdt, nodename);
45
+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a");
46
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size);
47
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000);
48
+ g_free(nodename);
49
+}
50
+
51
static void create_fdt(LoongArchMachineState *lams)
52
{
53
MachineState *ms = MACHINE(lams);
54
@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
55
qdev_get_gpio_in(pch_pic,
56
VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET),
57
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
58
+ fdt_add_uart_node(lams);
59
60
/* Network init */
61
for (i = 0; i < nb_nics; i++) {
62
@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
63
sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
64
qdev_get_gpio_in(pch_pic,
65
VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET));
66
+ fdt_add_rtc_node(lams);
67
68
pm_mem = g_new(MemoryRegion, 1);
69
memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops,
70
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
71
index XXXXXXX..XXXXXXX 100644
72
--- a/include/hw/pci-host/ls7a.h
73
+++ b/include/hw/pci-host/ls7a.h
74
@@ -XXX,XX +XXX,XX @@
75
#define VIRT_PCI_IRQS 48
76
#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
77
#define VIRT_UART_BASE 0x1fe001e0
78
+#define VIRT_UART_SIZE 0X100
79
#define VIRT_RTC_IRQ (PCH_PIC_IRQ_OFFSET + 3)
80
#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000)
81
#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100)
29
--
82
--
30
2.43.5
83
2.31.1
diff view generated by jsdifflib
[PULL v2 4/6] hw/loongarch/virt: Improve fdt table creation for CPU object
[PULL v3 5/7] hw/loongarch: Add TPM device for LoongArch virt machine
1
For CPU object, possible_cpu_arch_ids() function is used rather than
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
smp.cpus. With command -smp x, -device la464-loongarch-cpu, smp.cpus
3
is not accurate for all possible CPU objects, possible_cpu_arch_ids()
4
is used here.
5
2
6
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
3
Add TPM device for LoongArch virt machine, including
7
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
4
establish TPM acpi info and add TYPE_TPM_TIS_SYSBUS
5
to dynamic_sysbus_devices list.
6
7
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
8
Reviewed-by: Song Gao <gaosong@loongson.cn>
9
Message-Id: <20221028014007.2718352-4-yangxiaojuan@loongson.cn>
10
Signed-off-by: Song Gao <gaosong@loongson.cn>
8
---
11
---
9
hw/loongarch/virt.c | 39 +++++++++++++++++++++++++--------------
12
hw/loongarch/acpi-build.c | 51 ++++++++++++++++++++++++++++++++++++++-
10
1 file changed, 25 insertions(+), 14 deletions(-)
13
hw/loongarch/virt.c | 4 +++
14
2 files changed, 54 insertions(+), 1 deletion(-)
11
15
16
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/loongarch/acpi-build.c
19
+++ b/hw/loongarch/acpi-build.c
20
@@ -XXX,XX +XXX,XX @@
21
22
#include "hw/acpi/generic_event_device.h"
23
#include "hw/pci-host/gpex.h"
24
+#include "sysemu/tpm.h"
25
+#include "hw/platform-bus.h"
26
+#include "hw/acpi/aml-build.h"
27
28
#define ACPI_BUILD_ALIGN_SIZE 0x1000
29
#define ACPI_BUILD_TABLE_SIZE 0x20000
30
@@ -XXX,XX +XXX,XX @@ static void build_pci_device_aml(Aml *scope, LoongArchMachineState *lams)
31
acpi_dsdt_add_gpex(scope, &cfg);
32
}
33
34
+#ifdef CONFIG_TPM
35
+static void acpi_dsdt_add_tpm(Aml *scope, LoongArchMachineState *vms)
36
+{
37
+ PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
38
+ hwaddr pbus_base = VIRT_PLATFORM_BUS_BASEADDRESS;
39
+ SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());
40
+ MemoryRegion *sbdev_mr;
41
+ hwaddr tpm_base;
42
+
43
+ if (!sbdev) {
44
+ return;
45
+ }
46
+
47
+ tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
48
+ assert(tpm_base != -1);
49
+
50
+ tpm_base += pbus_base;
51
+
52
+ sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
53
+
54
+ Aml *dev = aml_device("TPM0");
55
+ aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
56
+ aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
57
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
58
+
59
+ Aml *crs = aml_resource_template();
60
+ aml_append(crs,
61
+ aml_memory32_fixed(tpm_base,
62
+ (uint32_t)memory_region_size(sbdev_mr),
63
+ AML_READ_WRITE));
64
+ aml_append(dev, aml_name_decl("_CRS", crs));
65
+ aml_append(scope, dev);
66
+}
67
+#endif
68
+
69
/* build DSDT */
70
static void
71
build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
72
@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
73
build_uart_device_aml(dsdt);
74
build_pci_device_aml(dsdt, lams);
75
build_la_ged_aml(dsdt, machine);
76
-
77
+#ifdef CONFIG_TPM
78
+ acpi_dsdt_add_tpm(dsdt, lams);
79
+#endif
80
/* System State Package */
81
scope = aml_scope("\\");
82
pkg = aml_package(4);
83
@@ -XXX,XX +XXX,XX @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
84
lams->oem_table_id);
85
}
86
87
+#ifdef CONFIG_TPM
88
+ /* TPM info */
89
+ if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
90
+ acpi_add_table(table_offsets, tables_blob);
91
+ build_tpm2(tables_blob, tables->linker,
92
+ tables->tcpalog, lams->oem_id,
93
+ lams->oem_table_id);
94
+ }
95
+#endif
96
/* Add tables supplied by user (if any) */
97
for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
98
unsigned len = acpi_table_len(u);
12
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
99
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
13
index XXXXXXX..XXXXXXX 100644
100
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/loongarch/virt.c
101
--- a/hw/loongarch/virt.c
15
+++ b/hw/loongarch/virt.c
102
+++ b/hw/loongarch/virt.c
16
@@ -XXX,XX +XXX,XX @@ static void create_fdt(LoongArchVirtMachineState *lvms)
103
@@ -XXX,XX +XXX,XX @@
17
static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms)
104
#include "hw/platform-bus.h"
105
#include "hw/display/ramfb.h"
106
#include "hw/mem/pc-dimm.h"
107
+#include "sysemu/tpm.h"
108
109
static void fdt_add_rtc_node(LoongArchMachineState *lams)
18
{
110
{
19
int num;
111
@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
20
- const MachineState *ms = MACHINE(lvms);
112
object_class_property_set_description(oc, "acpi",
21
- int smp_cpus = ms->smp.cpus;
113
"Enable ACPI");
22
+ MachineState *ms = MACHINE(lvms);
114
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
23
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
115
+#ifdef CONFIG_TPM
24
+ const CPUArchIdList *possible_cpus;
116
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
25
+ LoongArchCPU *cpu;
117
+#endif
26
+ CPUState *cs;
27
+ char *nodename, *map_path;
28
29
qemu_fdt_add_subnode(ms->fdt, "/cpus");
30
qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
31
qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
32
33
/* cpu nodes */
34
- for (num = smp_cpus - 1; num >= 0; num--) {
35
- char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
36
- LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num));
37
- CPUState *cs = CPU(cpu);
38
+ possible_cpus = mc->possible_cpu_arch_ids(ms);
39
+ for (num = 0; num < possible_cpus->len; num++) {
40
+ cs = possible_cpus->cpus[num].cpu;
41
+ if (cs == NULL) {
42
+ continue;
43
+ }
44
+
45
+ nodename = g_strdup_printf("/cpus/cpu@%d", num);
46
+ cpu = LOONGARCH_CPU(cs);
47
48
qemu_fdt_add_subnode(ms->fdt, nodename);
49
qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
50
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
51
cpu->dtb_compatible);
52
- if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
53
+ if (possible_cpus->cpus[num].props.has_node_id) {
54
qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
55
- ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
56
+ possible_cpus->cpus[num].props.node_id);
57
}
58
qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num);
59
qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
60
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms)
61
62
/*cpu map */
63
qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
64
+ for (num = 0; num < possible_cpus->len; num++) {
65
+ cs = possible_cpus->cpus[num].cpu;
66
+ if (cs == NULL) {
67
+ continue;
68
+ }
69
70
- for (num = smp_cpus - 1; num >= 0; num--) {
71
- char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num);
72
- char *map_path;
73
-
74
+ nodename = g_strdup_printf("/cpus/cpu@%d", num);
75
if (ms->smp.threads > 1) {
76
map_path = g_strdup_printf(
77
"/cpus/cpu-map/socket%d/core%d/thread%d",
78
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms)
79
num % ms->smp.cores);
80
}
81
qemu_fdt_add_path(ms->fdt, map_path);
82
- qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
83
+ qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", nodename);
84
85
g_free(map_path);
86
- g_free(cpu_path);
87
+ g_free(nodename);
88
}
89
}
118
}
90
119
120
static const TypeInfo loongarch_machine_types[] = {
91
--
121
--
92
2.43.5
122
2.31.1
diff view generated by jsdifflib
[PULL v2 6/6] target/loongarch: Use auto method with LASX feature
[PULL v3 6/7] target/loongarch: Add exception subcode
1
Like LSX feature, add type OnOffAuto for LASX feature setting.
1
We need subcodes to distinguish the same excode cs->exception_indexs,
2
such as EXCCODE_ADEF/EXCCODE_ADEM.
2
3
3
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
Signed-off-by: Song Gao <gaosong@loongson.cn>
4
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-ID: <20221101073210.3934280-1-gaosong@loongson.cn>
5
---
7
---
6
target/loongarch/cpu.c | 50 +++++++++++++++++++++++------------
8
target/loongarch/cpu.c | 7 +++--
7
target/loongarch/cpu.h | 2 ++
9
target/loongarch/cpu.h | 58 ++++++++++++++++++++++--------------------
8
target/loongarch/kvm/kvm.c | 53 ++++++++++++++++++++++++++++++++++++++
10
2 files changed, 36 insertions(+), 29 deletions(-)
9
3 files changed, 89 insertions(+), 16 deletions(-)
10
11
11
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
12
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/cpu.c
14
--- a/target/loongarch/cpu.c
14
+++ b/target/loongarch/cpu.c
15
+++ b/target/loongarch/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
16
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
16
uint32_t val;
17
env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
17
18
PC, (env->pc >> 2));
18
cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
19
} else {
19
+ if (cpu->lsx == ON_OFF_AUTO_OFF) {
20
- env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause);
20
+ cpu->lasx = ON_OFF_AUTO_OFF;
21
+ env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE,
21
+ if (cpu->lasx == ON_OFF_AUTO_ON) {
22
+ EXCODE_MCODE(cause));
22
+ error_setg(errp, "Failed to disable LSX since LASX is enabled");
23
+ env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE,
23
+ return;
24
+ EXCODE_SUBCODE(cause));
24
+ }
25
env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
25
+ }
26
FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
26
+
27
env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
27
if (kvm_enabled()) {
28
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
28
/* kvm feature detection in function kvm_arch_init_vcpu */
29
env->pc = env->CSR_TLBRENTRY;
29
return;
30
} else {
30
@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
31
env->pc = env->CSR_EENTRY;
31
error_setg(errp, "Failed to enable LSX in TCG mode");
32
- env->pc += cause * vec_size;
32
return;
33
+ env->pc += EXCODE_MCODE(cause) * vec_size;
33
}
34
}
34
+ } else {
35
qemu_log_mask(CPU_LOG_INT,
35
+ cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, 0);
36
"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
36
+ val = cpu->env.cpucfg[2];
37
}
38
39
cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value);
40
@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
41
42
static bool loongarch_get_lasx(Object *obj, Error **errp)
43
{
44
- LoongArchCPU *cpu = LOONGARCH_CPU(obj);
45
- bool ret;
46
-
47
- if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LASX)) {
48
- ret = true;
49
- } else {
50
- ret = false;
51
- }
52
- return ret;
53
+ return LOONGARCH_CPU(obj)->lasx != ON_OFF_AUTO_OFF;
54
}
55
56
static void loongarch_set_lasx(Object *obj, bool value, Error **errp)
57
{
58
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
59
+ uint32_t val;
60
61
- if (value) {
62
-    if (!FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
63
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1);
64
-    }
65
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 1);
66
- } else {
67
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0);
68
+ cpu->lasx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
69
+ if ((cpu->lsx == ON_OFF_AUTO_OFF) && (cpu->lasx == ON_OFF_AUTO_ON)) {
70
+ error_setg(errp, "Failed to enable LASX since lSX is disabled");
71
+ return;
72
+ }
73
+
74
+ if (kvm_enabled()) {
75
+ /* kvm feature detection in function kvm_arch_init_vcpu */
76
+ return;
77
}
78
+
79
+ /* LASX feature detection in TCG mode */
80
+ val = cpu->env.cpucfg[2];
81
+ if (cpu->lasx == ON_OFF_AUTO_ON) {
82
+ if (FIELD_EX32(val, CPUCFG2, LASX) == 0) {
83
+ error_setg(errp, "Failed to enable LASX in TCG mode");
84
+ return;
85
+ }
86
+ }
87
+
88
+ cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, value);
89
}
90
91
static bool loongarch_get_lbt(Object *obj, Error **errp)
92
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj)
93
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
94
95
cpu->lsx = ON_OFF_AUTO_AUTO;
96
+ cpu->lasx = ON_OFF_AUTO_AUTO;
97
object_property_add_bool(obj, "lsx", loongarch_get_lsx,
98
loongarch_set_lsx);
99
object_property_add_bool(obj, "lasx", loongarch_get_lasx,
100
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
37
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
101
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
102
--- a/target/loongarch/cpu.h
39
--- a/target/loongarch/cpu.h
103
+++ b/target/loongarch/cpu.h
40
+++ b/target/loongarch/cpu.h
104
@@ -XXX,XX +XXX,XX @@ typedef struct LoongArchTLB LoongArchTLB;
41
@@ -XXX,XX +XXX,XX @@ FIELD(FCSR0, CAUSE, 24, 5)
105
42
#define FP_DIV0 8
106
enum loongarch_features {
43
#define FP_INVALID 16
107
LOONGARCH_FEATURE_LSX,
44
108
+ LOONGARCH_FEATURE_LASX,
45
-#define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */
109
LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */
46
-#define EXCCODE_INT 0
110
LOONGARCH_FEATURE_PMU,
47
-#define EXCCODE_PIL 1
111
};
48
-#define EXCCODE_PIS 2
112
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
49
-#define EXCCODE_PIF 3
113
OnOffAuto lbt;
50
-#define EXCCODE_PME 4
114
OnOffAuto pmu;
51
-#define EXCCODE_PNR 5
115
OnOffAuto lsx;
52
-#define EXCCODE_PNX 6
116
+ OnOffAuto lasx;
53
-#define EXCCODE_PPI 7
117
54
-#define EXCCODE_ADEF 8 /* Different exception subcode */
118
/* 'compatible' string for this CPU for Linux device trees */
55
-#define EXCCODE_ADEM 8
119
const char *dtb_compatible;
56
-#define EXCCODE_ALE 9
120
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
57
-#define EXCCODE_BCE 10
121
index XXXXXXX..XXXXXXX 100644
58
-#define EXCCODE_SYS 11
122
--- a/target/loongarch/kvm/kvm.c
59
-#define EXCCODE_BRK 12
123
+++ b/target/loongarch/kvm/kvm.c
60
-#define EXCCODE_INE 13
124
@@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
61
-#define EXCCODE_IPE 14
125
}
62
-#define EXCCODE_FPD 15
126
return false;
63
-#define EXCCODE_SXD 16
127
64
-#define EXCCODE_ASXD 17
128
+ case LOONGARCH_FEATURE_LASX:
65
-#define EXCCODE_FPE 18 /* Different exception subcode */
129
+ attr.group = KVM_LOONGARCH_VM_FEAT_CTRL;
66
-#define EXCCODE_VFPE 18
130
+ attr.attr = KVM_LOONGARCH_VM_FEAT_LASX;
67
-#define EXCCODE_WPEF 19 /* Different exception subcode */
131
+ ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
68
-#define EXCCODE_WPEM 19
132
+ if (ret == 0) {
69
-#define EXCCODE_BTD 20
133
+ return true;
70
-#define EXCCODE_BTE 21
134
+ }
71
-#define EXCCODE_DBP 26 /* Reserved subcode used for debug */
72
+#define EXCODE(code, subcode) ( ((subcode) << 6) | (code) )
73
+#define EXCODE_MCODE(code) ( (code) & 0x3f )
74
+#define EXCODE_SUBCODE(code) ( (code) >> 6 )
135
+
75
+
136
+ /* Fallback to old kernel detect interface */
76
+#define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */
137
+ val = 0;
77
+#define EXCCODE_INT EXCODE(0, 0)
138
+ attr.group = KVM_LOONGARCH_VCPU_CPUCFG;
78
+#define EXCCODE_PIL EXCODE(1, 0)
139
+ /* Cpucfg2 */
79
+#define EXCCODE_PIS EXCODE(2, 0)
140
+ attr.attr = 2;
80
+#define EXCCODE_PIF EXCODE(3, 0)
141
+ attr.addr = (uint64_t)&val;
81
+#define EXCCODE_PME EXCODE(4, 0)
142
+ ret = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr);
82
+#define EXCCODE_PNR EXCODE(5, 0)
143
+ if (!ret) {
83
+#define EXCCODE_PNX EXCODE(6, 0)
144
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, &attr);
84
+#define EXCCODE_PPI EXCODE(7, 0)
145
+ if (ret) {
85
+#define EXCCODE_ADEF EXCODE(8, 0) /* Different exception subcode */
146
+ return false;
86
+#define EXCCODE_ADEM EXCODE(8, 1)
147
+ }
87
+#define EXCCODE_ALE EXCODE(9, 0)
148
+
88
+#define EXCCODE_BCE EXCODE(10, 0)
149
+ ret = FIELD_EX32((uint32_t)val, CPUCFG2, LASX);
89
+#define EXCCODE_SYS EXCODE(11, 0)
150
+ return (ret != 0);
90
+#define EXCCODE_BRK EXCODE(12, 0)
151
+ }
91
+#define EXCCODE_INE EXCODE(13, 0)
152
+ return false;
92
+#define EXCCODE_IPE EXCODE(14, 0)
153
+
93
+#define EXCCODE_FPD EXCODE(15, 0)
154
case LOONGARCH_FEATURE_LBT:
94
+#define EXCCODE_SXD EXCODE(16, 0)
155
/*
95
+#define EXCCODE_ASXD EXCODE(17, 0)
156
* Return all if all the LBT features are supported such as:
96
+#define EXCCODE_FPE EXCODE(18, 0) /* Different exception subcode */
157
@@ -XXX,XX +XXX,XX @@ static int kvm_cpu_check_lsx(CPUState *cs, Error **errp)
97
+#define EXCCODE_VFPE EXCODE(18, 1)
158
return 0;
98
+#define EXCCODE_WPEF EXCODE(19, 0) /* Different exception subcode */
159
}
99
+#define EXCCODE_WPEM EXCODE(19, 1)
160
100
+#define EXCCODE_BTD EXCODE(20, 0)
161
+static int kvm_cpu_check_lasx(CPUState *cs, Error **errp)
101
+#define EXCCODE_BTE EXCODE(21, 0)
162
+{
102
+#define EXCCODE_DBP EXCODE(26, 0) /* Reserved subcode used for debug */
163
+ CPULoongArchState *env = cpu_env(cs);
103
164
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
104
/* cpucfg[0] bits */
165
+ bool kvm_supported;
105
FIELD(CPUCFG0, PRID, 0, 32)
166
+
167
+ kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_LASX);
168
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 0);
169
+ if (cpu->lasx == ON_OFF_AUTO_ON) {
170
+ if (kvm_supported) {
171
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 1);
172
+ } else {
173
+ error_setg(errp, "'lasx' feature not supported by KVM on host");
174
+ return -ENOTSUP;
175
+ }
176
+ } else if ((cpu->lasx == ON_OFF_AUTO_AUTO) && kvm_supported) {
177
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 1);
178
+ }
179
+
180
+ return 0;
181
+}
182
+
183
static int kvm_cpu_check_lbt(CPUState *cs, Error **errp)
184
{
185
CPULoongArchState *env = cpu_env(cs);
186
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
187
error_report_err(local_err);
188
}
189
190
+ ret = kvm_cpu_check_lasx(cs, &local_err);
191
+ if (ret < 0) {
192
+ error_report_err(local_err);
193
+ }
194
+
195
ret = kvm_cpu_check_lbt(cs, &local_err);
196
if (ret < 0) {
197
error_report_err(local_err);
198
--
106
--
199
2.43.5
107
2.31.1
diff view generated by jsdifflib
[PULL v2 5/6] target/loongarch: Use auto method with LSX feature
[PULL v3 7/7] target/loongarch: Fix raise_mmu_exception() set wrong exception_index
1
Like LBT feature, add type OnOffAuto for LSX feature setting. Also
1
When the address is invalid address, We should set exception_index
2
add LSX feature detection with new VM ioctl command, fallback to old
2
according to MMUAccessType, and EXCCODE_ADEF need't update badinstr.
3
method if it is not supported.
3
Otherwise, The system enters an infinite loop. e.g:
4
run test.c on system mode
5
test.c:
6
#include<stdio.h>
4
7
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
8
void (*func)(int *);
6
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
9
10
int main()
11
{
12
int i = 8;
13
void *ptr = (void *)0x4000000000000000;
14
func = ptr;
15
func(&i);
16
return 0;
17
}
18
19
Signed-off-by: Song Gao <gaosong@loongson.cn>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-ID: <20221101073210.3934280-2-gaosong@loongson.cn>
7
---
22
---
8
target/loongarch/cpu.c | 38 +++++++++++++++------------
23
target/loongarch/cpu.c | 1 +
9
target/loongarch/cpu.h | 2 ++
24
target/loongarch/tlb_helper.c | 5 +++--
10
target/loongarch/kvm/kvm.c | 54 ++++++++++++++++++++++++++++++++++++++
25
2 files changed, 4 insertions(+), 2 deletions(-)
11
3 files changed, 77 insertions(+), 17 deletions(-)
12
26
13
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
27
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
14
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
15
--- a/target/loongarch/cpu.c
29
--- a/target/loongarch/cpu.c
16
+++ b/target/loongarch/cpu.c
30
+++ b/target/loongarch/cpu.c
17
@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
31
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
18
{
32
}
19
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
33
QEMU_FALLTHROUGH;
34
case EXCCODE_PIF:
35
+ case EXCCODE_ADEF:
36
cause = cs->exception_index;
37
update_badinstr = 0;
38
break;
39
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/loongarch/tlb_helper.c
42
+++ b/target/loongarch/tlb_helper.c
43
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
44
switch (tlb_error) {
45
default:
46
case TLBRET_BADADDR:
47
- cs->exception_index = EXCCODE_ADEM;
48
+ cs->exception_index = access_type == MMU_INST_FETCH
49
+ ? EXCCODE_ADEF : EXCCODE_ADEM;
50
break;
51
case TLBRET_NOMATCH:
52
/* No TLB match for a mapped address */
53
@@ -XXX,XX +XXX,XX @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
20
CPULoongArchState *env = &cpu->env;
54
CPULoongArchState *env = &cpu->env;
21
+ uint32_t data = 0;
55
hwaddr physical;
22
int i;
56
int prot;
23
57
- int ret = TLBRET_BADADDR;
24
for (i = 0; i < 21; i++) {
58
+ int ret;
25
@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
59
26
cpu->dtb_compatible = "loongarch,Loongson-3A5000";
60
/* Data access */
27
env->cpucfg[0] = 0x14c010; /* PRID */
61
ret = get_physical_address(env, &physical, &prot, address,
28
29
- uint32_t data = 0;
30
data = FIELD_DP32(data, CPUCFG1, ARCH, 2);
31
data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
32
data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
33
@@ -XXX,XX +XXX,XX @@ static void loongarch_la132_initfn(Object *obj)
34
{
35
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
36
CPULoongArchState *env = &cpu->env;
37
-
38
+ uint32_t data = 0;
39
int i;
40
41
for (i = 0; i < 21; i++) {
42
@@ -XXX,XX +XXX,XX @@ static void loongarch_la132_initfn(Object *obj)
43
cpu->dtb_compatible = "loongarch,Loongson-1C103";
44
env->cpucfg[0] = 0x148042; /* PRID */
45
46
- uint32_t data = 0;
47
data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
48
data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
49
data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
50
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
51
52
static bool loongarch_get_lsx(Object *obj, Error **errp)
53
{
54
- LoongArchCPU *cpu = LOONGARCH_CPU(obj);
55
- bool ret;
56
-
57
- if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
58
- ret = true;
59
- } else {
60
- ret = false;
61
- }
62
- return ret;
63
+ return LOONGARCH_CPU(obj)->lsx != ON_OFF_AUTO_OFF;
64
}
65
66
static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
67
{
68
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
69
+ uint32_t val;
70
71
- if (value) {
72
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1);
73
- } else {
74
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 0);
75
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0);
76
+ cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
77
+ if (kvm_enabled()) {
78
+ /* kvm feature detection in function kvm_arch_init_vcpu */
79
+ return;
80
}
81
+
82
+ /* LSX feature detection in TCG mode */
83
+ val = cpu->env.cpucfg[2];
84
+ if (cpu->lsx == ON_OFF_AUTO_ON) {
85
+ if (FIELD_EX32(val, CPUCFG2, LSX) == 0) {
86
+ error_setg(errp, "Failed to enable LSX in TCG mode");
87
+ return;
88
+ }
89
+ }
90
+
91
+ cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value);
92
}
93
94
static bool loongarch_get_lasx(Object *obj, Error **errp)
95
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj)
96
{
97
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
98
99
+ cpu->lsx = ON_OFF_AUTO_AUTO;
100
object_property_add_bool(obj, "lsx", loongarch_get_lsx,
101
loongarch_set_lsx);
102
object_property_add_bool(obj, "lasx", loongarch_get_lasx,
103
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj)
104
105
} else {
106
cpu->lbt = ON_OFF_AUTO_OFF;
107
+ cpu->pmu = ON_OFF_AUTO_OFF;
108
}
109
}
110
111
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
112
index XXXXXXX..XXXXXXX 100644
113
--- a/target/loongarch/cpu.h
114
+++ b/target/loongarch/cpu.h
115
@@ -XXX,XX +XXX,XX @@ typedef struct LoongArchTLB LoongArchTLB;
116
#endif
117
118
enum loongarch_features {
119
+ LOONGARCH_FEATURE_LSX,
120
LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */
121
LOONGARCH_FEATURE_PMU,
122
};
123
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
124
uint32_t phy_id;
125
OnOffAuto lbt;
126
OnOffAuto pmu;
127
+ OnOffAuto lsx;
128
129
/* 'compatible' string for this CPU for Linux device trees */
130
const char *dtb_compatible;
131
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/target/loongarch/kvm/kvm.c
134
+++ b/target/loongarch/kvm/kvm.c
135
@@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
136
{
137
int ret;
138
struct kvm_device_attr attr;
139
+ uint64_t val;
140
141
switch (feature) {
142
+ case LOONGARCH_FEATURE_LSX:
143
+ attr.group = KVM_LOONGARCH_VM_FEAT_CTRL;
144
+ attr.attr = KVM_LOONGARCH_VM_FEAT_LSX;
145
+ ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
146
+ if (ret == 0) {
147
+ return true;
148
+ }
149
+
150
+ /* Fallback to old kernel detect interface */
151
+ val = 0;
152
+ attr.group = KVM_LOONGARCH_VCPU_CPUCFG;
153
+ /* Cpucfg2 */
154
+ attr.attr = 2;
155
+ attr.addr = (uint64_t)&val;
156
+ ret = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr);
157
+ if (!ret) {
158
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, &attr);
159
+ if (ret) {
160
+ return false;
161
+ }
162
+
163
+ ret = FIELD_EX32((uint32_t)val, CPUCFG2, LSX);
164
+ return (ret != 0);
165
+ }
166
+ return false;
167
+
168
case LOONGARCH_FEATURE_LBT:
169
/*
170
* Return all if all the LBT features are supported such as:
171
@@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
172
return false;
173
}
174
175
+static int kvm_cpu_check_lsx(CPUState *cs, Error **errp)
176
+{
177
+ CPULoongArchState *env = cpu_env(cs);
178
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
179
+ bool kvm_supported;
180
+
181
+ kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_LSX);
182
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 0);
183
+ if (cpu->lsx == ON_OFF_AUTO_ON) {
184
+ if (kvm_supported) {
185
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 1);
186
+ } else {
187
+ error_setg(errp, "'lsx' feature not supported by KVM on this host");
188
+ return -ENOTSUP;
189
+ }
190
+ } else if ((cpu->lsx == ON_OFF_AUTO_AUTO) && kvm_supported) {
191
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 1);
192
+ }
193
+
194
+ return 0;
195
+}
196
+
197
static int kvm_cpu_check_lbt(CPUState *cs, Error **errp)
198
{
199
CPULoongArchState *env = cpu_env(cs);
200
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
201
brk_insn = val;
202
}
203
204
+ ret = kvm_cpu_check_lsx(cs, &local_err);
205
+ if (ret < 0) {
206
+ error_report_err(local_err);
207
+ }
208
+
209
ret = kvm_cpu_check_lbt(cs, &local_err);
210
if (ret < 0) {
211
error_report_err(local_err);
212
--
62
--
213
2.43.5
63
2.31.1
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Patchew 2.1-devel-b67e4c2

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