Convert all targets simultaneously, as the gen_intermediate_code
function disappears from the target. While there are possible
workarounds, they're larger than simply performing the conversion.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
include/exec/translator.h | 14 --------------
include/hw/core/tcg-cpu-ops.h | 13 +++++++++++++
target/alpha/cpu.h | 2 ++
target/arm/internals.h | 2 ++
target/avr/cpu.h | 2 ++
target/hexagon/cpu.h | 2 ++
target/hppa/cpu.h | 2 ++
target/i386/tcg/helper-tcg.h | 2 ++
target/loongarch/internals.h | 2 ++
target/m68k/cpu.h | 2 ++
target/microblaze/cpu.h | 2 ++
target/mips/tcg/tcg-internal.h | 2 ++
target/openrisc/cpu.h | 2 ++
target/ppc/cpu.h | 2 ++
target/riscv/cpu.h | 3 +++
target/rx/cpu.h | 2 ++
target/s390x/s390x-internal.h | 2 ++
target/sh4/cpu.h | 2 ++
target/sparc/cpu.h | 2 ++
target/tricore/cpu.h | 2 ++
target/xtensa/cpu.h | 2 ++
accel/tcg/cpu-exec.c | 8 +++++---
accel/tcg/translate-all.c | 8 +++++---
target/alpha/cpu.c | 1 +
target/alpha/translate.c | 4 ++--
target/arm/cpu.c | 1 +
target/arm/tcg/cpu-v7m.c | 1 +
target/arm/tcg/translate.c | 5 ++---
target/avr/cpu.c | 1 +
target/avr/translate.c | 6 +++---
target/hexagon/cpu.c | 1 +
target/hexagon/translate.c | 4 ++--
target/hppa/cpu.c | 1 +
target/hppa/translate.c | 4 ++--
target/i386/tcg/tcg-cpu.c | 1 +
target/i386/tcg/translate.c | 5 ++---
target/loongarch/cpu.c | 1 +
target/loongarch/tcg/translate.c | 4 ++--
target/m68k/cpu.c | 1 +
target/m68k/translate.c | 4 ++--
target/microblaze/cpu.c | 1 +
target/microblaze/translate.c | 4 ++--
target/mips/cpu.c | 1 +
target/mips/tcg/translate.c | 4 ++--
target/openrisc/cpu.c | 1 +
target/openrisc/translate.c | 4 ++--
target/ppc/cpu_init.c | 1 +
target/ppc/translate.c | 4 ++--
target/riscv/tcg/tcg-cpu.c | 1 +
target/riscv/translate.c | 4 ++--
target/rx/cpu.c | 1 +
target/rx/translate.c | 4 ++--
target/s390x/cpu.c | 1 +
target/s390x/tcg/translate.c | 4 ++--
target/sh4/cpu.c | 1 +
target/sh4/translate.c | 4 ++--
target/sparc/cpu.c | 1 +
target/sparc/translate.c | 4 ++--
target/tricore/cpu.c | 1 +
target/tricore/translate.c | 5 ++---
target/xtensa/cpu.c | 1 +
target/xtensa/translate.c | 4 ++--
62 files changed, 121 insertions(+), 62 deletions(-)
diff --git a/include/exec/translator.h b/include/exec/translator.h
index 41e2a41180..d70942a10f 100644
@@ -21,20 +21,6 @@
#include "qemu/bswap.h"
#include "exec/vaddr.h"
-/**
- * gen_intermediate_code
- * @cpu: cpu context
- * @tb: translation block
- * @max_insns: max number of instructions to translate
- * @pc: guest virtual program counter address
- * @host_pc: host physical program counter address
- *
- * This function must be provided by the target, which should create
- * the target-specific DisasContext, and then invoke translator_loop.
- */
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- vaddr pc, void *host_pc);
-
/**
* DisasJumpType:
* @DISAS_NEXT: Next instruction in program order.
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 663efb9133..2e3f1690f1 100644
@@ -24,6 +24,19 @@ struct TCGCPUOps {
* Called when the first CPU is realized.
*/
void (*initialize)(void);
+ /**
+ * @translate_code: Translate guest instructions to TCGOps
+ * @cpu: cpu context
+ * @tb: translation block
+ * @max_insns: max number of instructions to translate
+ * @pc: guest virtual program counter address
+ * @host_pc: host physical program counter address
+ *
+ * This function must be provided by the target, which should create
+ * the target-specific DisasContext, and then invoke translator_loop.
+ */
+ void (*translate_code)(CPUState *cpu, TranslationBlock *tb,
+ int *max_insns, vaddr pc, void *host_pc);
/**
* @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
*
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 3556d3227f..80562adfb5 100644
@@ -431,6 +431,8 @@ enum {
};
void alpha_translate_init(void);
+void alpha_translate_code(CPUState *cs, TranslationBlock *tb,
+ int *max_insns, vaddr pc, void *host_pc);
#define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
diff --git a/target/arm/internals.h b/target/arm/internals.h
index c3a5b1385f..863a84edf8 100644
@@ -357,6 +357,8 @@ void init_cpreg_list(ARMCPU *cpu);
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
void arm_translate_init(void);
+void arm_translate_code(CPUState *cs, TranslationBlock *tb,
+ int *max_insns, vaddr pc, void *host_pc);
void arm_cpu_register_gdb_commands(ARMCPU *cpu);
void aarch64_cpu_register_gdb_commands(ARMCPU *cpu, GString *,
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 4725535102..06f5ae4d1b 100644
@@ -183,6 +183,8 @@ static inline void set_avr_feature(CPUAVRState *env, int feature)
}
void avr_cpu_tcg_init(void);
+void avr_cpu_translate_code(CPUState *cs, TranslationBlock *tb,
+ int *max_insns, vaddr pc, void *host_pc);
int cpu_avr_exec(CPUState *cpu);
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 14e6e819c2..79e60d4bfa 100644
@@ -150,6 +150,8 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
typedef HexagonCPU ArchCPU;
void hexagon_translate_init(void);
+void hexagon_translate_code(CPUState *cs, TranslationBlock *tb,
+ int *max_insns, vaddr pc, void *host_pc);
#include "exec/cpu-all.h"
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index e45ba50a59..22a6510e08 100644
@@ -303,6 +303,8 @@ static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env)
}
void hppa_translate_init(void);
+void hppa_translate_code(CPUState *cs, TranslationBlock *tb,
+ int *max_insns, vaddr pc, void *host_pc);
#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h
index 696d6ef016..54d845379c 100644
@@ -59,6 +59,8 @@ static inline target_long lshift(target_long x, int n)
/* translate.c */
void tcg_x86_init(void);
+void x86_translate_code(CPUState *cs, TranslationBlock *tb,
+ int *max_insns, vaddr pc, void *host_pc);
/* excp_helper.c */
G_NORETURN void raise_exception(CPUX86State *env, int exception_index);
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index 0655ac948b..ad9cf4fc7a 100644
@@ -17,6 +17,8 @@
#define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS)
void loongarch_translate_init(void);
+void loongarch_translate_code(CPUState *cs, TranslationBlock *tb,
+ int *max_insns, vaddr pc, void *host_pc);
void G_NORETURN do_raise_exception(CPULoongArchState *env,
uint32_t exception,
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index b5bbeedb7a..ddb0f29f4a 100644
@@ -193,6 +193,8 @@ int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void m68k_tcg_init(void);
+void m68k_translate_code(CPUState *cs, TranslationBlock *tb,
+ int *max_insns, vaddr pc, void *host_pc);
void m68k_cpu_init_gdb(M68kCPU *cpu);
uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 3e5a3e5c60..f6879eee35 100644
@@ -398,6 +398,8 @@ static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val)
}
void mb_tcg_init(void);
+void mb_translate_code(CPUState *cs, TranslationBlock *tb,
+ int *max_insns, vaddr pc, void *host_pc);
#define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index aef032c48d..74fc1309a7 100644
@@ -16,6 +16,8 @@
#include "cpu.h"
void mips_tcg_init(void);
+void mips_translate_code(CPUState *cs, TranslationBlock *tb,
+ int *max_insns, vaddr pc, void *host_pc);
void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
G_NORETURN void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index c9fe9ae12d..b97d2ffdd2 100644
@@ -301,6 +301,8 @@ void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void openrisc_translate_init(void);
+void openrisc_translate_code(CPUState *cs, TranslationBlock *tb,
+ int *max_insns, vaddr pc, void *host_pc);
int print_insn_or1k(bfd_vma addr, disassemble_info *info);
#ifndef CONFIG_USER_ONLY
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 2ffac2ed03..0b8b4c0517 100644
@@ -1581,6 +1581,8 @@ extern const VMStateDescription vmstate_ppc_cpu;
/