[v1] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

[RFC 0/1] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

Paolo Savini posted 1 patch 1 year, 1 month ago

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Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

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target/riscv/insn_trans/trans_rvv.c.inc | 125 +++++++++++++++---------
1 file changed, 78 insertions(+), 47 deletions(-)

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[RFC 0/1] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

Posted by Paolo Savini 1 year, 1 month ago

Following the reviews on the previous version:

- RFC v1: https://lore.kernel.org/all/20241218170840.1090473-1-paolo.savini@embecosm.com/
- Review: https://lore.kernel.org/all/e8fb908d-4723-417a-bf88-b4050432ddad@linaro.org/

we apply the following fixes:

- Fall back to using the helper function if vstart != 0 at the beginning
  of the iterations and refactor the setting of the function arguments
  accordignly.
- Add mark_vs_dirty before performing the memory operations.
- Loosen the atomicity constraints and apply only MO_ATOM_IFALIGN_PAIR
  for element sizes MO_16, MO_32 and MO_64.
- Change the way we update vstart in order to set vstart to 0 if it's the last
  iteration.
- Fix the indentation.

We also rephrase the commit message to better reflect the new behaviour of the
patch.

Many thanks Richard for the thorough review and explanations.

Cc: Richard Handerson <richard.henderson@linaro.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Weiwei Li <liwei1518@gmail.com>
Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: Helene Chelin <helene.chelin@embecosm.com>
Cc: Nathan Egge <negge@google.com>
Cc: Max Chou <max.chou@sifive.com>
Cc: Jeremy Bennett <jeremy.bennett@embecosm.com>
Cc: Craig Blackmore <craig.blackmore@embecosm.com>


Paolo Savini (1):
  target/riscv: use tcg ops generation to emulate whole reg rvv
    loads/stores.

 target/riscv/insn_trans/trans_rvv.c.inc | 125 +++++++++++++++---------
 1 file changed, 78 insertions(+), 47 deletions(-)

-- 
2.34.1