The following changes since commit 3e9793ab01904144c204589811e0e879109a9713:
Merge tag 'qga-pull-2024-12-18' of https://github.com/kostyanf14/qemu into staging (2024-12-18 20:24:59 -0500)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20241220
for you to fetch changes up to 2fc8f50eadad5dcc99bc5de1333808b9de47a097:
target/riscv: add support for RV64 Xiangshan Nanhu CPU (2024-12-20 11:22:47 +1000)
----------------------------------------------------------------
RISC-V PR for 10.0
* Correct the validness check of iova
* Fix APLIC in_clrip and clripnum write emulation
* Support riscv-iommu-sys device
* Add Tenstorrent Ascalon CPU
* Add AIA userspace irqchip_split support
* Add Microblaze V generic board
* Upgrade ACPI SPCR table to support SPCR table revision 4 format
* Remove tswap64() calls from HTIF
* Support 64-bit address of initrd
* Introduce svukte ISA extension
* Support ssstateen extension
* Support for RV64 Xiangshan Nanhu CPU
----------------------------------------------------------------
Anton Blanchard (1):
target/riscv: Add Tenstorrent Ascalon CPU
Daniel Henrique Barboza (15):
hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init()
hw/riscv/riscv-iommu: parametrize CAP.IGS
hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support
hw/riscv/riscv-iommu: implement reset protocol
docs/specs: add riscv-iommu-sys information
hw/intc/riscv_aplic: rename is_kvm_aia()
hw/riscv/virt.c: reduce virt_use_kvm_aia() usage
hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic()
target/riscv/kvm: consider irqchip_split() in aia_create()
hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers
hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic
target/riscv/kvm: remove irqchip_split() restriction
docs: update riscv/virt.rst with kernel-irqchip=split support
target/riscv/tcg: hide warn for named feats when disabling via priv_ver
target/riscv: add ssstateen
Fea.Wang (6):
target/riscv: Add svukte extension capability variable
target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled
target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled
target/riscv: Check memory access to meet svukte rule
target/riscv: Expose svukte ISA extension
target/riscv: Check svukte is not enabled in RV32
Jason Chien (1):
hw/riscv/riscv-iommu.c: Correct the validness check of iova
Jim Shu (3):
hw/riscv: Support to load DTB after 3GB memory on 64-bit system.
hw/riscv: Add a new struct RISCVBootInfo
hw/riscv: Add the checking if DTB overlaps to kernel or initrd
MollyChen (1):
target/riscv: add support for RV64 Xiangshan Nanhu CPU
Philippe Mathieu-Daudé (5):
MAINTAINERS: Cover RISC-V HTIF interface
hw/char/riscv_htif: Explicit little-endian implementation
hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses
target/riscv: Include missing headers in 'vector_internals.h'
target/riscv: Include missing headers in 'internals.h'
Sai Pavan Boddu (1):
hw/riscv: Add Microblaze V generic board
Sia Jee Heng (3):
qtest: allow SPCR acpi table changes
hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format
tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V
Sunil V L (1):
hw/riscv/virt: Add IOMMU as platform device if the option is set
Tomasz Jeznach (1):
hw/riscv: add riscv-iommu-sys platform device
Yong-Xuan Wang (1):
hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation
MAINTAINERS | 8 +
docs/specs/index.rst | 1 +
docs/specs/riscv-aia.rst | 83 ++++++++++
docs/specs/riscv-iommu.rst | 30 +++-
docs/system/riscv/microblaze-v-generic.rst | 42 +++++
docs/system/riscv/virt.rst | 17 ++
docs/system/target-riscv.rst | 1 +
hw/riscv/riscv-iommu-bits.h | 6 +
hw/riscv/riscv-iommu.h | 5 +
include/hw/acpi/acpi-defs.h | 7 +-
include/hw/acpi/aml-build.h | 2 +-
include/hw/intc/riscv_aplic.h | 8 +
include/hw/riscv/boot.h | 28 +++-
include/hw/riscv/iommu.h | 10 +-
include/hw/riscv/virt.h | 6 +-
target/riscv/cpu-qom.h | 2 +
target/riscv/cpu_bits.h | 2 +
target/riscv/cpu_cfg.h | 2 +
target/riscv/internals.h | 3 +
target/riscv/vector_internals.h | 1 +
hw/acpi/aml-build.c | 20 ++-
hw/arm/virt-acpi-build.c | 8 +-
hw/char/riscv_htif.c | 15 +-
hw/intc/riscv_aplic.c | 74 +++++++--
hw/loongarch/acpi-build.c | 6 +-
hw/riscv/boot.c | 100 +++++++----
hw/riscv/microblaze-v-generic.c | 184 +++++++++++++++++++++
hw/riscv/microchip_pfsoc.c | 13 +-
hw/riscv/opentitan.c | 4 +-
hw/riscv/riscv-iommu-pci.c | 21 +++
hw/riscv/riscv-iommu-sys.c | 256 +++++++++++++++++++++++++++++
hw/riscv/riscv-iommu.c | 137 ++++++++++-----
hw/riscv/sifive_e.c | 4 +-
hw/riscv/sifive_u.c | 18 +-
hw/riscv/spike.c | 14 +-
hw/riscv/virt-acpi-build.c | 12 +-
hw/riscv/virt.c | 159 +++++++++++++++---
target/riscv/cpu.c | 101 ++++++++++++
target/riscv/cpu_helper.c | 55 +++++++
target/riscv/csr.c | 7 +
target/riscv/kvm/kvm-cpu.c | 43 ++---
target/riscv/tcg/tcg-cpu.c | 27 ++-
hw/riscv/Kconfig | 8 +
hw/riscv/meson.build | 3 +-
hw/riscv/trace-events | 4 +
tests/data/acpi/riscv64/virt/SPCR | Bin 80 -> 90 bytes
46 files changed, 1380 insertions(+), 177 deletions(-)
create mode 100644 docs/specs/riscv-aia.rst
create mode 100644 docs/system/riscv/microblaze-v-generic.rst
create mode 100644 hw/riscv/microblaze-v-generic.c
create mode 100644 hw/riscv/riscv-iommu-sys.c