The following changes since commit ece5f8374d0416a339f0c0a9399faa2c42d4ad6f:

Merge tag 'linux-user-for-7.2-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2022-11-03 10:55:05 -0400)

https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20221104

for you to fetch changes up to 2419978cb09e11bc53a07d4de5621424d2a6a86d:

target/loongarch: Fix emulation of float-point disable exception (2022-11-04 17:10:53 +0800)

pull-loongarch-20221104

v2:

- fix win32/win64 complie error;

- Add Rui Wang' patches.

Rui Wang (2):

target/loongarch: Adjust the layout of hardware flags bit fields

target/loongarch: Fix emulation of float-point disable exception

Song Gao (2):

target/loongarch: Add exception subcode

target/loongarch: Fix raise_mmu_exception() set wrong exception_index

Xiaojuan Yang (5):

hw/intc: Convert the memops to with_attrs in LoongArch extioi

hw/intc: Fix LoongArch extioi coreisr accessing

hw/loongarch: Load FDT table into dram memory space

hw/loongarch: Improve fdt for LoongArch virt machine

hw/loongarch: Add TPM device for LoongArch virt machine

hw/intc/loongarch_extioi.c | 41 +++++++------

hw/intc/trace-events | 3 +-

hw/loongarch/acpi-build.c | 51 +++++++++++++++-

hw/loongarch/virt.c | 53 ++++++++++++++---

include/hw/loongarch/virt.h | 3 -

include/hw/pci-host/ls7a.h | 1 +

target/loongarch/cpu.c | 10 +++-

target/loongarch/cpu.h | 69 +++++++++++++---------

target/loongarch/insn_trans/trans_farith.c.inc | 30 ++++++++++

target/loongarch/insn_trans/trans_fcmp.c.inc | 11 +++-

target/loongarch/insn_trans/trans_fmemory.c.inc | 34 +++++++++--

target/loongarch/insn_trans/trans_fmov.c.inc | 29 ++++++++-

target/loongarch/insn_trans/trans_privileged.c.inc | 2 +-

target/loongarch/iocsr_helper.c | 19 +++---

target/loongarch/tlb_helper.c | 5 +-

target/loongarch/translate.c | 6 +-

16 files changed, 283 insertions(+), 84 deletions(-)

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Converting the MemoryRegionOps read/write handlers to

with_attrs in LoongArch extioi emulation.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-Id: <20221021015307.2570844-2-yangxiaojuan@loongson.cn>

Signed-off-by: Song Gao <gaosong@loongson.cn>

hw/intc/loongarch_extioi.c | 31 +++++++++++++++++--------------

hw/intc/trace-events | 3 +--

2 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c

--- a/hw/intc/loongarch_extioi.c

+++ b/hw/intc/loongarch_extioi.c

@@ -XXX,XX +XXX,XX @@ static void extioi_setirq(void *opaque, int irq, int level)

extioi_update_irq(s, irq, level);

-static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size)

+static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,

+ unsigned size, MemTxAttrs attrs)

LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);

unsigned long offset = addr & 0xffff;

- uint32_t index, cpu, ret = 0;

+ uint32_t index, cpu;

switch (offset) {

case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:

index = (offset - EXTIOI_NODETYPE_START) >> 2;

- ret = s->nodetype[index];

+ *data = s->nodetype[index];

break;

case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:

index = (offset - EXTIOI_IPMAP_START) >> 2;

- ret = s->ipmap[index];

+ *data = s->ipmap[index];

break;

case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:

index = (offset - EXTIOI_ENABLE_START) >> 2;

- ret = s->enable[index];

+ *data = s->enable[index];

break;

case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:

index = (offset - EXTIOI_BOUNCE_START) >> 2;

- ret = s->bounce[index];

+ *data = s->bounce[index];

break;

case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:

index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;

cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;

- ret = s->coreisr[cpu][index];

+ *data = s->coreisr[cpu][index];

break;

case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:

index = (offset - EXTIOI_COREMAP_START) >> 2;

- ret = s->coremap[index];

+ *data = s->coremap[index];

break;

default:

break;

- trace_loongarch_extioi_readw(addr, ret);

- return ret;

+ trace_loongarch_extioi_readw(addr, *data);

+ return MEMTX_OK;

static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\

@@ -XXX,XX +XXX,XX @@ static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\

-static void extioi_writew(void *opaque, hwaddr addr,

- uint64_t val, unsigned size)

+static MemTxResult extioi_writew(void *opaque, hwaddr addr,

+ uint64_t val, unsigned size,

+ MemTxAttrs attrs)

{

LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);

int i, cpu, index, old_data, irq;

@@ -XXX,XX +XXX,XX @@ static void extioi_writew(void *opaque, hwaddr addr,

default:

break;

}

+ return MEMTX_OK;

}

static const MemoryRegionOps extioi_ops = {

- .read = extioi_readw,

- .write = extioi_writew,

+ .read_with_attrs = extioi_readw,

+ .write_with_attrs = extioi_writew,

.impl.min_access_size = 4,

.impl.max_access_size = 4,

.valid.min_access_size = 4,

diff --git a/hw/intc/trace-events b/hw/intc/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/trace-events

+++ b/hw/intc/trace-events

@@ -XXX,XX +XXX,XX @@ loongarch_msi_set_irq(int irq_num) "set msi irq %d"

# loongarch_extioi.c

loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d"

-loongarch_extioi_readw(uint64_t addr, uint32_t val) "addr: 0x%"PRIx64 "val: 0x%x"

+loongarch_extioi_readw(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64

loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64

-

2.31.1

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

1. When cpu read or write extioi COREISR reg, it should access

the reg belonged to itself, so the cpu index of 's->coreisr'

is current cpu number. Using MemTxAttrs' requester_id to get

the cpu index.

2. it need not to mask 0x1f when calculate the coreisr array index.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-Id: <20221021015307.2570844-3-yangxiaojuan@loongson.cn>

Signed-off-by: Song Gao <gaosong@loongson.cn>

hw/intc/loongarch_extioi.c | 10 ++++++----

target/loongarch/iocsr_helper.c | 19 +++++++++++--------

2 files changed, 17 insertions(+), 12 deletions(-)

@@ -XXX,XX +XXX,XX @@ static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,

*data = s->bounce[index];

break;

case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:

- index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;

- cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;

+ index = (offset - EXTIOI_COREISR_START) >> 2;

+ /* using attrs to get current cpu index */

+ cpu = attrs.requester_id;

*data = s->coreisr[cpu][index];

break;

case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:

@@ -XXX,XX +XXX,XX @@ static MemTxResult extioi_writew(void *opaque, hwaddr addr,

s->bounce[index] = val;

break;

case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:

- index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;

- cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;

+ index = (offset - EXTIOI_COREISR_START) >> 2;

+ /* using attrs to get current cpu index */

+ cpu = attrs.requester_id;

old_data = s->coreisr[cpu][index];

s->coreisr[cpu][index] = old_data & ~val;

/* write 1 to clear interrrupt */

diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/loongarch/iocsr_helper.c

+++ b/target/loongarch/iocsr_helper.c

@@ -XXX,XX +XXX,XX @@

#include "exec/cpu_ldst.h"

#include "tcg/tcg-ldst.h"

+#define GET_MEMTXATTRS(cas) \

+ ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})

+

uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)

{

return address_space_ldub(&env->address_space_iocsr, r_addr,

- MEMTXATTRS_UNSPECIFIED, NULL);

+ GET_MEMTXATTRS(env), NULL);

uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)

{

return address_space_lduw(&env->address_space_iocsr, r_addr,

- MEMTXATTRS_UNSPECIFIED, NULL);

+ GET_MEMTXATTRS(env), NULL);

}

uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)

{

return address_space_ldl(&env->address_space_iocsr, r_addr,

- MEMTXATTRS_UNSPECIFIED, NULL);

+ GET_MEMTXATTRS(env), NULL);

}

uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)

{

return address_space_ldq(&env->address_space_iocsr, r_addr,

- MEMTXATTRS_UNSPECIFIED, NULL);

+ GET_MEMTXATTRS(env), NULL);

}

void helper_iocsrwr_b(CPULoongArchState *env, target_ulong w_addr,

target_ulong val)

{

address_space_stb(&env->address_space_iocsr, w_addr,

- val, MEMTXATTRS_UNSPECIFIED, NULL);

+ val, GET_MEMTXATTRS(env), NULL);

}

void helper_iocsrwr_h(CPULoongArchState *env, target_ulong w_addr,

target_ulong val)

{

address_space_stw(&env->address_space_iocsr, w_addr,

- val, MEMTXATTRS_UNSPECIFIED, NULL);

+ val, GET_MEMTXATTRS(env), NULL);

}

void helper_iocsrwr_w(CPULoongArchState *env, target_ulong w_addr,

target_ulong val)

{

address_space_stl(&env->address_space_iocsr, w_addr,

- val, MEMTXATTRS_UNSPECIFIED, NULL);

+ val, GET_MEMTXATTRS(env), NULL);

}

void helper_iocsrwr_d(CPULoongArchState *env, target_ulong w_addr,

target_ulong val)

{

address_space_stq(&env->address_space_iocsr, w_addr,

- val, MEMTXATTRS_UNSPECIFIED, NULL);

+ val, GET_MEMTXATTRS(env), NULL);

}

2.31.1

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Load FDT table into dram memory space, and the addr is 2 MiB.

Since lowmem region starts from 0, FDT base address is located

at 2 MiB to avoid NULL pointer access.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Acked-by: Song Gao <gaosong@loongson.cn>

Message-Id: <20221028014007.2718352-2-yangxiaojuan@loongson.cn>

Signed-off-by: Song Gao <gaosong@loongson.cn>

hw/loongarch/virt.c | 18 +++++++++++-------

include/hw/loongarch/virt.h | 3 ---

2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c

--- a/hw/loongarch/virt.c

+++ b/hw/loongarch/virt.c

@@ -XXX,XX +XXX,XX @@ static void fdt_add_pcie_node(const LoongArchMachineState *lams)

1, FDT_PCI_RANGE_MMIO, 2, base_mmio,

2, base_mmio, 2, size_mmio);

g_free(nodename);

- qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size);

static void fdt_add_irqchip_node(LoongArchMachineState *lams)

@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)

MemoryRegion *address_space_mem = get_system_memory();

LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);

int i;

+ hwaddr fdt_base;

if (!cpu_model) {

cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");

@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)

lams->machine_done.notify = virt_machine_done;

qemu_add_machine_init_done_notifier(&lams->machine_done);

fdt_add_pcie_node(lams);

-

- /* load fdt */

- MemoryRegion *fdt_rom = g_new(MemoryRegion, 1);

- memory_region_init_rom(fdt_rom, NULL, "fdt", VIRT_FDT_SIZE, &error_fatal);

- memory_region_add_subregion(get_system_memory(), VIRT_FDT_BASE, fdt_rom);

- rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, VIRT_FDT_BASE);

+ /*

+ * Since lowmem region starts from 0, FDT base address is located

+ * at 2 MiB to avoid NULL pointer access.

+ *

+ * Put the FDT into the memory map as a ROM image: this will ensure

+ * the FDT is copied again upon reset, even if addr points into RAM.

+ */

+ fdt_base = 2 * MiB;

+ qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size);

+ rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base);

bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)

diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/loongarch/virt.h

+++ b/include/hw/loongarch/virt.h

@@ -XXX,XX +XXX,XX @@

#define VIRT_GED_MEM_ADDR (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN)

#define VIRT_GED_REG_ADDR (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN)

-#define VIRT_FDT_BASE 0x1c400000

-#define VIRT_FDT_SIZE 0x100000

struct LoongArchMachineState {

/*< private >*/

MachineState parent_obj;

2.31.1

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Add new items into LoongArch FDT, including rtc and uart info.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>

hw/loongarch/virt.c | 31 +++++++++++++++++++++++++++++++

include/hw/pci-host/ls7a.h | 1 +

2 files changed, 32 insertions(+)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c

--- a/hw/loongarch/virt.c

+++ b/hw/loongarch/virt.c

#include "hw/display/ramfb.h"

#include "hw/mem/pc-dimm.h"

+static void fdt_add_rtc_node(LoongArchMachineState *lams)

+ char *nodename;

+ hwaddr base = VIRT_RTC_REG_BASE;

+ hwaddr size = VIRT_RTC_LEN;

+ MachineState *ms = MACHINE(lams);

+ nodename = g_strdup_printf("/rtc@%" PRIx64, base);

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc");

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 0x0, base, size);

+ g_free(nodename);

+static void fdt_add_uart_node(LoongArchMachineState *lams)

+ char *nodename;

+ hwaddr base = VIRT_UART_BASE;

+ hwaddr size = VIRT_UART_SIZE;

+ MachineState *ms = MACHINE(lams);

+ nodename = g_strdup_printf("/serial@%" PRIx64, base);

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a");

+ qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size);

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000);

+ g_free(nodename);

static void create_fdt(LoongArchMachineState *lams)

MachineState *ms = MACHINE(lams);

@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *

qdev_get_gpio_in(pch_pic,

VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET),

115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);

+ fdt_add_uart_node(lams);

/* Network init */

for (i = 0; i < nb_nics; i++) {

@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *

sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,

qdev_get_gpio_in(pch_pic,

VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET));

+ fdt_add_rtc_node(lams);

pm_mem = g_new(MemoryRegion, 1);

memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops,

diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h

--- a/include/hw/pci-host/ls7a.h

+++ b/include/hw/pci-host/ls7a.h

@@ -XXX,XX +XXX,XX @@

#define VIRT_PCI_IRQS 48

#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)

#define VIRT_UART_BASE 0x1fe001e0

+#define VIRT_UART_SIZE 0X100

#define VIRT_RTC_IRQ (PCH_PIC_IRQ_OFFSET + 3)

#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000)

#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100)

2.31.1

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Add TPM device for LoongArch virt machine, including

establish TPM acpi info and add TYPE_TPM_TIS_SYSBUS

to dynamic_sysbus_devices list.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>

hw/loongarch/acpi-build.c | 51 ++++++++++++++++++++++++++++++++++++++-

hw/loongarch/virt.c | 4 +++

2 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c

--- a/hw/loongarch/acpi-build.c

+++ b/hw/loongarch/acpi-build.c

#include "hw/acpi/generic_event_device.h"

#include "hw/pci-host/gpex.h"

+#include "sysemu/tpm.h"

+#include "hw/platform-bus.h"

+#include "hw/acpi/aml-build.h"

#define ACPI_BUILD_ALIGN_SIZE 0x1000

#define ACPI_BUILD_TABLE_SIZE 0x20000

@@ -XXX,XX +XXX,XX @@ static void build_pci_device_aml(Aml *scope, LoongArchMachineState *lams)

acpi_dsdt_add_gpex(scope, &cfg);

}

+#ifdef CONFIG_TPM

+static void acpi_dsdt_add_tpm(Aml *scope, LoongArchMachineState *vms)

+{

+ PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);

+ hwaddr pbus_base = VIRT_PLATFORM_BUS_BASEADDRESS;

+ SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());

+ MemoryRegion *sbdev_mr;

+ hwaddr tpm_base;

+

+ if (!sbdev) {

+ return;

+ }

+

+ tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);

+ assert(tpm_base != -1);

+

+ tpm_base += pbus_base;

+

+ sbdev_mr = sysbus_mmio_get_region(sbdev, 0);

+

+ Aml *dev = aml_device("TPM0");

+ aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));

+ aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));

+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));

+

+ Aml *crs = aml_resource_template();

+ aml_append(crs,

+ aml_memory32_fixed(tpm_base,

+ (uint32_t)memory_region_size(sbdev_mr),

+ AML_READ_WRITE));

+ aml_append(dev, aml_name_decl("_CRS", crs));

+ aml_append(scope, dev);

+}

+#endif

+

/* build DSDT */

static void

build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)

@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)

build_uart_device_aml(dsdt);

build_pci_device_aml(dsdt, lams);

build_la_ged_aml(dsdt, machine);

-

+#ifdef CONFIG_TPM

+ acpi_dsdt_add_tpm(dsdt, lams);

+#endif

/* System State Package */

scope = aml_scope("\\");

pkg = aml_package(4);

@@ -XXX,XX +XXX,XX @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)

lams->oem_table_id);

}

+#ifdef CONFIG_TPM

+ /* TPM info */

+ if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {

+ acpi_add_table(table_offsets, tables_blob);

+ build_tpm2(tables_blob, tables->linker,

+ tables->tcpalog, lams->oem_id,

+ lams->oem_table_id);

+ }

+#endif

/* Add tables supplied by user (if any) */

for (u = acpi_table_first(); u; u = acpi_table_next(u)) {

unsigned len = acpi_table_len(u);

@@ -XXX,XX +XXX,XX @@

#include "hw/platform-bus.h"

#include "hw/display/ramfb.h"

#include "hw/mem/pc-dimm.h"

+#include "sysemu/tpm.h"

static void fdt_add_rtc_node(LoongArchMachineState *lams)

{

@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)

object_class_property_set_description(oc, "acpi",

"Enable ACPI");

machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);

+#ifdef CONFIG_TPM

+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);

+#endif

}

static const TypeInfo loongarch_machine_types[] = {

2.31.1

We need subcodes to distinguish the same excode cs->exception_indexs,

such as EXCCODE_ADEF/EXCCODE_ADEM.

Signed-off-by: Song Gao <gaosong@loongson.cn>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-ID: <20221101073210.3934280-1-gaosong@loongson.cn>

target/loongarch/cpu.c | 7 +++--

target/loongarch/cpu.h | 58 ++++++++++++++++++++++--------------------

2 files changed, 36 insertions(+), 29 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c

--- a/target/loongarch/cpu.c

+++ b/target/loongarch/cpu.c

@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)

env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,

PC, (env->pc >> 2));

} else {

- env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause);

+ env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE,

+ EXCODE_MCODE(cause));

+ env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE,

+ EXCODE_SUBCODE(cause));

env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,

FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));

env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,

@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)

env->pc = env->CSR_TLBRENTRY;

} else {

env->pc = env->CSR_EENTRY;

- env->pc += cause * vec_size;

+ env->pc += EXCODE_MCODE(cause) * vec_size;

}

qemu_log_mask(CPU_LOG_INT,

"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h

--- a/target/loongarch/cpu.h

+++ b/target/loongarch/cpu.h

@@ -XXX,XX +XXX,XX @@ FIELD(FCSR0, CAUSE, 24, 5)

#define FP_DIV0 8

#define FP_INVALID 16

-#define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */

-#define EXCCODE_INT 0

-#define EXCCODE_PIL 1

-#define EXCCODE_PIS 2

-#define EXCCODE_PIF 3

-#define EXCCODE_PME 4

-#define EXCCODE_PNR 5

-#define EXCCODE_PNX 6

-#define EXCCODE_PPI 7

-#define EXCCODE_ADEF 8 /* Different exception subcode */

-#define EXCCODE_ADEM 8

-#define EXCCODE_ALE 9

-#define EXCCODE_BCE 10

-#define EXCCODE_SYS 11

-#define EXCCODE_BRK 12

-#define EXCCODE_INE 13

-#define EXCCODE_IPE 14

-#define EXCCODE_FPD 15

-#define EXCCODE_SXD 16

-#define EXCCODE_ASXD 17

-#define EXCCODE_FPE 18 /* Different exception subcode */

-#define EXCCODE_VFPE 18

-#define EXCCODE_WPEF 19 /* Different exception subcode */

-#define EXCCODE_WPEM 19

-#define EXCCODE_BTD 20

-#define EXCCODE_BTE 21

-#define EXCCODE_DBP 26 /* Reserved subcode used for debug */

+#define EXCODE(code, subcode) ( ((subcode) << 6) | (code) )

+#define EXCODE_MCODE(code) ( (code) & 0x3f )

+#define EXCODE_SUBCODE(code) ( (code) >> 6 )

+

+#define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */

+#define EXCCODE_INT EXCODE(0, 0)

+#define EXCCODE_PIL EXCODE(1, 0)

+#define EXCCODE_PIS EXCODE(2, 0)

+#define EXCCODE_PIF EXCODE(3, 0)

+#define EXCCODE_PME EXCODE(4, 0)

+#define EXCCODE_PNR EXCODE(5, 0)

+#define EXCCODE_PNX EXCODE(6, 0)

+#define EXCCODE_PPI EXCODE(7, 0)

+#define EXCCODE_ADEF EXCODE(8, 0) /* Different exception subcode */

+#define EXCCODE_ADEM EXCODE(8, 1)

+#define EXCCODE_ALE EXCODE(9, 0)

+#define EXCCODE_BCE EXCODE(10, 0)

+#define EXCCODE_SYS EXCODE(11, 0)

+#define EXCCODE_BRK EXCODE(12, 0)

+#define EXCCODE_INE EXCODE(13, 0)

+#define EXCCODE_IPE EXCODE(14, 0)

+#define EXCCODE_FPD EXCODE(15, 0)

+#define EXCCODE_SXD EXCODE(16, 0)

+#define EXCCODE_ASXD EXCODE(17, 0)

+#define EXCCODE_FPE EXCODE(18, 0) /* Different exception subcode */

+#define EXCCODE_VFPE EXCODE(18, 1)

+#define EXCCODE_WPEF EXCODE(19, 0) /* Different exception subcode */

+#define EXCCODE_WPEM EXCODE(19, 1)

+#define EXCCODE_BTD EXCODE(20, 0)

+#define EXCCODE_BTE EXCODE(21, 0)

+#define EXCCODE_DBP EXCODE(26, 0) /* Reserved subcode used for debug */

/* cpucfg[0] bits */

FIELD(CPUCFG0, PRID, 0, 32)

2.31.1

When the address is invalid address, We should set exception_index

according to MMUAccessType, and EXCCODE_ADEF need't update badinstr.

Otherwise, The system enters an infinite loop. e.g:

run test.c on system mode

test.c:

#include<stdio.h>

void (*func)(int *);

int main()

{

int i = 8;

void *ptr = (void *)0x4000000000000000;

func = ptr;

func(&i);

return 0;

}

Signed-off-by: Song Gao <gaosong@loongson.cn>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-ID: <20221101073210.3934280-2-gaosong@loongson.cn>

target/loongarch/cpu.c | 1 +

target/loongarch/tlb_helper.c | 5 +++--

2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c

--- a/target/loongarch/cpu.c

+++ b/target/loongarch/cpu.c

@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)

}

QEMU_FALLTHROUGH;

case EXCCODE_PIF:

+ case EXCCODE_ADEF:

cause = cs->exception_index;

update_badinstr = 0;

break;

diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c

--- a/target/loongarch/tlb_helper.c

+++ b/target/loongarch/tlb_helper.c

@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,

switch (tlb_error) {

default:

case TLBRET_BADADDR:

- cs->exception_index = EXCCODE_ADEM;

+ cs->exception_index = access_type == MMU_INST_FETCH

+ ? EXCCODE_ADEF : EXCCODE_ADEM;

break;

case TLBRET_NOMATCH:

/* No TLB match for a mapped address */

@@ -XXX,XX +XXX,XX @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,

CPULoongArchState *env = &cpu->env;

hwaddr physical;

int prot;

- int ret = TLBRET_BADADDR;

+ int ret;

/* Data access */

ret = get_physical_address(env, &physical, &prot, address,

2.31.1

From: Rui Wang <wangrui@loongson.cn>

Suggested-by: Richard Henderson <richard.henderson@linaro.org>

target/loongarch/cpu.h | 9 ++++++++-

target/loongarch/insn_trans/trans_privileged.c.inc | 2 +-

target/loongarch/translate.c | 6 +++++-

3 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h

--- a/target/loongarch/cpu.h

+++ b/target/loongarch/cpu.h

@@ -XXX,XX +XXX,XX @@

#include "qemu/timer.h"

#include "exec/memory.h"

#include "hw/sysbus.h"

+#include "cpu-csr.h"

#define IOCSRF_TEMP 0

#define IOCSRF_NODECNT 1

@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)

#endif

+/*

+ * LoongArch CPUs hardware flags.

+ */

+#define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */

+#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */

+

static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,

target_ulong *pc,

target_ulong *cs_base,

@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,

*pc = env->pc;

*cs_base = 0;

- *flags = cpu_mmu_index(env, false);

+ *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);

void loongarch_cpu_list(void);

diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/target/loongarch/insn_trans/trans_privileged.c.inc

+++ b/target/loongarch/insn_trans/trans_privileged.c.inc

@@ -XXX,XX +XXX,XX @@ static const CSRInfo csr_info[] = {

static bool check_plv(DisasContext *ctx)

- if (ctx->base.tb->flags == MMU_USER_IDX) {

+ if (ctx->mem_idx == MMU_USER_IDX) {

generate_exception(ctx, EXCCODE_IPE);

return true;

}

diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/loongarch/translate.c

+++ b/target/loongarch/translate.c

@@ -XXX,XX +XXX,XX @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,

DisasContext *ctx = container_of(dcbase, DisasContext, base);

ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;

- ctx->mem_idx = ctx->base.tb->flags;

+ if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) {

+ ctx->mem_idx = ctx->base.tb->flags & HW_FLAGS_PLV_MASK;

+ } else {

+ ctx->mem_idx = MMU_DA_IDX;

/* Bound the number of insns to execute to those left on the page. */

bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;

2.31.1

From: Rui Wang <wangrui@loongson.cn>

We need to emulate it to generate a floating point disable exception

when CSR.EUEN.FPE is zero.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

target/loongarch/cpu.c | 2 ++

target/loongarch/cpu.h | 2 ++

.../loongarch/insn_trans/trans_farith.c.inc | 30 ++++++++++++++++

target/loongarch/insn_trans/trans_fcmp.c.inc | 11 ++++--

.../loongarch/insn_trans/trans_fmemory.c.inc | 34 +++++++++++++++----

target/loongarch/insn_trans/trans_fmov.c.inc | 29 ++++++++++++++--

6 files changed, 97 insertions(+), 11 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/loongarch/cpu.c

+++ b/target/loongarch/cpu.c

@@ -XXX,XX +XXX,XX @@ static const char * const excp_names[] = {

[EXCCODE_BRK] = "Break",

[EXCCODE_INE] = "Instruction Non-Existent",

[EXCCODE_IPE] = "Instruction privilege error",

+ [EXCCODE_FPD] = "Floating Point Disabled",

[EXCCODE_FPE] = "Floating Point Exception",

[EXCCODE_DBP] = "Debug breakpoint",

[EXCCODE_BCE] = "Bound Check Exception",

@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)

case EXCCODE_BRK:

case EXCCODE_INE:

case EXCCODE_IPE:

+ case EXCCODE_FPD:

case EXCCODE_FPE:

case EXCCODE_BCE:

env->CSR_BADV = env->pc;

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/loongarch/cpu.h

+++ b/target/loongarch/cpu.h

@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)

*/

#define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */

#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */

+#define HW_FLAGS_EUEN_FPE 0x04

static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,

target_ulong *pc,

@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,

*pc = env->pc;

*cs_base = 0;

*flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);

+ *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;

}

void loongarch_cpu_list(void);

diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loongarch/insn_trans/trans_farith.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/target/loongarch/insn_trans/trans_farith.c.inc

+++ b/target/loongarch/insn_trans/trans_farith.c.inc

+#ifndef CONFIG_USER_ONLY

+#define CHECK_FPE do { \

+ if ((ctx->base.tb->flags & HW_FLAGS_EUEN_FPE) == 0) { \