[PULL 00/18] loongarch-to-apply queue
[PULL v2 0/9] loongarch-to-apply queue
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The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
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The following changes since commit d29201ff34a135cdfc197f4413c1c5047e4f58bb:
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Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
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Merge tag 'pull-hmp-20220915a' of https://gitlab.com/dagrh/qemu into staging (2022-09-17 10:31:11 -0400)
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are available in the Git repository at:
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are available in the Git repository at:
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https://gitlab.com/bibo-mao/qemu.git pull-loongarch-20241213
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https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20220920
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for you to fetch changes up to 78aa256571aa06f32001bd80635a1858187c609b:
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for you to fetch changes up to 1895b967922890f76ad0ba8eefad6019e0328606:
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hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic (2024-12-13 14:39:39 +0800)
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hw/loongarch: Improve acpi dsdt table (2022-09-20 15:44:25 +0800)
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----------------------------------------------------------------
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----------------------------------------------------------------
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pull-loongarch-20241213
14
v2: fix compile error.
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----------------------------------------------------------------
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----------------------------------------------------------------
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Bibo Mao (8):
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Xiaojuan Yang (9):
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include: Add loongarch_pic_common header file
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hw/loongarch: Remove vga device when loongarch init
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include: Move struct LoongArchPCHPIC to loongarch_pic_common header file
19
hw/loongarch: Support fw_cfg dma function
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hw/intc/loongarch_pch: Merge instance_init() into realize()
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hw/loongarch: Add interrupt information to FDT table
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hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonState
21
hw/loongarch: Add platform bus support
22
hw/intc/loongarch_pch: Move some functions to file loongarch_pic_common
22
hw/loongarch: Add hotplug handler for machine
23
hw/intc/loongarch_pch: Inherit from loongarch_pic_common
23
hw/loongarch: Add RAMFB to dynamic_sysbus_devices list
24
hw/intc/loongarch_pch: Add pre_save and post_load interfaces
24
hw/loongarch: Fix acpi ged irq number in dsdt table
25
hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic
25
hw/loongarch: Support memory hotplug
26
hw/loongarch: Improve acpi dsdt table
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27
27
hw/intc/loongarch_pch_pic.c | 106 +++++++++++----------------------
28
hw/loongarch/Kconfig | 5 +-
28
hw/intc/loongarch_pic_common.c | 97 ++++++++++++++++++++++++++++++
29
hw/loongarch/acpi-build.c | 191 ++++++++++-------------------------------
29
hw/intc/meson.build | 2 +-
30
hw/loongarch/fw_cfg.c | 3 +-
30
hw/loongarch/virt.c | 2 +-
31
hw/loongarch/virt.c | 204 +++++++++++++++++++++++++++++++++++++++++++-
31
include/hw/intc/loongarch_pch_pic.h | 70 +++++-----------------
32
include/hw/loongarch/virt.h | 2 +
32
include/hw/intc/loongarch_pic_common.h | 82 +++++++++++++++++++++++++
33
include/hw/pci-host/ls7a.h | 5 ++
33
6 files changed, 230 insertions(+), 129 deletions(-)
34
6 files changed, 258 insertions(+), 152 deletions(-)
34
create mode 100644 hw/intc/loongarch_pic_common.c
35
create mode 100644 include/hw/intc/loongarch_pic_common.h
diff view generated by jsdifflib
[PULL 01/18] include: Add loongarch_pic_common header file
Deleted patch
1
Add common header file hw/intc/loongarch_pic_common.h, and move
2
some macro definition from hw/intc/loongarch_pch_pic.h to the common
3
header file.
4
1
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
include/hw/intc/loongarch_pch_pic.h | 36 +++-------------------
9
include/hw/intc/loongarch_pic_common.h | 42 ++++++++++++++++++++++++++
10
2 files changed, 47 insertions(+), 31 deletions(-)
11
create mode 100644 include/hw/intc/loongarch_pic_common.h
12
13
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/intc/loongarch_pch_pic.h
16
+++ b/include/hw/intc/loongarch_pch_pic.h
17
@@ -XXX,XX +XXX,XX @@
18
* Copyright (c) 2021 Loongson Technology Corporation Limited
19
*/
20
21
-#include "hw/sysbus.h"
22
+#ifndef HW_LOONGARCH_PCH_PIC_H
23
+#define HW_LOONGARCH_PCH_PIC_H
24
+
25
+#include "hw/intc/loongarch_pic_common.h"
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27
#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
28
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
29
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
30
31
-#define PCH_PIC_INT_ID_VAL 0x7000000UL
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-#define PCH_PIC_INT_ID_VER 0x1UL
33
-
34
-#define PCH_PIC_INT_ID_LO 0x00
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-#define PCH_PIC_INT_ID_HI 0x04
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-#define PCH_PIC_INT_MASK_LO 0x20
37
-#define PCH_PIC_INT_MASK_HI 0x24
38
-#define PCH_PIC_HTMSI_EN_LO 0x40
39
-#define PCH_PIC_HTMSI_EN_HI 0x44
40
-#define PCH_PIC_INT_EDGE_LO 0x60
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-#define PCH_PIC_INT_EDGE_HI 0x64
42
-#define PCH_PIC_INT_CLEAR_LO 0x80
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-#define PCH_PIC_INT_CLEAR_HI 0x84
44
-#define PCH_PIC_AUTO_CTRL0_LO 0xc0
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-#define PCH_PIC_AUTO_CTRL0_HI 0xc4
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-#define PCH_PIC_AUTO_CTRL1_LO 0xe0
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-#define PCH_PIC_AUTO_CTRL1_HI 0xe4
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-#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100
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-#define PCH_PIC_ROUTE_ENTRY_END 0x13f
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-#define PCH_PIC_HTMSI_VEC_OFFSET 0x200
51
-#define PCH_PIC_HTMSI_VEC_END 0x23f
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-#define PCH_PIC_INT_STATUS_LO 0x3a0
53
-#define PCH_PIC_INT_STATUS_HI 0x3a4
54
-#define PCH_PIC_INT_POL_LO 0x3e0
55
-#define PCH_PIC_INT_POL_HI 0x3e4
56
-
57
-#define STATUS_LO_START 0
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-#define STATUS_HI_START 0x4
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-#define POL_LO_START 0x40
60
-#define POL_HI_START 0x44
61
struct LoongArchPCHPIC {
62
SysBusDevice parent_obj;
63
qemu_irq parent_irq[64];
64
@@ -XXX,XX +XXX,XX @@ struct LoongArchPCHPIC {
65
MemoryRegion iomem8;
66
unsigned int irq_num;
67
};
68
+#endif /* HW_LOONGARCH_PCH_PIC_H */
69
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
70
new file mode 100644
71
index XXXXXXX..XXXXXXX
72
--- /dev/null
73
+++ b/include/hw/intc/loongarch_pic_common.h
74
@@ -XXX,XX +XXX,XX @@
75
+/* SPDX-License-Identifier: GPL-2.0-or-later */
76
+/*
77
+ * LoongArch 7A1000 I/O interrupt controller definitions
78
+ * Copyright (c) 2024 Loongson Technology Corporation Limited
79
+ */
80
+
81
+#ifndef HW_LOONGARCH_PIC_COMMON_H
82
+#define HW_LOONGARCH_PIC_COMMON_H
83
+
84
+#include "hw/pci-host/ls7a.h"
85
+#include "hw/sysbus.h"
86
+
87
+#define PCH_PIC_INT_ID_VAL 0x7000000UL
88
+#define PCH_PIC_INT_ID_VER 0x1UL
89
+#define PCH_PIC_INT_ID_LO 0x00
90
+#define PCH_PIC_INT_ID_HI 0x04
91
+#define PCH_PIC_INT_MASK_LO 0x20
92
+#define PCH_PIC_INT_MASK_HI 0x24
93
+#define PCH_PIC_HTMSI_EN_LO 0x40
94
+#define PCH_PIC_HTMSI_EN_HI 0x44
95
+#define PCH_PIC_INT_EDGE_LO 0x60
96
+#define PCH_PIC_INT_EDGE_HI 0x64
97
+#define PCH_PIC_INT_CLEAR_LO 0x80
98
+#define PCH_PIC_INT_CLEAR_HI 0x84
99
+#define PCH_PIC_AUTO_CTRL0_LO 0xc0
100
+#define PCH_PIC_AUTO_CTRL0_HI 0xc4
101
+#define PCH_PIC_AUTO_CTRL1_LO 0xe0
102
+#define PCH_PIC_AUTO_CTRL1_HI 0xe4
103
+#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100
104
+#define PCH_PIC_ROUTE_ENTRY_END 0x13f
105
+#define PCH_PIC_HTMSI_VEC_OFFSET 0x200
106
+#define PCH_PIC_HTMSI_VEC_END 0x23f
107
+#define PCH_PIC_INT_STATUS_LO 0x3a0
108
+#define PCH_PIC_INT_STATUS_HI 0x3a4
109
+#define PCH_PIC_INT_POL_LO 0x3e0
110
+#define PCH_PIC_INT_POL_HI 0x3e4
111
+
112
+#define STATUS_LO_START 0
113
+#define STATUS_HI_START 0x4
114
+#define POL_LO_START 0x40
115
+#define POL_HI_START 0x44
116
+#endif /* HW_LOONGARCH_PIC_COMMON_H */
117
--
118
2.43.5
diff view generated by jsdifflib
[PULL 02/18] include: Move struct LoongArchPCHPIC to loongarch_pic_common header file
Deleted patch
1
Move structure LoongArchPCHPIC from header file loongarch_pch_pic.h
2
to file loongarch_pic_common.h, and rename structure name with
3
LoongArchPICCommonState.
4
1
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
include/hw/intc/loongarch_pch_pic.h | 27 +------------------------
9
include/hw/intc/loongarch_pic_common.h | 28 ++++++++++++++++++++++++++
10
2 files changed, 29 insertions(+), 26 deletions(-)
11
12
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/include/hw/intc/loongarch_pch_pic.h
15
+++ b/include/hw/intc/loongarch_pch_pic.h
16
@@ -XXX,XX +XXX,XX @@
17
18
#include "hw/intc/loongarch_pic_common.h"
19
20
+#define LoongArchPCHPIC LoongArchPICCommonState
21
#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
22
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
23
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
24
25
-struct LoongArchPCHPIC {
26
- SysBusDevice parent_obj;
27
- qemu_irq parent_irq[64];
28
- uint64_t int_mask; /*0x020 interrupt mask register*/
29
- uint64_t htmsi_en; /*0x040 1=msi*/
30
- uint64_t intedge; /*0x060 edge=1 level =0*/
31
- uint64_t intclr; /*0x080 for clean edge int,set 1 clean,set 0 is noused*/
32
- uint64_t auto_crtl0; /*0x0c0*/
33
- uint64_t auto_crtl1; /*0x0e0*/
34
- uint64_t last_intirr; /* edge detection */
35
- uint64_t intirr; /* 0x380 interrupt request register */
36
- uint64_t intisr; /* 0x3a0 interrupt service register */
37
- /*
38
- * 0x3e0 interrupt level polarity selection
39
- * register 0 for high level trigger
40
- */
41
- uint64_t int_polarity;
42
-
43
- uint8_t route_entry[64]; /*0x100 - 0x138*/
44
- uint8_t htmsi_vector[64]; /*0x200 - 0x238*/
45
-
46
- MemoryRegion iomem32_low;
47
- MemoryRegion iomem32_high;
48
- MemoryRegion iomem8;
49
- unsigned int irq_num;
50
-};
51
#endif /* HW_LOONGARCH_PCH_PIC_H */
52
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
53
index XXXXXXX..XXXXXXX 100644
54
--- a/include/hw/intc/loongarch_pic_common.h
55
+++ b/include/hw/intc/loongarch_pic_common.h
56
@@ -XXX,XX +XXX,XX @@
57
#define STATUS_HI_START 0x4
58
#define POL_LO_START 0x40
59
#define POL_HI_START 0x44
60
+
61
+struct LoongArchPICCommonState {
62
+ SysBusDevice parent_obj;
63
+
64
+ qemu_irq parent_irq[64];
65
+ uint64_t int_mask; /* 0x020 interrupt mask register */
66
+ uint64_t htmsi_en; /* 0x040 1=msi */
67
+ uint64_t intedge; /* 0x060 edge=1 level=0 */
68
+ uint64_t intclr; /* 0x080 clean edge int, set 1 clean, 0 noused */
69
+ uint64_t auto_crtl0; /* 0x0c0 */
70
+ uint64_t auto_crtl1; /* 0x0e0 */
71
+ uint64_t last_intirr; /* edge detection */
72
+ uint64_t intirr; /* 0x380 interrupt request register */
73
+ uint64_t intisr; /* 0x3a0 interrupt service register */
74
+ /*
75
+ * 0x3e0 interrupt level polarity selection
76
+ * register 0 for high level trigger
77
+ */
78
+ uint64_t int_polarity;
79
+
80
+ uint8_t route_entry[64]; /* 0x100 - 0x138 */
81
+ uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */
82
+
83
+ MemoryRegion iomem32_low;
84
+ MemoryRegion iomem32_high;
85
+ MemoryRegion iomem8;
86
+ unsigned int irq_num;
87
+};
88
#endif /* HW_LOONGARCH_PIC_COMMON_H */
89
--
90
2.43.5
diff view generated by jsdifflib
[PULL 11/18] include: Rename LoongArchExtIOI with LoongArchExtIOICommonState
[PULL v2 1/9] hw/loongarch: Remove vga device when loongarch init
1
Rename structure LoongArchExtIOI with LoongArchExtIOICommonState,
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
since it is defined in file loongarch_extioi_common.h
3
2
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
3
Remove the vga device when loongarch machine init and
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
4
we will support other display device in the future.
5
6
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
7
Acked-by: Song Gao <gaosong@loongson.cn>
8
Message-Id: <20220908094623.73051-2-yangxiaojuan@loongson.cn>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
6
---
10
---
7
include/hw/intc/loongarch_extioi.h | 1 +
11
hw/loongarch/Kconfig | 1 -
8
include/hw/intc/loongarch_extioi_common.h | 2 +-
12
hw/loongarch/virt.c | 3 ---
9
2 files changed, 2 insertions(+), 1 deletion(-)
13
2 files changed, 4 deletions(-)
10
14
11
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
15
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/intc/loongarch_extioi.h
17
--- a/hw/loongarch/Kconfig
14
+++ b/include/hw/intc/loongarch_extioi.h
18
+++ b/hw/loongarch/Kconfig
15
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ config LOONGARCH_VIRT
16
20
bool
17
#include "hw/intc/loongarch_extioi_common.h"
21
select PCI
18
22
select PCI_EXPRESS_GENERIC_BRIDGE
19
+#define LoongArchExtIOI LoongArchExtIOICommonState
23
- imply VGA_PCI
20
#define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
24
imply VIRTIO_VGA
21
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
25
imply PCI_DEVICES
22
#endif /* LOONGARCH_EXTIOI_H */
26
select ISA_BUS
23
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
27
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
24
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/intc/loongarch_extioi_common.h
29
--- a/hw/loongarch/virt.c
26
+++ b/include/hw/intc/loongarch_extioi_common.h
30
+++ b/hw/loongarch/virt.c
27
@@ -XXX,XX +XXX,XX @@ typedef struct ExtIOICore {
31
@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
28
qemu_irq parent_irq[LS3A_INTC_IP];
32
pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
29
} ExtIOICore;
33
}
30
34
31
-struct LoongArchExtIOI {
35
- /* VGA setup */
32
+struct LoongArchExtIOICommonState {
36
- pci_vga_init(pci_bus);
33
SysBusDevice parent_obj;
37
-
34
uint32_t num_cpu;
38
/*
35
uint32_t features;
39
* There are some invalid guest memory access.
40
* Create some unimplemented devices to emulate this.
36
--
41
--
37
2.43.5
42
2.31.1
diff view generated by jsdifflib
[PULL 10/18] include: Move struct LoongArchExtIOI to header file loongarch_extioi_common
[PULL v2 2/9] hw/loongarch: Support fw_cfg dma function
1
Move definiton of structure LoongArchExtIOI from header file loongarch_extioi.h
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
to file loongarch_extioi_common.h.
3
2
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
3
Support fw_cfg dma function for LoongArch virt machine.
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
4
5
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
6
Acked-by: Song Gao <gaosong@loongson.cn>
7
Message-Id: <20220908094623.73051-3-yangxiaojuan@loongson.cn>
8
Signed-off-by: Song Gao <gaosong@loongson.cn>
6
---
9
---
7
include/hw/intc/loongarch_extioi.h | 26 ----------------------
10
hw/loongarch/Kconfig | 1 +
8
include/hw/intc/loongarch_extioi_common.h | 27 +++++++++++++++++++++++
11
hw/loongarch/fw_cfg.c | 3 ++-
9
2 files changed, 27 insertions(+), 26 deletions(-)
12
hw/loongarch/virt.c | 2 +-
13
3 files changed, 4 insertions(+), 2 deletions(-)
10
14
11
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
15
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/intc/loongarch_extioi.h
17
--- a/hw/loongarch/Kconfig
14
+++ b/include/hw/intc/loongarch_extioi.h
18
+++ b/hw/loongarch/Kconfig
15
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ config LOONGARCH_VIRT
16
20
select SMBIOS
17
#include "hw/intc/loongarch_extioi_common.h"
21
select ACPI_PCI
18
22
select ACPI_HW_REDUCED
19
-typedef struct ExtIOICore {
23
+ select FW_CFG_DMA
20
- uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
24
diff --git a/hw/loongarch/fw_cfg.c b/hw/loongarch/fw_cfg.c
21
- DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
22
- qemu_irq parent_irq[LS3A_INTC_IP];
23
-} ExtIOICore;
24
-
25
#define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
26
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
27
-struct LoongArchExtIOI {
28
- SysBusDevice parent_obj;
29
- uint32_t num_cpu;
30
- uint32_t features;
31
- uint32_t status;
32
- /* hardware state */
33
- uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
34
- uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
35
- uint32_t isr[EXTIOI_IRQS / 32];
36
- uint32_t enable[EXTIOI_IRQS / 32];
37
- uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
38
- uint32_t coremap[EXTIOI_IRQS / 4];
39
- uint32_t sw_pending[EXTIOI_IRQS / 32];
40
- uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
41
- uint8_t sw_coremap[EXTIOI_IRQS];
42
- qemu_irq irq[EXTIOI_IRQS];
43
- ExtIOICore *cpu;
44
- MemoryRegion extioi_system_mem;
45
- MemoryRegion virt_extend;
46
-};
47
#endif /* LOONGARCH_EXTIOI_H */
48
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
49
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/intc/loongarch_extioi_common.h
26
--- a/hw/loongarch/fw_cfg.c
51
+++ b/include/hw/intc/loongarch_extioi_common.h
27
+++ b/hw/loongarch/fw_cfg.c
52
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@ FWCfgState *loongarch_fw_cfg_init(ram_addr_t ram_size, MachineState *ms)
53
#define EXTIOI_ENABLE_CPU_ENCODE (3)
29
int max_cpus = ms->smp.max_cpus;
54
#define EXTIOI_VIRT_COREMAP_START (0x40)
30
int smp_cpus = ms->smp.cpus;
55
#define EXTIOI_VIRT_COREMAP_END (0x240)
31
56
+
32
- fw_cfg = fw_cfg_init_mem_wide(VIRT_FWCFG_BASE + 8, VIRT_FWCFG_BASE, 8, 0, NULL);
57
+typedef struct ExtIOICore {
33
+ fw_cfg = fw_cfg_init_mem_wide(VIRT_FWCFG_BASE + 8, VIRT_FWCFG_BASE, 8,
58
+ uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
34
+ VIRT_FWCFG_BASE + 16, &address_space_memory);
59
+ DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
35
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
60
+ qemu_irq parent_irq[LS3A_INTC_IP];
36
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
61
+} ExtIOICore;
37
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
62
+
38
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
63
+struct LoongArchExtIOI {
39
index XXXXXXX..XXXXXXX 100644
64
+ SysBusDevice parent_obj;
40
--- a/hw/loongarch/virt.c
65
+ uint32_t num_cpu;
41
+++ b/hw/loongarch/virt.c
66
+ uint32_t features;
42
@@ -XXX,XX +XXX,XX @@ static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams)
67
+ uint32_t status;
43
qemu_fdt_setprop_string(ms->fdt, nodename,
68
+ /* hardware state */
44
"compatible", "qemu,fw-cfg-mmio");
69
+ uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
45
qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
70
+ uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
46
- 2, base, 2, 0x8);
71
+ uint32_t isr[EXTIOI_IRQS / 32];
47
+ 2, base, 2, 0x18);
72
+ uint32_t enable[EXTIOI_IRQS / 32];
48
qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
73
+ uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
49
g_free(nodename);
74
+ uint32_t coremap[EXTIOI_IRQS / 4];
50
}
75
+ uint32_t sw_pending[EXTIOI_IRQS / 32];
76
+ uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
77
+ uint8_t sw_coremap[EXTIOI_IRQS];
78
+ qemu_irq irq[EXTIOI_IRQS];
79
+ ExtIOICore *cpu;
80
+ MemoryRegion extioi_system_mem;
81
+ MemoryRegion virt_extend;
82
+};
83
#endif /* LOONGARCH_EXTIOI_H */
84
--
51
--
85
2.43.5
52
2.31.1
diff view generated by jsdifflib
[PULL 09/18] include: Add loongarch_extioi_common header file
[PULL v2 3/9] hw/loongarch: Add interrupt information to FDT table
1
Add common header file include/hw/intc/loongarch_extioi_common.h, and
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
move some macro definition from include/hw/intc/loongarch_extioi.h to
3
the common header file.
4
2
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
3
Add interrupt information to FDT table, such as interrupt
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
4
controller info, compatiable info, etc.
5
6
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
7
Acked-by: Song Gao <gaosong@loongson.cn>
8
Message-Id: <20220908094623.73051-4-yangxiaojuan@loongson.cn>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
7
---
10
---
8
include/hw/intc/loongarch_extioi.h | 50 +------------------
11
hw/loongarch/virt.c | 28 ++++++++++++++++++++++++++++
9
include/hw/intc/loongarch_extioi_common.h | 58 +++++++++++++++++++++++
12
1 file changed, 28 insertions(+)
10
2 files changed, 59 insertions(+), 49 deletions(-)
11
create mode 100644 include/hw/intc/loongarch_extioi_common.h
12
13
13
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
14
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/intc/loongarch_extioi.h
16
--- a/hw/loongarch/virt.c
16
+++ b/include/hw/intc/loongarch_extioi.h
17
+++ b/hw/loongarch/virt.c
17
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pcie_node(const LoongArchMachineState *lams)
18
* Copyright (C) 2021 Loongson Technology Corporation Limited
19
qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size);
19
*/
20
}
20
21
21
-#include "hw/sysbus.h"
22
+static void fdt_add_irqchip_node(LoongArchMachineState *lams)
22
-#include "hw/loongarch/virt.h"
23
+{
23
-
24
+ MachineState *ms = MACHINE(lams);
24
#ifndef LOONGARCH_EXTIOI_H
25
+ char *nodename;
25
#define LOONGARCH_EXTIOI_H
26
+ uint32_t irqchip_phandle;
26
27
-#define LS3A_INTC_IP 8
28
-#define EXTIOI_IRQS (256)
29
-#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
30
-/* irq from EXTIOI is routed to no more than 4 cpus */
31
-#define EXTIOI_CPUS (4)
32
-/* map to ipnum per 32 irqs */
33
-#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
34
-#define EXTIOI_IRQS_COREMAP_SIZE 256
35
-#define EXTIOI_IRQS_NODETYPE_COUNT 16
36
-#define EXTIOI_IRQS_GROUP_COUNT 8
37
-
38
-#define APIC_OFFSET 0x400
39
-#define APIC_BASE (0x1000ULL + APIC_OFFSET)
40
-
41
-#define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
42
-#define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
43
-#define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
44
-#define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
45
-#define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
46
-#define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
47
-#define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
48
-#define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
49
-#define EXTIOI_ISR_START (0x700 - APIC_OFFSET)
50
-#define EXTIOI_ISR_END (0x720 - APIC_OFFSET)
51
-#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET)
52
-#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
53
-#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
54
-#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
55
-#define EXTIOI_SIZE 0x800
56
-
57
-#define EXTIOI_VIRT_BASE (0x40000000)
58
-#define EXTIOI_VIRT_SIZE (0x1000)
59
-#define EXTIOI_VIRT_FEATURES (0x0)
60
-#define EXTIOI_HAS_VIRT_EXTENSION (0)
61
-#define EXTIOI_HAS_ENABLE_OPTION (1)
62
-#define EXTIOI_HAS_INT_ENCODE (2)
63
-#define EXTIOI_HAS_CPU_ENCODE (3)
64
-#define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \
65
- | BIT(EXTIOI_HAS_ENABLE_OPTION) \
66
- | BIT(EXTIOI_HAS_CPU_ENCODE))
67
-#define EXTIOI_VIRT_CONFIG (0x4)
68
-#define EXTIOI_ENABLE (1)
69
-#define EXTIOI_ENABLE_INT_ENCODE (2)
70
-#define EXTIOI_ENABLE_CPU_ENCODE (3)
71
-#define EXTIOI_VIRT_COREMAP_START (0x40)
72
-#define EXTIOI_VIRT_COREMAP_END (0x240)
73
+#include "hw/intc/loongarch_extioi_common.h"
74
75
typedef struct ExtIOICore {
76
uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
77
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
78
new file mode 100644
79
index XXXXXXX..XXXXXXX
80
--- /dev/null
81
+++ b/include/hw/intc/loongarch_extioi_common.h
82
@@ -XXX,XX +XXX,XX @@
83
+/* SPDX-License-Identifier: GPL-2.0-or-later */
84
+/*
85
+ * LoongArch 3A5000 ext interrupt controller definitions
86
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
87
+ */
88
+
27
+
89
+#ifndef LOONGARCH_EXTIOI_COMMON_H
28
+ irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt);
90
+#define LOONGARCH_EXTIOI_COMMON_H
29
+ qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle);
91
+
30
+
92
+#include "hw/sysbus.h"
31
+ nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE);
93
+#include "hw/loongarch/virt.h"
32
+ qemu_fdt_add_subnode(ms->fdt, nodename);
33
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
34
+ qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
35
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
36
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
37
+ qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
94
+
38
+
95
+#define LS3A_INTC_IP 8
39
+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
96
+#define EXTIOI_IRQS (256)
40
+ "loongarch,ls7a");
97
+#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
98
+/* irq from EXTIOI is routed to no more than 4 cpus */
99
+#define EXTIOI_CPUS (4)
100
+/* map to ipnum per 32 irqs */
101
+#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
102
+#define EXTIOI_IRQS_COREMAP_SIZE 256
103
+#define EXTIOI_IRQS_NODETYPE_COUNT 16
104
+#define EXTIOI_IRQS_GROUP_COUNT 8
105
+
41
+
106
+#define APIC_OFFSET 0x400
42
+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
107
+#define APIC_BASE (0x1000ULL + APIC_OFFSET)
43
+ 2, VIRT_IOAPIC_REG_BASE,
108
+#define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
44
+ 2, PCH_PIC_ROUTE_ENTRY_OFFSET);
109
+#define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
110
+#define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
111
+#define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
112
+#define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
113
+#define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
114
+#define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
115
+#define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
116
+#define EXTIOI_ISR_START (0x700 - APIC_OFFSET)
117
+#define EXTIOI_ISR_END (0x720 - APIC_OFFSET)
118
+#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET)
119
+#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
120
+#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
121
+#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
122
+#define EXTIOI_SIZE 0x800
123
+
45
+
124
+#define EXTIOI_VIRT_BASE (0x40000000)
46
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle);
125
+#define EXTIOI_VIRT_SIZE (0x1000)
47
+ g_free(nodename);
126
+#define EXTIOI_VIRT_FEATURES (0x0)
48
+}
127
+#define EXTIOI_HAS_VIRT_EXTENSION (0)
49
128
+#define EXTIOI_HAS_ENABLE_OPTION (1)
50
#define PM_BASE 0x10080000
129
+#define EXTIOI_HAS_INT_ENCODE (2)
51
#define PM_SIZE 0x100
130
+#define EXTIOI_HAS_CPU_ENCODE (3)
52
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
131
+#define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \
53
}
132
+ | BIT(EXTIOI_HAS_ENABLE_OPTION) \
54
/* Initialize the IO interrupt subsystem */
133
+ | BIT(EXTIOI_HAS_CPU_ENCODE))
55
loongarch_irq_init(lams);
134
+#define EXTIOI_VIRT_CONFIG (0x4)
56
+ fdt_add_irqchip_node(lams);
135
+#define EXTIOI_ENABLE (1)
57
lams->machine_done.notify = virt_machine_done;
136
+#define EXTIOI_ENABLE_INT_ENCODE (2)
58
qemu_add_machine_init_done_notifier(&lams->machine_done);
137
+#define EXTIOI_ENABLE_CPU_ENCODE (3)
59
fdt_add_pcie_node(lams);
138
+#define EXTIOI_VIRT_COREMAP_START (0x40)
139
+#define EXTIOI_VIRT_COREMAP_END (0x240)
140
+#endif /* LOONGARCH_EXTIOI_H */
141
--
60
--
142
2.43.5
61
2.31.1
diff view generated by jsdifflib
[PULL 04/18] hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonState
[PULL v2 4/9] hw/loongarch: Add platform bus support
1
With pic vmstate, rename structure name vmstate_loongarch_pch_pic with
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
vmstate_loongarch_pic_common, and with pic property rename
3
loongarch_pch_pic_properties with loongarch_pic_common_properties.
4
2
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
3
Add platform bus support and add the bus information such as address,
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
4
size, irq number to FDT table.
5
6
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
7
Acked-by: Song Gao <gaosong@loongson.cn>
8
Message-Id: <20220908094623.73051-5-yangxiaojuan@loongson.cn>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
7
---
10
---
8
hw/intc/loongarch_pch_pic.c | 52 +++++++++++++++++++++++--------------
11
hw/loongarch/Kconfig | 1 +
9
1 file changed, 32 insertions(+), 20 deletions(-)
12
hw/loongarch/virt.c | 33 +++++++++++++++++++++++++++++++++
13
include/hw/loongarch/virt.h | 1 +
14
include/hw/pci-host/ls7a.h | 5 +++++
15
4 files changed, 40 insertions(+)
10
16
11
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
17
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/loongarch_pch_pic.c
19
--- a/hw/loongarch/Kconfig
14
+++ b/hw/intc/loongarch_pch_pic.c
20
+++ b/hw/loongarch/Kconfig
15
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
21
@@ -XXX,XX +XXX,XX @@ config LOONGARCH_VIRT
16
s->int_polarity = 0x0;
22
select SERIAL
23
select SERIAL_ISA
24
select VIRTIO_PCI
25
+ select PLATFORM_BUS
26
select LOONGARCH_IPI
27
select LOONGARCH_PCH_PIC
28
select LOONGARCH_PCH_MSI
29
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/loongarch/virt.c
32
+++ b/hw/loongarch/virt.c
33
@@ -XXX,XX +XXX,XX @@
34
#include "hw/mem/nvdimm.h"
35
#include "sysemu/device_tree.h"
36
#include <libfdt.h>
37
+#include "hw/core/sysbus-fdt.h"
38
+#include "hw/platform-bus.h"
39
40
static void create_fdt(LoongArchMachineState *lams)
41
{
42
@@ -XXX,XX +XXX,XX @@ static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState
43
return dev;
17
}
44
}
18
45
19
+static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
46
+static DeviceState *create_platform_bus(DeviceState *pch_pic)
20
+{
47
+{
21
+ LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
48
+ DeviceState *dev;
49
+ SysBusDevice *sysbus;
50
+ int i, irq;
51
+ MemoryRegion *sysmem = get_system_memory();
22
+
52
+
23
+ if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
53
+ dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
24
+ error_setg(errp, "Invalid 'pic_irq_num'");
54
+ dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
25
+ return;
55
+ qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS);
56
+ qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE);
57
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
58
+
59
+ sysbus = SYS_BUS_DEVICE(dev);
60
+ for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) {
61
+ irq = VIRT_PLATFORM_BUS_IRQ - PCH_PIC_IRQ_OFFSET + i;
62
+ sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq));
26
+ }
63
+ }
64
+
65
+ memory_region_add_subregion(sysmem,
66
+ VIRT_PLATFORM_BUS_BASEADDRESS,
67
+ sysbus_mmio_get_region(sysbus, 0));
68
+ return dev;
27
+}
69
+}
28
+
70
+
29
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
71
static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams)
30
{
72
{
31
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
73
DeviceState *gpex_dev;
32
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
74
@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
33
+ Error *local_err = NULL;
75
memory_region_add_subregion(get_system_memory(), PM_BASE, pm_mem);
34
76
/* acpi ged */
35
- if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
77
lams->acpi_ged = create_acpi_ged(pch_pic, lams);
36
- error_setg(errp, "Invalid 'pic_irq_num'");
78
+ /* platform bus */
37
+ loongarch_pic_common_realize(dev, &local_err);
79
+ lams->platform_bus_dev = create_platform_bus(pch_pic);
38
+ if (local_err) {
39
+ error_propagate(errp, local_err);
40
return;
41
}
42
43
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
44
45
}
80
}
46
81
47
-static Property loongarch_pch_pic_properties[] = {
82
static void loongarch_irq_init(LoongArchMachineState *lams)
48
- DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPCHPIC, irq_num, 0),
83
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
49
+static Property loongarch_pic_common_properties[] = {
84
/* Initialize the IO interrupt subsystem */
50
+ DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
85
loongarch_irq_init(lams);
51
DEFINE_PROP_END_OF_LIST(),
86
fdt_add_irqchip_node(lams);
87
+ platform_bus_add_all_fdt_nodes(machine->fdt, "/intc",
88
+ VIRT_PLATFORM_BUS_BASEADDRESS,
89
+ VIRT_PLATFORM_BUS_SIZE,
90
+ VIRT_PLATFORM_BUS_IRQ);
91
lams->machine_done.notify = virt_machine_done;
92
qemu_add_machine_init_done_notifier(&lams->machine_done);
93
fdt_add_pcie_node(lams);
94
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
95
index XXXXXXX..XXXXXXX 100644
96
--- a/include/hw/loongarch/virt.h
97
+++ b/include/hw/loongarch/virt.h
98
@@ -XXX,XX +XXX,XX @@ struct LoongArchMachineState {
99
char *oem_table_id;
100
DeviceState *acpi_ged;
101
int fdt_size;
102
+ DeviceState *platform_bus_dev;
52
};
103
};
53
104
54
-static const VMStateDescription vmstate_loongarch_pch_pic = {
105
#define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("virt")
55
- .name = TYPE_LOONGARCH_PCH_PIC,
106
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
56
+static const VMStateDescription vmstate_loongarch_pic_common = {
107
index XXXXXXX..XXXXXXX 100644
57
+ .name = "loongarch_pch_pic",
108
--- a/include/hw/pci-host/ls7a.h
58
.version_id = 1,
109
+++ b/include/hw/pci-host/ls7a.h
59
.minimum_version_id = 1,
110
@@ -XXX,XX +XXX,XX @@
60
.fields = (const VMStateField[]) {
111
#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100)
61
- VMSTATE_UINT64(int_mask, LoongArchPCHPIC),
112
#define VIRT_RTC_LEN 0x100
62
- VMSTATE_UINT64(htmsi_en, LoongArchPCHPIC),
113
#define VIRT_SCI_IRQ (PCH_PIC_IRQ_OFFSET + 4)
63
- VMSTATE_UINT64(intedge, LoongArchPCHPIC),
114
+
64
- VMSTATE_UINT64(intclr, LoongArchPCHPIC),
115
+#define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000
65
- VMSTATE_UINT64(auto_crtl0, LoongArchPCHPIC),
116
+#define VIRT_PLATFORM_BUS_SIZE 0x2000000
66
- VMSTATE_UINT64(auto_crtl1, LoongArchPCHPIC),
117
+#define VIRT_PLATFORM_BUS_NUM_IRQS 2
67
- VMSTATE_UINT8_ARRAY(route_entry, LoongArchPCHPIC, 64),
118
+#define VIRT_PLATFORM_BUS_IRQ 69
68
- VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPCHPIC, 64),
119
#endif
69
- VMSTATE_UINT64(last_intirr, LoongArchPCHPIC),
70
- VMSTATE_UINT64(intirr, LoongArchPCHPIC),
71
- VMSTATE_UINT64(intisr, LoongArchPCHPIC),
72
- VMSTATE_UINT64(int_polarity, LoongArchPCHPIC),
73
+ VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
74
+ VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
75
+ VMSTATE_UINT64(intedge, LoongArchPICCommonState),
76
+ VMSTATE_UINT64(intclr, LoongArchPICCommonState),
77
+ VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
78
+ VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
79
+ VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
80
+ VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
81
+ VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
82
+ VMSTATE_UINT64(intirr, LoongArchPICCommonState),
83
+ VMSTATE_UINT64(intisr, LoongArchPICCommonState),
84
+ VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
85
VMSTATE_END_OF_LIST()
86
}
87
};
88
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
89
90
dc->realize = loongarch_pch_pic_realize;
91
device_class_set_legacy_reset(dc, loongarch_pch_pic_reset);
92
- dc->vmsd = &vmstate_loongarch_pch_pic;
93
- device_class_set_props(dc, loongarch_pch_pic_properties);
94
+ dc->vmsd = &vmstate_loongarch_pic_common;
95
+ device_class_set_props(dc, loongarch_pic_common_properties);
96
}
97
98
static const TypeInfo loongarch_pch_pic_info = {
99
--
120
--
100
2.43.5
121
2.31.1
diff view generated by jsdifflib
[PULL 05/18] hw/intc/loongarch_pch: Move some functions to file loongarch_pic_common
[PULL v2 5/9] hw/loongarch: Add hotplug handler for machine
1
Move some common functions to file loongarch_pic_common.c, the common
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
functions include loongarch_pic_common_realize(), property structure
3
loongarch_pic_common_properties and vmstate structure
4
vmstate_loongarch_pic_common.
5
2
6
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
3
Add hotplug handler for LoongArch virt machine and now only support
7
Reviewed-by: Song Gao <gaosong@loongson.cn>
4
the dynamic sysbus device.
5
6
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
7
Acked-by: Song Gao <gaosong@loongson.cn>
8
Message-Id: <20220908094623.73051-6-yangxiaojuan@loongson.cn>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
8
---
10
---
9
hw/intc/loongarch_pch_pic.c | 37 +-----------------------------
11
hw/loongarch/virt.c | 32 ++++++++++++++++++++++++++++++++
10
hw/intc/loongarch_pic_common.c | 41 ++++++++++++++++++++++++++++++++++
12
1 file changed, 32 insertions(+)
11
2 files changed, 42 insertions(+), 36 deletions(-)
12
create mode 100644 hw/intc/loongarch_pic_common.c
13
13
14
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
14
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/loongarch_pch_pic.c
16
--- a/hw/loongarch/virt.c
17
+++ b/hw/intc/loongarch_pch_pic.c
17
+++ b/hw/loongarch/virt.c
18
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
18
@@ -XXX,XX +XXX,XX @@ static void loongarch_machine_initfn(Object *obj)
19
s->int_polarity = 0x0;
19
lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
20
}
20
}
21
21
22
-static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
22
+static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev,
23
-{
23
+ DeviceState *dev, Error **errp)
24
- LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
24
+{
25
-
25
+ LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev);
26
- if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
26
+ MachineClass *mc = MACHINE_GET_CLASS(lams);
27
- error_setg(errp, "Invalid 'pic_irq_num'");
28
- return;
29
- }
30
-}
31
-
32
+#include "loongarch_pic_common.c"
33
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
34
{
35
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
36
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
37
38
}
39
40
-static Property loongarch_pic_common_properties[] = {
41
- DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
42
- DEFINE_PROP_END_OF_LIST(),
43
-};
44
-
45
-static const VMStateDescription vmstate_loongarch_pic_common = {
46
- .name = "loongarch_pch_pic",
47
- .version_id = 1,
48
- .minimum_version_id = 1,
49
- .fields = (const VMStateField[]) {
50
- VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
51
- VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
52
- VMSTATE_UINT64(intedge, LoongArchPICCommonState),
53
- VMSTATE_UINT64(intclr, LoongArchPICCommonState),
54
- VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
55
- VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
56
- VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
57
- VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
58
- VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
59
- VMSTATE_UINT64(intirr, LoongArchPICCommonState),
60
- VMSTATE_UINT64(intisr, LoongArchPICCommonState),
61
- VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
62
- VMSTATE_END_OF_LIST()
63
- }
64
-};
65
-
66
static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
67
{
68
DeviceClass *dc = DEVICE_CLASS(klass);
69
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
70
new file mode 100644
71
index XXXXXXX..XXXXXXX
72
--- /dev/null
73
+++ b/hw/intc/loongarch_pic_common.c
74
@@ -XXX,XX +XXX,XX @@
75
+/* SPDX-License-Identifier: GPL-2.0-or-later */
76
+/*
77
+ * QEMU Loongson 7A1000 I/O interrupt controller.
78
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
79
+ */
80
+
27
+
81
+static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
28
+ if (device_is_dynamic_sysbus(mc, dev)) {
82
+{
29
+ if (lams->platform_bus_dev) {
83
+ LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
30
+ platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev),
84
+
31
+ SYS_BUS_DEVICE(dev));
85
+ if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
32
+ }
86
+ error_setg(errp, "Invalid 'pic_irq_num'");
87
+ return;
88
+ }
33
+ }
89
+}
34
+}
90
+
35
+
91
+static Property loongarch_pic_common_properties[] = {
36
+static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
92
+ DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
37
+ DeviceState *dev)
93
+ DEFINE_PROP_END_OF_LIST(),
38
+{
94
+};
39
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
95
+
40
+
96
+static const VMStateDescription vmstate_loongarch_pic_common = {
41
+ if (device_is_dynamic_sysbus(mc, dev)) {
97
+ .name = "loongarch_pch_pic",
42
+ return HOTPLUG_HANDLER(machine);
98
+ .version_id = 1,
99
+ .minimum_version_id = 1,
100
+ .fields = (const VMStateField[]) {
101
+ VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
102
+ VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
103
+ VMSTATE_UINT64(intedge, LoongArchPICCommonState),
104
+ VMSTATE_UINT64(intclr, LoongArchPICCommonState),
105
+ VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
106
+ VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
107
+ VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
108
+ VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
109
+ VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
110
+ VMSTATE_UINT64(intirr, LoongArchPICCommonState),
111
+ VMSTATE_UINT64(intisr, LoongArchPICCommonState),
112
+ VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
113
+ VMSTATE_END_OF_LIST()
114
+ }
43
+ }
115
+};
44
+ return NULL;
45
+}
46
+
47
static void loongarch_class_init(ObjectClass *oc, void *data)
48
{
49
MachineClass *mc = MACHINE_CLASS(oc);
50
+ HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
51
52
mc->desc = "Loongson-3A5000 LS7A1000 machine";
53
mc->init = loongarch_init;
54
@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
55
mc->block_default_type = IF_VIRTIO;
56
mc->default_boot_order = "c";
57
mc->no_cdrom = 1;
58
+ mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
59
+ hc->plug = loongarch_machine_device_plug_cb;
60
61
object_class_property_add(oc, "acpi", "OnOffAuto",
62
loongarch_get_acpi, loongarch_set_acpi,
63
@@ -XXX,XX +XXX,XX @@ static const TypeInfo loongarch_machine_types[] = {
64
.instance_size = sizeof(LoongArchMachineState),
65
.class_init = loongarch_class_init,
66
.instance_init = loongarch_machine_initfn,
67
+ .interfaces = (InterfaceInfo[]) {
68
+ { TYPE_HOTPLUG_HANDLER },
69
+ { }
70
+ },
71
}
72
};
73
116
--
74
--
117
2.43.5
75
2.31.1
diff view generated by jsdifflib
[PULL 06/18] hw/intc/loongarch_pch: Inherit from loongarch_pic_common
[PULL v2 6/9] hw/loongarch: Add RAMFB to dynamic_sysbus_devices list
1
Set TYPE_LOONGARCH_PIC inherit from TYPE_LOONGARCH_PIC_COMMON object,
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
it shares vmsate and property of TYPE_LOONGARCH_PIC_COMMON, and has
3
its own realize() function.
4
2
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
3
Add RAMFB device to dynamic_sysbus_devices list so that it can be
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
4
hotpluged to the machine.
5
6
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
7
Acked-by: Song Gao <gaosong@loongson.cn>
8
Message-Id: <20220908094623.73051-7-yangxiaojuan@loongson.cn>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
7
---
10
---
8
hw/intc/loongarch_pch_pic.c | 38 ++++++++++++--------------
11
hw/loongarch/virt.c | 2 ++
9
hw/intc/loongarch_pic_common.c | 32 +++++++++++++++++++++-
12
1 file changed, 2 insertions(+)
10
hw/intc/meson.build | 2 +-
11
include/hw/intc/loongarch_pch_pic.h | 21 +++++++++++---
12
include/hw/intc/loongarch_pic_common.h | 10 +++++++
13
5 files changed, 77 insertions(+), 26 deletions(-)
14
13
15
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
14
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/loongarch_pch_pic.c
16
--- a/hw/loongarch/virt.c
18
+++ b/hw/intc/loongarch_pch_pic.c
17
+++ b/hw/loongarch/virt.c
19
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
18
@@ -XXX,XX +XXX,XX @@
20
s->int_polarity = 0x0;
19
#include <libfdt.h>
20
#include "hw/core/sysbus-fdt.h"
21
#include "hw/platform-bus.h"
22
+#include "hw/display/ramfb.h"
23
24
static void create_fdt(LoongArchMachineState *lams)
25
{
26
@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
27
NULL, NULL);
28
object_class_property_set_description(oc, "acpi",
29
"Enable ACPI");
30
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
21
}
31
}
22
32
23
-#include "loongarch_pic_common.c"
33
static const TypeInfo loongarch_machine_types[] = {
24
-static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
25
+static void loongarch_pic_realize(DeviceState *dev, Error **errp)
26
{
27
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
28
- SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
29
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
30
+ LoongarchPICClass *lpc = LOONGARCH_PIC_GET_CLASS(dev);
31
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
32
Error *local_err = NULL;
33
34
- loongarch_pic_common_realize(dev, &local_err);
35
+ lpc->parent_realize(dev, &local_err);
36
if (local_err) {
37
error_propagate(errp, local_err);
38
return;
39
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
40
41
}
42
43
-static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
44
+static void loongarch_pic_class_init(ObjectClass *klass, void *data)
45
{
46
DeviceClass *dc = DEVICE_CLASS(klass);
47
+ LoongarchPICClass *lpc = LOONGARCH_PIC_CLASS(klass);
48
49
- dc->realize = loongarch_pch_pic_realize;
50
device_class_set_legacy_reset(dc, loongarch_pch_pic_reset);
51
- dc->vmsd = &vmstate_loongarch_pic_common;
52
- device_class_set_props(dc, loongarch_pic_common_properties);
53
+ device_class_set_parent_realize(dc, loongarch_pic_realize,
54
+ &lpc->parent_realize);
55
}
56
57
-static const TypeInfo loongarch_pch_pic_info = {
58
- .name = TYPE_LOONGARCH_PCH_PIC,
59
- .parent = TYPE_SYS_BUS_DEVICE,
60
- .instance_size = sizeof(LoongArchPCHPIC),
61
- .class_init = loongarch_pch_pic_class_init,
62
+static const TypeInfo loongarch_pic_types[] = {
63
+ {
64
+ .name = TYPE_LOONGARCH_PIC,
65
+ .parent = TYPE_LOONGARCH_PIC_COMMON,
66
+ .instance_size = sizeof(LoongarchPICState),
67
+ .class_size = sizeof(LoongarchPICClass),
68
+ .class_init = loongarch_pic_class_init,
69
+ }
70
};
71
72
-static void loongarch_pch_pic_register_types(void)
73
-{
74
- type_register_static(&loongarch_pch_pic_info);
75
-}
76
-
77
-type_init(loongarch_pch_pic_register_types)
78
+DEFINE_TYPES(loongarch_pic_types)
79
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/intc/loongarch_pic_common.c
82
+++ b/hw/intc/loongarch_pic_common.c
83
@@ -XXX,XX +XXX,XX @@
84
* Copyright (C) 2024 Loongson Technology Corporation Limited
85
*/
86
87
+#include "qemu/osdep.h"
88
+#include "qapi/error.h"
89
+#include "hw/intc/loongarch_pic_common.h"
90
+#include "hw/qdev-properties.h"
91
+#include "migration/vmstate.h"
92
+
93
static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
94
{
95
- LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
96
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
97
98
if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
99
error_setg(errp, "Invalid 'pic_irq_num'");
100
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_pic_common = {
101
VMSTATE_END_OF_LIST()
102
}
103
};
104
+
105
+static void loongarch_pic_common_class_init(ObjectClass *klass, void *data)
106
+{
107
+ DeviceClass *dc = DEVICE_CLASS(klass);
108
+ LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_CLASS(klass);
109
+
110
+ device_class_set_parent_realize(dc, loongarch_pic_common_realize,
111
+ &lpcc->parent_realize);
112
+ device_class_set_props(dc, loongarch_pic_common_properties);
113
+ dc->vmsd = &vmstate_loongarch_pic_common;
114
+}
115
+
116
+static const TypeInfo loongarch_pic_common_types[] = {
117
+ {
118
+ .name = TYPE_LOONGARCH_PIC_COMMON,
119
+ .parent = TYPE_SYS_BUS_DEVICE,
120
+ .instance_size = sizeof(LoongArchPICCommonState),
121
+ .class_size = sizeof(LoongArchPICCommonClass),
122
+ .class_init = loongarch_pic_common_class_init,
123
+ .abstract = true,
124
+ }
125
+};
126
+
127
+DEFINE_TYPES(loongarch_pic_common_types)
128
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
129
index XXXXXXX..XXXXXXX 100644
130
--- a/hw/intc/meson.build
131
+++ b/hw/intc/meson.build
132
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
133
specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c'))
134
specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c'))
135
specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
136
-specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
137
+specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c', 'loongarch_pic_common.c'))
138
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
139
specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c'))
140
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
141
index XXXXXXX..XXXXXXX 100644
142
--- a/include/hw/intc/loongarch_pch_pic.h
143
+++ b/include/hw/intc/loongarch_pch_pic.h
144
@@ -XXX,XX +XXX,XX @@
145
146
#include "hw/intc/loongarch_pic_common.h"
147
148
-#define LoongArchPCHPIC LoongArchPICCommonState
149
-#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
150
-#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
151
-OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
152
+#define TYPE_LOONGARCH_PIC "loongarch_pic"
153
+#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PIC#name
154
+OBJECT_DECLARE_TYPE(LoongarchPICState, LoongarchPICClass, LOONGARCH_PIC)
155
+
156
+struct LoongarchPICState {
157
+ LoongArchPICCommonState parent_obj;
158
+};
159
+
160
+struct LoongarchPICClass {
161
+ LoongArchPICCommonClass parent_class;
162
+
163
+ DeviceRealize parent_realize;
164
+};
165
+
166
+#define TYPE_LOONGARCH_PCH_PIC TYPE_LOONGARCH_PIC
167
+typedef struct LoongArchPICCommonState LoongArchPCHPIC;
168
+#define LOONGARCH_PCH_PIC(obj) ((struct LoongArchPICCommonState *)(obj))
169
170
#endif /* HW_LOONGARCH_PCH_PIC_H */
171
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
172
index XXXXXXX..XXXXXXX 100644
173
--- a/include/hw/intc/loongarch_pic_common.h
174
+++ b/include/hw/intc/loongarch_pic_common.h
175
@@ -XXX,XX +XXX,XX @@
176
#define POL_LO_START 0x40
177
#define POL_HI_START 0x44
178
179
+#define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common"
180
+OBJECT_DECLARE_TYPE(LoongArchPICCommonState,
181
+ LoongArchPICCommonClass, LOONGARCH_PIC_COMMON)
182
+
183
struct LoongArchPICCommonState {
184
SysBusDevice parent_obj;
185
186
@@ -XXX,XX +XXX,XX @@ struct LoongArchPICCommonState {
187
MemoryRegion iomem8;
188
unsigned int irq_num;
189
};
190
+
191
+struct LoongArchPICCommonClass {
192
+ SysBusDeviceClass parent_class;
193
+
194
+ DeviceRealize parent_realize;
195
+};
196
#endif /* HW_LOONGARCH_PIC_COMMON_H */
197
--
34
--
198
2.43.5
35
2.31.1
diff view generated by jsdifflib
[PULL 03/18] hw/intc/loongarch_pch: Merge instance_init() into realize()
[PULL v2 7/9] hw/loongarch: Fix acpi ged irq number in dsdt table
1
Memory region is created in instance_init(), merge it into function
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
realize(). There is no special class_init() for loongarch_pch object.
3
2
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
3
In dsdt, acpi ged irq should use gsi number, and the
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
4
VIRT_SCI_IRQ means it.
5
6
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
7
Acked-by: Song Gao <gaosong@loongson.cn>
8
Message-Id: <20220908094623.73051-8-yangxiaojuan@loongson.cn>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
6
---
10
---
7
hw/intc/loongarch_pch_pic.c | 15 ++++-----------
11
hw/loongarch/acpi-build.c | 2 +-
8
1 file changed, 4 insertions(+), 11 deletions(-)
12
1 file changed, 1 insertion(+), 1 deletion(-)
9
13
10
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
14
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
11
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/intc/loongarch_pch_pic.c
16
--- a/hw/loongarch/acpi-build.c
13
+++ b/hw/intc/loongarch_pch_pic.c
17
+++ b/hw/loongarch/acpi-build.c
14
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
18
@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
15
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
19
if (lams->acpi_ged) {
16
{
20
build_ged_aml(dsdt, "\\_SB."GED_DEVICE,
17
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
21
HOTPLUG_HANDLER(lams->acpi_ged),
18
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
22
- VIRT_SCI_IRQ - PCH_PIC_IRQ_OFFSET, AML_SYSTEM_MEMORY,
19
23
+ VIRT_SCI_IRQ, AML_SYSTEM_MEMORY,
20
if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
24
VIRT_GED_EVT_ADDR);
21
error_setg(errp, "Invalid 'pic_irq_num'");
25
}
22
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
23
24
qdev_init_gpio_out(dev, s->parent_irq, s->irq_num);
25
qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num);
26
-}
27
-
28
-static void loongarch_pch_pic_init(Object *obj)
29
-{
30
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(obj);
31
- SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
32
-
33
- memory_region_init_io(&s->iomem32_low, obj,
34
+ memory_region_init_io(&s->iomem32_low, OBJECT(dev),
35
&loongarch_pch_pic_reg32_low_ops,
36
s, PCH_PIC_NAME(.reg32_part1), 0x100);
37
- memory_region_init_io(&s->iomem8, obj, &loongarch_pch_pic_reg8_ops,
38
+ memory_region_init_io(&s->iomem8, OBJECT(dev), &loongarch_pch_pic_reg8_ops,
39
s, PCH_PIC_NAME(.reg8), 0x2a0);
40
- memory_region_init_io(&s->iomem32_high, obj,
41
+ memory_region_init_io(&s->iomem32_high, OBJECT(dev),
42
&loongarch_pch_pic_reg32_high_ops,
43
s, PCH_PIC_NAME(.reg32_part2), 0xc60);
44
sysbus_init_mmio(sbd, &s->iomem32_low);
45
@@ -XXX,XX +XXX,XX @@ static const TypeInfo loongarch_pch_pic_info = {
46
.name = TYPE_LOONGARCH_PCH_PIC,
47
.parent = TYPE_SYS_BUS_DEVICE,
48
.instance_size = sizeof(LoongArchPCHPIC),
49
- .instance_init = loongarch_pch_pic_init,
50
.class_init = loongarch_pch_pic_class_init,
51
};
52
26
53
--
27
--
54
2.43.5
28
2.31.1
diff view generated by jsdifflib
[PULL 07/18] hw/intc/loongarch_pch: Add pre_save and post_load interfaces
Deleted patch
1
Add vmstate pre_save and post_load interfaces, which can be used
2
by pic kvm driver in future.
3
1
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
---
7
hw/intc/loongarch_pic_common.c | 26 ++++++++++++++++++++++++++
8
include/hw/intc/loongarch_pic_common.h | 2 ++
9
2 files changed, 28 insertions(+)
10
11
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/loongarch_pic_common.c
14
+++ b/hw/intc/loongarch_pic_common.c
15
@@ -XXX,XX +XXX,XX @@
16
#include "hw/qdev-properties.h"
17
#include "migration/vmstate.h"
18
19
+static int loongarch_pic_pre_save(void *opaque)
20
+{
21
+ LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
22
+ LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
23
+
24
+ if (lpcc->pre_save) {
25
+ return lpcc->pre_save(s);
26
+ }
27
+
28
+ return 0;
29
+}
30
+
31
+static int loongarch_pic_post_load(void *opaque, int version_id)
32
+{
33
+ LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
34
+ LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
35
+
36
+ if (lpcc->post_load) {
37
+ return lpcc->post_load(s, version_id);
38
+ }
39
+
40
+ return 0;
41
+}
42
+
43
static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
44
{
45
LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
46
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_pic_common = {
47
.name = "loongarch_pch_pic",
48
.version_id = 1,
49
.minimum_version_id = 1,
50
+ .pre_save = loongarch_pic_pre_save,
51
+ .post_load = loongarch_pic_post_load,
52
.fields = (const VMStateField[]) {
53
VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
54
VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
55
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
56
index XXXXXXX..XXXXXXX 100644
57
--- a/include/hw/intc/loongarch_pic_common.h
58
+++ b/include/hw/intc/loongarch_pic_common.h
59
@@ -XXX,XX +XXX,XX @@ struct LoongArchPICCommonClass {
60
SysBusDeviceClass parent_class;
61
62
DeviceRealize parent_realize;
63
+ int (*pre_save)(LoongArchPICCommonState *s);
64
+ int (*post_load)(LoongArchPICCommonState *s, int version_id);
65
};
66
#endif /* HW_LOONGARCH_PIC_COMMON_H */
67
--
68
2.43.5
diff view generated by jsdifflib
[PULL 08/18] hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic
[PULL v2 8/9] hw/loongarch: Support memory hotplug
1
Remove definition about LoongArchPCHPIC and LOONGARCH_PCH_PIC, and
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
replace them with LoongArchPICCommonState and LOONGARCH_PIC_COMMON
3
separately. Also remove unnecessary header files.
4
2
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
3
Add hotplug/unplug interface for memory device.
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
4
5
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
6
Acked-by: Song Gao <gaosong@loongson.cn>
7
Message-Id: <20220908094623.73051-9-yangxiaojuan@loongson.cn>
8
Signed-off-by: Song Gao <gaosong@loongson.cn>
7
---
9
---
8
hw/intc/loongarch_pch_pic.c | 24 ++++++++++--------------
10
hw/loongarch/Kconfig | 2 +
9
hw/loongarch/virt.c | 2 +-
11
hw/loongarch/acpi-build.c | 32 +++++++++---
10
include/hw/intc/loongarch_pch_pic.h | 4 ----
12
hw/loongarch/virt.c | 105 +++++++++++++++++++++++++++++++++++++-
11
3 files changed, 11 insertions(+), 19 deletions(-)
13
3 files changed, 132 insertions(+), 7 deletions(-)
12
14
13
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
15
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/loongarch_pch_pic.c
17
--- a/hw/loongarch/Kconfig
16
+++ b/hw/intc/loongarch_pch_pic.c
18
+++ b/hw/loongarch/Kconfig
17
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ config LOONGARCH_VIRT
18
20
select PCI_EXPRESS_GENERIC_BRIDGE
19
#include "qemu/osdep.h"
21
imply VIRTIO_VGA
20
#include "qemu/bitops.h"
22
imply PCI_DEVICES
21
-#include "hw/sysbus.h"
23
+ imply NVDIMM
22
-#include "hw/loongarch/virt.h"
24
select ISA_BUS
23
-#include "hw/pci-host/ls7a.h"
25
select SERIAL
24
#include "hw/irq.h"
26
select SERIAL_ISA
25
#include "hw/intc/loongarch_pch_pic.h"
27
@@ -XXX,XX +XXX,XX @@ config LOONGARCH_VIRT
26
-#include "hw/qdev-properties.h"
28
select ACPI_PCI
27
-#include "migration/vmstate.h"
29
select ACPI_HW_REDUCED
28
#include "trace.h"
30
select FW_CFG_DMA
29
#include "qapi/error.h"
31
+ select DIMM
30
32
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
31
-static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
33
index XXXXXXX..XXXXXXX 100644
32
+static void pch_pic_update_irq(LoongArchPICCommonState *s, uint64_t mask,
34
--- a/hw/loongarch/acpi-build.c
33
+ int level)
35
+++ b/hw/loongarch/acpi-build.c
34
{
36
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
35
uint64_t val;
37
build_srat_memory(table_data, VIRT_HIGHMEM_BASE, machine->ram_size - VIRT_LOWMEM_SIZE,
36
int irq;
38
0, MEM_AFFINITY_ENABLED);
37
@@ -XXX,XX +XXX,XX @@ static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
39
38
40
+ if (ms->device_memory) {
39
static void pch_pic_irq_handler(void *opaque, int irq, int level)
41
+ build_srat_memory(table_data, ms->device_memory->base,
40
{
42
+ memory_region_size(&ms->device_memory->mr),
41
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
43
+ 0, MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
42
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
44
+ }
43
uint64_t mask = 1ULL << irq;
45
+
44
46
acpi_table_end(linker, &table);
45
assert(irq < s->irq_num);
47
}
46
@@ -XXX,XX +XXX,XX @@ static void pch_pic_irq_handler(void *opaque, int irq, int level)
48
47
static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,
49
@@ -XXX,XX +XXX,XX @@ static void build_uart_device_aml(Aml *table)
48
unsigned size)
50
aml_append(table, scope);
49
{
51
}
50
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
52
51
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
53
+static void
52
uint64_t val = 0;
54
+build_la_ged_aml(Aml *dsdt, MachineState *machine)
53
uint32_t offset = addr & 0xfff;
55
+{
54
56
+ uint32_t event;
55
@@ -XXX,XX +XXX,XX @@ static uint64_t get_writew_val(uint64_t value, uint32_t target, bool hi)
57
+ LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
56
static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
58
+
57
uint64_t value, unsigned size)
59
+ build_ged_aml(dsdt, "\\_SB."GED_DEVICE,
58
{
60
+ HOTPLUG_HANDLER(lams->acpi_ged),
59
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
61
+ VIRT_SCI_IRQ, AML_SYSTEM_MEMORY,
60
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
62
+ VIRT_GED_EVT_ADDR);
61
uint32_t offset, old_valid, data = (uint32_t)value;
63
+ event = object_property_get_uint(OBJECT(lams->acpi_ged),
62
uint64_t old, int_mask;
64
+ "ged-event", &error_abort);
63
offset = addr & 0xfff;
65
+ if (event & ACPI_GED_MEM_HOTPLUG_EVT) {
64
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
66
+ build_memory_hotplug_aml(dsdt, machine->ram_slots, "\\_SB", NULL,
65
static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
67
+ AML_SYSTEM_MEMORY,
66
unsigned size)
68
+ VIRT_GED_MEM_ADDR);
67
{
69
+ }
68
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
70
+}
69
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
71
+
70
uint64_t val = 0;
72
/* build DSDT */
71
uint32_t offset = addr & 0xfff;
73
static void
72
74
build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
73
@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
75
@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
74
static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
76
75
uint64_t value, unsigned size)
77
build_gpex_pci0_int(dsdt);
76
{
78
build_uart_device_aml(dsdt);
77
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
79
- if (lams->acpi_ged) {
78
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
80
- build_ged_aml(dsdt, "\\_SB."GED_DEVICE,
79
uint32_t offset, data = (uint32_t)value;
81
- HOTPLUG_HANDLER(lams->acpi_ged),
80
offset = addr & 0xfff;
82
- VIRT_SCI_IRQ, AML_SYSTEM_MEMORY,
81
83
- VIRT_GED_EVT_ADDR);
82
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
84
- }
83
static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
85
+ build_la_ged_aml(dsdt, machine);
84
unsigned size)
86
85
{
87
scope = aml_scope("\\_SB.PCI0");
86
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
88
/* Build PCI0._CRS */
87
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
88
uint64_t val = 0;
89
uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
90
int64_t offset_tmp;
91
@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
92
static void loongarch_pch_pic_writeb(void *opaque, hwaddr addr,
93
uint64_t data, unsigned size)
94
{
95
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
96
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
97
int32_t offset_tmp;
98
uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
99
100
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps loongarch_pch_pic_reg8_ops = {
101
102
static void loongarch_pch_pic_reset(DeviceState *d)
103
{
104
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(d);
105
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(d);
106
int i;
107
108
s->int_mask = -1;
109
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
89
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
110
index XXXXXXX..XXXXXXX 100644
90
index XXXXXXX..XXXXXXX 100644
111
--- a/hw/loongarch/virt.c
91
--- a/hw/loongarch/virt.c
112
+++ b/hw/loongarch/virt.c
92
+++ b/hw/loongarch/virt.c
113
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
93
@@ -XXX,XX +XXX,XX @@
114
/* Add Extend I/O Interrupt Controller node */
94
#include "hw/core/sysbus-fdt.h"
115
fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
95
#include "hw/platform-bus.h"
116
96
#include "hw/display/ramfb.h"
117
- pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
97
+#include "hw/mem/pc-dimm.h"
118
+ pch_pic = qdev_new(TYPE_LOONGARCH_PIC);
98
119
num = VIRT_PCH_PIC_IRQ_NUM;
99
static void create_fdt(LoongArchMachineState *lams)
120
qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
100
{
121
d = SYS_BUS_DEVICE(pch_pic);
101
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
122
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
102
machine->ram, offset, highram_size);
123
index XXXXXXX..XXXXXXX 100644
103
memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem);
124
--- a/include/hw/intc/loongarch_pch_pic.h
104
memmap_add_entry(0x90000000, highram_size, 1);
125
+++ b/include/hw/intc/loongarch_pch_pic.h
105
+
126
@@ -XXX,XX +XXX,XX @@ struct LoongarchPICClass {
106
+ /* initialize device memory address space */
127
DeviceRealize parent_realize;
107
+ if (machine->ram_size < machine->maxram_size) {
128
};
108
+ machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
129
109
+ ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
130
-#define TYPE_LOONGARCH_PCH_PIC TYPE_LOONGARCH_PIC
110
+
131
-typedef struct LoongArchPICCommonState LoongArchPCHPIC;
111
+ if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
132
-#define LOONGARCH_PCH_PIC(obj) ((struct LoongArchPICCommonState *)(obj))
112
+ error_report("unsupported amount of memory slots: %"PRIu64,
133
-
113
+ machine->ram_slots);
134
#endif /* HW_LOONGARCH_PCH_PIC_H */
114
+ exit(EXIT_FAILURE);
115
+ }
116
+
117
+ if (QEMU_ALIGN_UP(machine->maxram_size,
118
+ TARGET_PAGE_SIZE) != machine->maxram_size) {
119
+ error_report("maximum memory size must by aligned to multiple of "
120
+ "%d bytes", TARGET_PAGE_SIZE);
121
+ exit(EXIT_FAILURE);
122
+ }
123
+ /* device memory base is the top of high memory address. */
124
+ machine->device_memory->base = 0x90000000 + highram_size;
125
+ machine->device_memory->base =
126
+ ROUND_UP(machine->device_memory->base, 1 * GiB);
127
+
128
+ memory_region_init(&machine->device_memory->mr, OBJECT(lams),
129
+ "device-memory", device_mem_size);
130
+ memory_region_add_subregion(address_space_mem, machine->device_memory->base,
131
+ &machine->device_memory->mr);
132
+ }
133
+
134
/* Add isa io region */
135
memory_region_init_alias(&lams->isa_io, NULL, "isa-io",
136
get_system_io(), 0, VIRT_ISA_IO_SIZE);
137
@@ -XXX,XX +XXX,XX @@ static void loongarch_machine_initfn(Object *obj)
138
lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
139
}
140
141
+static bool memhp_type_supported(DeviceState *dev)
142
+{
143
+ /* we only support pc dimm now */
144
+ return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) &&
145
+ !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
146
+}
147
+
148
+static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
149
+ Error **errp)
150
+{
151
+ pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
152
+}
153
+
154
+static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev,
155
+ DeviceState *dev, Error **errp)
156
+{
157
+ if (memhp_type_supported(dev)) {
158
+ virt_mem_pre_plug(hotplug_dev, dev, errp);
159
+ }
160
+}
161
+
162
+static void virt_mem_unplug_request(HotplugHandler *hotplug_dev,
163
+ DeviceState *dev, Error **errp)
164
+{
165
+ LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev);
166
+
167
+ /* the acpi ged is always exist */
168
+ hotplug_handler_unplug_request(HOTPLUG_HANDLER(lams->acpi_ged), dev,
169
+ errp);
170
+}
171
+
172
+static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev,
173
+ DeviceState *dev, Error **errp)
174
+{
175
+ if (memhp_type_supported(dev)) {
176
+ virt_mem_unplug_request(hotplug_dev, dev, errp);
177
+ }
178
+}
179
+
180
+static void virt_mem_unplug(HotplugHandler *hotplug_dev,
181
+ DeviceState *dev, Error **errp)
182
+{
183
+ LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev);
184
+
185
+ hotplug_handler_unplug(HOTPLUG_HANDLER(lams->acpi_ged), dev, errp);
186
+ pc_dimm_unplug(PC_DIMM(dev), MACHINE(lams));
187
+ qdev_unrealize(dev);
188
+}
189
+
190
+static void virt_machine_device_unplug(HotplugHandler *hotplug_dev,
191
+ DeviceState *dev, Error **errp)
192
+{
193
+ if (memhp_type_supported(dev)) {
194
+ virt_mem_unplug(hotplug_dev, dev, errp);
195
+ }
196
+}
197
+
198
+static void virt_mem_plug(HotplugHandler *hotplug_dev,
199
+ DeviceState *dev, Error **errp)
200
+{
201
+ LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev);
202
+
203
+ pc_dimm_plug(PC_DIMM(dev), MACHINE(lams));
204
+ hotplug_handler_plug(HOTPLUG_HANDLER(lams->acpi_ged),
205
+ dev, &error_abort);
206
+}
207
+
208
static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev,
209
DeviceState *dev, Error **errp)
210
{
211
@@ -XXX,XX +XXX,XX @@ static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev,
212
platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev),
213
SYS_BUS_DEVICE(dev));
214
}
215
+ } else if (memhp_type_supported(dev)) {
216
+ virt_mem_plug(hotplug_dev, dev, errp);
217
}
218
}
219
220
@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
221
{
222
MachineClass *mc = MACHINE_GET_CLASS(machine);
223
224
- if (device_is_dynamic_sysbus(mc, dev)) {
225
+ if (device_is_dynamic_sysbus(mc, dev) ||
226
+ memhp_type_supported(dev)) {
227
return HOTPLUG_HANDLER(machine);
228
}
229
return NULL;
230
@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
231
mc->no_cdrom = 1;
232
mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
233
hc->plug = loongarch_machine_device_plug_cb;
234
+ hc->pre_plug = virt_machine_device_pre_plug;
235
+ hc->unplug_request = virt_machine_device_unplug_request;
236
+ hc->unplug = virt_machine_device_unplug;
237
238
object_class_property_add(oc, "acpi", "OnOffAuto",
239
loongarch_get_acpi, loongarch_set_acpi,
135
--
240
--
136
2.43.5
241
2.31.1
diff view generated by jsdifflib
[PULL 12/18] hw/intc/loongarch_extioi: Rename LoongArchExtIOI with LoongArchExtIOICommonState
[PULL v2 9/9] hw/loongarch: Improve acpi dsdt table
1
With some structure such as vmstate and property, rename LoongArchExtIOI
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
with LoongArchExtIOICommonState, these common structure will be moved
3
to common file.
4
2
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
3
Cleanup the previous pci information in acpi dsdt table.
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
4
And using the common acpi_dsdt_add_gpex function to build
5
the gpex and pci information.
6
7
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
8
Acked-by: Song Gao <gaosong@loongson.cn>
9
Message-Id: <20220908094623.73051-10-yangxiaojuan@loongson.cn>
10
Signed-off-by: Song Gao <gaosong@loongson.cn>
7
---
11
---
8
hw/intc/loongarch_extioi.c | 41 +++++++++++++++++++++++---------------
12
hw/loongarch/acpi-build.c | 159 +++++-------------------------------
9
1 file changed, 25 insertions(+), 16 deletions(-)
13
hw/loongarch/virt.c | 1 +
14
include/hw/loongarch/virt.h | 1 +
15
3 files changed, 21 insertions(+), 140 deletions(-)
10
16
11
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
17
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/loongarch_extioi.c
19
--- a/hw/loongarch/acpi-build.c
14
+++ b/hw/intc/loongarch_extioi.c
20
+++ b/hw/loongarch/acpi-build.c
15
@@ -XXX,XX +XXX,XX @@ static int vmstate_extioi_post_load(void *opaque, int version_id)
21
@@ -XXX,XX +XXX,XX @@
16
return 0;
22
#include "qom/qom-qobject.h"
23
24
#include "hw/acpi/generic_event_device.h"
25
+#include "hw/pci-host/gpex.h"
26
27
#define ACPI_BUILD_ALIGN_SIZE 0x1000
28
#define ACPI_BUILD_TABLE_SIZE 0x20000
29
@@ -XXX,XX +XXX,XX @@ struct AcpiBuildState {
30
MemoryRegion *linker_mr;
31
} AcpiBuildState;
32
33
-static void build_gpex_pci0_int(Aml *table)
34
-{
35
- Aml *sb_scope = aml_scope("_SB");
36
- Aml *pci0_scope = aml_scope("PCI0");
37
- Aml *prt_pkg = aml_varpackage(128);
38
- int slot, pin;
39
-
40
- for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
41
- for (pin = 0; pin < PCI_NUM_PINS; pin++) {
42
- Aml *pkg = aml_package(4);
43
- aml_append(pkg, aml_int((slot << 16) | 0xFFFF));
44
- aml_append(pkg, aml_int(pin));
45
- aml_append(pkg, aml_int(0));
46
- aml_append(pkg, aml_int(80 + (slot + pin) % 4));
47
- aml_append(prt_pkg, pkg);
48
- }
49
- }
50
- aml_append(pci0_scope, aml_name_decl("_PRT", prt_pkg));
51
- aml_append(sb_scope, pci0_scope);
52
- aml_append(table, sb_scope);
53
-}
54
-
55
-static void build_dbg_aml(Aml *table)
56
-{
57
- Aml *field;
58
- Aml *method;
59
- Aml *while_ctx;
60
- Aml *scope = aml_scope("\\");
61
- Aml *buf = aml_local(0);
62
- Aml *len = aml_local(1);
63
- Aml *idx = aml_local(2);
64
-
65
- aml_append(scope,
66
- aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
67
- field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
68
- aml_append(field, aml_named_field("DBGB", 8));
69
- aml_append(scope, field);
70
-
71
- method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
72
-
73
- aml_append(method, aml_to_hexstring(aml_arg(0), buf));
74
- aml_append(method, aml_to_buffer(buf, buf));
75
- aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
76
- aml_append(method, aml_store(aml_int(0), idx));
77
-
78
- while_ctx = aml_while(aml_lless(idx, len));
79
- aml_append(while_ctx,
80
- aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
81
- aml_append(while_ctx, aml_increment(idx));
82
- aml_append(method, while_ctx);
83
- aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
84
- aml_append(scope, method);
85
- aml_append(table, scope);
86
-}
87
-
88
-static Aml *build_osc_method(void)
89
-{
90
- Aml *if_ctx;
91
- Aml *if_ctx2;
92
- Aml *else_ctx;
93
- Aml *method;
94
- Aml *a_cwd1 = aml_name("CDW1");
95
- Aml *a_ctrl = aml_local(0);
96
-
97
- method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
98
- aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
99
-
100
- if_ctx = aml_if(aml_equal(
101
- aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
102
- aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
103
- aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
104
- aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
105
-
106
- /*
107
- * Always allow native PME, AER (no dependencies)
108
- * Allow SHPC (PCI bridges can have SHPC controller)
109
- */
110
- aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
111
-
112
- if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
113
- /* Unknown revision */
114
- aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
115
- aml_append(if_ctx, if_ctx2);
116
-
117
- if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
118
- /* Capabilities bits were masked */
119
- aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
120
- aml_append(if_ctx, if_ctx2);
121
-
122
- /* Update DWORD3 in the buffer */
123
- aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
124
- aml_append(method, if_ctx);
125
-
126
- else_ctx = aml_else();
127
- /* Unrecognized UUID */
128
- aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
129
- aml_append(method, else_ctx);
130
-
131
- aml_append(method, aml_return(aml_arg(3)));
132
- return method;
133
-}
134
-
135
static void build_uart_device_aml(Aml *table)
136
{
137
Aml *dev;
138
@@ -XXX,XX +XXX,XX @@ build_la_ged_aml(Aml *dsdt, MachineState *machine)
139
}
17
}
140
}
18
141
19
+static int loongarch_extioi_common_post_load(void *opaque, int version_id)
142
+static void build_pci_device_aml(Aml *scope, LoongArchMachineState *lams)
20
+{
143
+{
21
+ return vmstate_extioi_post_load(opaque, version_id);
144
+ struct GPEXConfig cfg = {
145
+ .mmio64.base = VIRT_PCI_MEM_BASE,
146
+ .mmio64.size = VIRT_PCI_MEM_SIZE,
147
+ .pio.base = VIRT_PCI_IO_BASE,
148
+ .pio.size = VIRT_PCI_IO_SIZE,
149
+ .ecam.base = VIRT_PCI_CFG_BASE,
150
+ .ecam.size = VIRT_PCI_CFG_SIZE,
151
+ .irq = PCH_PIC_IRQ_OFFSET + VIRT_DEVICE_IRQS,
152
+ .bus = lams->pci_bus,
153
+ };
154
+
155
+ acpi_dsdt_add_gpex(scope, &cfg);
22
+}
156
+}
23
+
157
+
24
static const VMStateDescription vmstate_extioi_core = {
158
/* build DSDT */
25
.name = "extioi-core",
159
static void
26
.version_id = 1,
160
build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
27
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_extioi_core = {
161
{
162
- Aml *dsdt, *sb_scope, *scope, *dev, *crs, *pkg;
163
- int root_bus_limit = 0x7F;
164
+ Aml *dsdt, *scope, *pkg;
165
LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
166
AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = lams->oem_id,
167
.oem_table_id = lams->oem_table_id };
168
169
acpi_table_begin(&table, table_data);
170
-
171
dsdt = init_aml_allocator();
172
-
173
- build_dbg_aml(dsdt);
174
-
175
- sb_scope = aml_scope("_SB");
176
- dev = aml_device("PCI0");
177
- aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
178
- aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
179
- aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
180
- aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
181
- aml_append(dev, aml_name_decl("_UID", aml_int(1)));
182
- aml_append(dev, build_osc_method());
183
- aml_append(sb_scope, dev);
184
- aml_append(dsdt, sb_scope);
185
-
186
- build_gpex_pci0_int(dsdt);
187
build_uart_device_aml(dsdt);
188
+ build_pci_device_aml(dsdt, lams);
189
build_la_ged_aml(dsdt, machine);
190
191
- scope = aml_scope("\\_SB.PCI0");
192
- /* Build PCI0._CRS */
193
- crs = aml_resource_template();
194
- aml_append(crs,
195
- aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
196
- 0x0000, 0x0, root_bus_limit,
197
- 0x0000, root_bus_limit + 1));
198
- aml_append(crs,
199
- aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED,
200
- AML_POS_DECODE, AML_ENTIRE_RANGE,
201
- 0x0000, 0x0000, 0xFFFF, 0x18000000, 0x10000));
202
- aml_append(crs,
203
- aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
204
- AML_CACHEABLE, AML_READ_WRITE,
205
- 0, VIRT_PCI_MEM_BASE,
206
- VIRT_PCI_MEM_BASE + VIRT_PCI_MEM_SIZE - 1,
207
- 0, VIRT_PCI_MEM_BASE));
208
- aml_append(scope, aml_name_decl("_CRS", crs));
209
- aml_append(dsdt, scope);
210
-
211
/* System State Package */
212
scope = aml_scope("\\");
213
pkg = aml_package(4);
214
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
215
index XXXXXXX..XXXXXXX 100644
216
--- a/hw/loongarch/virt.c
217
+++ b/hw/loongarch/virt.c
218
@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
219
d = SYS_BUS_DEVICE(gpex_dev);
220
sysbus_realize_and_unref(d, &error_fatal);
221
pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus;
222
+ lams->pci_bus = pci_bus;
223
224
/* Map only part size_ecam bytes of ECAM space */
225
ecam_alias = g_new0(MemoryRegion, 1);
226
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
227
index XXXXXXX..XXXXXXX 100644
228
--- a/include/hw/loongarch/virt.h
229
+++ b/include/hw/loongarch/virt.h
230
@@ -XXX,XX +XXX,XX @@ struct LoongArchMachineState {
231
DeviceState *acpi_ged;
232
int fdt_size;
233
DeviceState *platform_bus_dev;
234
+ PCIBus *pci_bus;
28
};
235
};
29
236
30
static const VMStateDescription vmstate_loongarch_extioi = {
237
#define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("virt")
31
- .name = TYPE_LOONGARCH_EXTIOI,
32
+ .name = "loongarch.extioi",
33
.version_id = 3,
34
.minimum_version_id = 3,
35
- .post_load = vmstate_extioi_post_load,
36
+ .post_load = loongarch_extioi_common_post_load,
37
.fields = (const VMStateField[]) {
38
- VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
39
- VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
40
+ VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOICommonState,
41
+ EXTIOI_IRQS_GROUP_COUNT),
42
+ VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOICommonState,
43
EXTIOI_IRQS_NODETYPE_COUNT / 2),
44
- VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOI, EXTIOI_IRQS / 32),
45
- VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOI, EXTIOI_IRQS / 32),
46
- VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOI, EXTIOI_IRQS_IPMAP_SIZE / 4),
47
- VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOI, EXTIOI_IRQS / 4),
48
-
49
- VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOI, num_cpu,
50
- vmstate_extioi_core, ExtIOICore),
51
- VMSTATE_UINT32(features, LoongArchExtIOI),
52
- VMSTATE_UINT32(status, LoongArchExtIOI),
53
+ VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOICommonState,
54
+ EXTIOI_IRQS / 32),
55
+ VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOICommonState,
56
+ EXTIOI_IRQS / 32),
57
+ VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOICommonState,
58
+ EXTIOI_IRQS_IPMAP_SIZE / 4),
59
+ VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOICommonState,
60
+ EXTIOI_IRQS / 4),
61
+ VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOICommonState,
62
+ num_cpu, vmstate_extioi_core, ExtIOICore),
63
+ VMSTATE_UINT32(features, LoongArchExtIOICommonState),
64
+ VMSTATE_UINT32(status, LoongArchExtIOICommonState),
65
VMSTATE_END_OF_LIST()
66
}
67
};
68
69
static Property extioi_properties[] = {
70
- DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOI, num_cpu, 1),
71
- DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOI, features,
72
- EXTIOI_HAS_VIRT_EXTENSION, 0),
73
+ DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOICommonState, num_cpu, 1),
74
+ DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOICommonState,
75
+ features, EXTIOI_HAS_VIRT_EXTENSION, 0),
76
DEFINE_PROP_END_OF_LIST(),
77
};
78
79
--
238
--
80
2.43.5
239
2.31.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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