| 1 | Pretty small still, but there are two patches that ought | 1 | v2: Rebase and resolve target/loongarch conflicts. |
|---|---|---|---|
| 2 | to get backported to stable, so no point in delaying. | 2 | Include linux-user/aarch64 vdso fix. |
| 3 | 3 | ||
| 4 | r~ | 4 | r~ |
| 5 | 5 | ||
| 6 | The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307: | 6 | The following changes since commit 29b008927ef6e3fbb70e6607b25d3fcae26a5190: |
| 7 | 7 | ||
| 8 | Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000) | 8 | Merge tag 'pull-nic-config-2-20240202' of git://git.infradead.org/users/dwmw2/qemu into staging (2024-02-02 16:47:36 +0000) |
| 9 | 9 | ||
| 10 | are available in the Git repository at: | 10 | are available in the Git repository at: |
| 11 | 11 | ||
| 12 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212 | 12 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240202-2 |
| 13 | 13 | ||
| 14 | for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf: | 14 | for you to fetch changes up to 6400be014f80e4c2c246eb8be709ea3a96428233: |
| 15 | 15 | ||
| 16 | target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600) | 16 | linux-user/aarch64: Add padding before __kernel_rt_sigreturn (2024-02-03 16:46:10 +1000) |
| 17 | 17 | ||
| 18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 19 | tcg: Reset free_temps before tcg_optimize | 19 | tests/tcg: Fix multiarch/gdbstub/prot-none.py |
| 20 | tcg/riscv: Fix StoreStore barrier generation | 20 | hw/core: Convert cpu_mmu_index to a CPUClass hook |
| 21 | include/exec: Introduce fpst alias in helper-head.h.inc | 21 | tcg/loongarch64: Set vector registers call clobbered |
| 22 | target/sparc: Use memcpy() and remove memcpy32() | 22 | target/sparc: floating-point cleanup |
| 23 | linux-user/aarch64: Add padding before __kernel_rt_sigreturn | ||
| 23 | 24 | ||
| 24 | ---------------------------------------------------------------- | 25 | ---------------------------------------------------------------- |
| 25 | Philippe Mathieu-Daudé (1): | 26 | Ilya Leoshkevich (1): |
| 26 | target/sparc: Use memcpy() and remove memcpy32() | 27 | tests/tcg: Fix the /proc/self/mem probing in the PROT_NONE gdbstub test |
| 27 | 28 | ||
| 28 | Richard Henderson (2): | 29 | Richard Henderson (57): |
| 29 | tcg: Reset free_temps before tcg_optimize | 30 | include/hw/core: Add mmu_index to CPUClass |
| 30 | include/exec: Introduce fpst alias in helper-head.h.inc | 31 | target/alpha: Split out alpha_env_mmu_index |
| 32 | target/alpha: Populate CPUClass.mmu_index | ||
| 33 | target/arm: Split out arm_env_mmu_index | ||
| 34 | target/arm: Populate CPUClass.mmu_index | ||
| 35 | target/avr: Populate CPUClass.mmu_index | ||
| 36 | target/cris: Cache mem_index in DisasContext | ||
| 37 | target/cris: Populate CPUClass.mmu_index | ||
| 38 | target/hppa: Populate CPUClass.mmu_index | ||
| 39 | target/i386: Populate CPUClass.mmu_index | ||
| 40 | target/loongarch: Populate CPUClass.mmu_index | ||
| 41 | target/loongarch: Rename MMU_IDX_* | ||
| 42 | target/m68k: Populate CPUClass.mmu_index | ||
| 43 | target/microblaze: Populate CPUClass.mmu_index | ||
| 44 | target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill | ||
| 45 | target/mips: Split out mips_env_mmu_index | ||
| 46 | target/mips: Populate CPUClass.mmu_index | ||
| 47 | target/nios2: Populate CPUClass.mmu_index | ||
| 48 | target/openrisc: Populate CPUClass.mmu_index | ||
| 49 | target/ppc: Split out ppc_env_mmu_index | ||
| 50 | target/ppc: Populate CPUClass.mmu_index | ||
| 51 | target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index | ||
| 52 | target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index | ||
| 53 | target/riscv: Populate CPUClass.mmu_index | ||
| 54 | target/rx: Populate CPUClass.mmu_index | ||
| 55 | target/s390x: Split out s390x_env_mmu_index | ||
| 56 | target/s390x: Populate CPUClass.mmu_index | ||
| 57 | target/sh4: Populate CPUClass.mmu_index | ||
| 58 | target/sparc: Populate CPUClass.mmu_index | ||
| 59 | target/tricore: Populate CPUClass.mmu_index | ||
| 60 | target/xtensa: Populate CPUClass.mmu_index | ||
| 61 | include/exec: Implement cpu_mmu_index generically | ||
| 62 | include/exec: Change cpu_mmu_index argument to CPUState | ||
| 63 | tcg/loongarch64: Set vector registers call clobbered | ||
| 64 | target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BCOPY | ||
| 65 | target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILL | ||
| 66 | target/sparc: Remove gen_dest_fpr_F | ||
| 67 | target/sparc: Introduce gen_{load,store}_fpr_Q | ||
| 68 | target/sparc: Inline FNEG, FABS | ||
| 69 | target/sparc: Use i128 for FSQRTq | ||
| 70 | target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq | ||
| 71 | target/sparc: Use i128 for FqTOs, FqTOi | ||
| 72 | target/sparc: Use i128 for FqTOd, FqTOx | ||
| 73 | target/sparc: Use i128 for FCMPq, FCMPEq | ||
| 74 | target/sparc: Use i128 for FsTOq, FiTOq | ||
| 75 | target/sparc: Use i128 for FdTOq, FxTOq | ||
| 76 | target/sparc: Use i128 for Fdmulq | ||
| 77 | target/sparc: Remove qt0, qt1 temporaries | ||
| 78 | target/sparc: Introduce cpu_get_fsr, cpu_put_fsr | ||
| 79 | target/sparc: Split ver from env->fsr | ||
| 80 | target/sparc: Clear cexc and ftt in do_check_ieee_exceptions | ||
| 81 | target/sparc: Merge check_ieee_exceptions with FPop helpers | ||
| 82 | target/sparc: Split cexc and ftt from env->fsr | ||
| 83 | target/sparc: Remove cpu_fsr | ||
| 84 | target/sparc: Split fcc out of env->fsr | ||
| 85 | target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK | ||
| 86 | linux-user/aarch64: Add padding before __kernel_rt_sigreturn | ||
| 31 | 87 | ||
| 32 | Roman Artemev (1): | 88 | include/exec/cpu-all.h | 4 + |
| 33 | tcg/riscv: Fix StoreStore barrier generation | 89 | include/exec/cpu-common.h | 21 + |
| 34 | 90 | include/hw/core/cpu.h | 3 + | |
| 35 | include/tcg/tcg-temp-internal.h | 6 ++++++ | 91 | target/alpha/cpu.h | 2 +- |
| 36 | accel/tcg/plugin-gen.c | 2 +- | 92 | target/arm/cpu.h | 13 - |
| 37 | target/sparc/win_helper.c | 26 ++++++++------------------ | 93 | target/arm/internals.h | 5 + |
| 38 | tcg/tcg.c | 5 ++++- | 94 | target/avr/cpu.h | 7 - |
| 39 | include/exec/helper-head.h.inc | 3 +++ | 95 | target/cris/cpu.h | 4 - |
| 40 | tcg/riscv/tcg-target.c.inc | 2 +- | 96 | target/hexagon/cpu.h | 9 - |
| 41 | 6 files changed, 23 insertions(+), 21 deletions(-) | 97 | target/hppa/cpu.h | 13 - |
| 42 | 98 | target/i386/cpu.h | 7 - | |
| 99 | target/loongarch/cpu.h | 18 +- | ||
| 100 | target/m68k/cpu.h | 4 - | ||
| 101 | target/microblaze/cpu.h | 15 - | ||
| 102 | target/mips/cpu.h | 6 +- | ||
| 103 | target/nios2/cpu.h | 6 - | ||
| 104 | target/openrisc/cpu.h | 12 - | ||
| 105 | target/ppc/cpu.h | 2 +- | ||
| 106 | target/riscv/cpu.h | 4 +- | ||
| 107 | target/rx/cpu.h | 5 - | ||
| 108 | target/s390x/cpu.h | 2 +- | ||
| 109 | target/sh4/cpu.h | 10 - | ||
| 110 | target/sparc/cpu.h | 69 +- | ||
| 111 | target/sparc/helper.h | 116 ++- | ||
| 112 | target/tricore/cpu.h | 5 - | ||
| 113 | target/xtensa/cpu.h | 5 - | ||
| 114 | accel/tcg/cputlb.c | 22 +- | ||
| 115 | linux-user/sparc/cpu_loop.c | 2 +- | ||
| 116 | linux-user/sparc/signal.c | 14 +- | ||
| 117 | semihosting/uaccess.c | 2 +- | ||
| 118 | target/alpha/cpu.c | 6 + | ||
| 119 | target/alpha/translate.c | 2 +- | ||
| 120 | target/arm/cpu.c | 6 + | ||
| 121 | target/arm/helper.c | 2 +- | ||
| 122 | target/arm/tcg/helper-a64.c | 4 +- | ||
| 123 | target/arm/tcg/mte_helper.c | 18 +- | ||
| 124 | target/arm/tcg/sve_helper.c | 8 +- | ||
| 125 | target/arm/tcg/tlb_helper.c | 2 +- | ||
| 126 | target/avr/cpu.c | 6 + | ||
| 127 | target/cris/cpu.c | 6 + | ||
| 128 | target/cris/translate.c | 14 +- | ||
| 129 | target/hppa/cpu.c | 12 + | ||
| 130 | target/hppa/mem_helper.c | 2 +- | ||
| 131 | target/hppa/op_helper.c | 8 +- | ||
| 132 | target/i386/cpu.c | 10 + | ||
| 133 | target/i386/tcg/translate.c | 2 +- | ||
| 134 | target/loongarch/cpu.c | 11 + | ||
| 135 | target/loongarch/cpu_helper.c | 6 +- | ||
| 136 | target/loongarch/tcg/tlb_helper.c | 2 +- | ||
| 137 | target/loongarch/tcg/translate.c | 2 +- | ||
| 138 | target/m68k/cpu.c | 6 + | ||
| 139 | target/m68k/op_helper.c | 2 +- | ||
| 140 | target/microblaze/cpu.c | 18 +- | ||
| 141 | target/microblaze/helper.c | 3 +- | ||
| 142 | target/microblaze/mmu.c | 2 +- | ||
| 143 | target/microblaze/translate.c | 2 +- | ||
| 144 | target/mips/cpu.c | 6 + | ||
| 145 | target/mips/sysemu/physaddr.c | 2 +- | ||
| 146 | target/mips/tcg/msa_helper.c | 10 +- | ||
| 147 | target/mips/tcg/sysemu/cp0_helper.c | 2 +- | ||
| 148 | target/mips/tcg/sysemu/special_helper.c | 2 +- | ||
| 149 | target/mips/tcg/sysemu/tlb_helper.c | 34 +- | ||
| 150 | target/nios2/cpu.c | 7 + | ||
| 151 | target/nios2/translate.c | 2 +- | ||
| 152 | target/openrisc/cpu.c | 13 + | ||
| 153 | target/openrisc/translate.c | 2 +- | ||
| 154 | target/ppc/cpu_init.c | 8 +- | ||
| 155 | target/ppc/mem_helper.c | 10 +- | ||
| 156 | target/ppc/mmu_common.c | 4 +- | ||
| 157 | target/riscv/cpu.c | 6 + | ||
| 158 | target/riscv/cpu_helper.c | 6 +- | ||
| 159 | target/riscv/op_helper.c | 4 +- | ||
| 160 | target/riscv/vector_helper.c | 9 +- | ||
| 161 | target/rx/cpu.c | 6 + | ||
| 162 | target/s390x/cpu.c | 6 + | ||
| 163 | target/s390x/tcg/mem_helper.c | 34 +- | ||
| 164 | target/sh4/cpu.c | 16 + | ||
| 165 | target/sparc/cpu.c | 61 +- | ||
| 166 | target/sparc/fop_helper.c | 510 +++++++------ | ||
| 167 | target/sparc/gdbstub.c | 8 +- | ||
| 168 | target/sparc/ldst_helper.c | 5 +- | ||
| 169 | target/sparc/machine.c | 36 +- | ||
| 170 | target/sparc/mmu_helper.c | 2 +- | ||
| 171 | target/sparc/translate.c | 799 +++++++-------------- | ||
| 172 | target/tricore/cpu.c | 6 + | ||
| 173 | target/tricore/helper.c | 2 +- | ||
| 174 | target/tricore/translate.c | 2 +- | ||
| 175 | target/xtensa/cpu.c | 6 + | ||
| 176 | target/xtensa/mmu_helper.c | 2 +- | ||
| 177 | accel/tcg/ldst_common.c.inc | 42 +- | ||
| 178 | target/cris/translate_v10.c.inc | 6 +- | ||
| 179 | .../tcg/insn_trans/trans_privileged.c.inc | 2 +- | ||
| 180 | tcg/loongarch64/tcg-target.c.inc | 2 +- | ||
| 181 | linux-user/aarch64/vdso-be.so | Bin 3216 -> 3224 bytes | ||
| 182 | linux-user/aarch64/vdso-le.so | Bin 3216 -> 3224 bytes | ||
| 183 | linux-user/aarch64/vdso.S | 4 + | ||
| 184 | tests/tcg/multiarch/gdbstub/prot-none.py | 2 +- | ||
| 185 | 97 files changed, 1064 insertions(+), 1191 deletions(-) | diff view generated by jsdifflib |
| 1 | This allows targets to declare that the helper requires a | 1 | The expected form is MMU_FOO_IDX, not MMU_IDX_FOO. |
|---|---|---|---|
| 2 | float_status pointer and instead of a generic void pointer. | 2 | Rename to match generic code. |
| 3 | 3 | ||
| 4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 6 | --- | 6 | --- |
| 7 | include/exec/helper-head.h.inc | 3 +++ | 7 | target/loongarch/cpu.h | 8 ++++---- |
| 8 | 1 file changed, 3 insertions(+) | 8 | target/loongarch/cpu.c | 2 +- |
| 9 | target/loongarch/cpu_helper.c | 4 ++-- | ||
| 10 | target/loongarch/tcg/translate.c | 2 +- | ||
| 11 | target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 2 +- | ||
| 12 | 5 files changed, 9 insertions(+), 9 deletions(-) | ||
| 9 | 13 | ||
| 10 | diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc | 14 | diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h |
| 11 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 12 | --- a/include/exec/helper-head.h.inc | 16 | --- a/target/loongarch/cpu.h |
| 13 | +++ b/include/exec/helper-head.h.inc | 17 | +++ b/target/loongarch/cpu.h |
| 14 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ struct LoongArchCPUClass { |
| 15 | #define dh_alias_ptr ptr | 19 | */ |
| 16 | #define dh_alias_cptr ptr | 20 | #define MMU_PLV_KERNEL 0 |
| 17 | #define dh_alias_env ptr | 21 | #define MMU_PLV_USER 3 |
| 18 | +#define dh_alias_fpst ptr | 22 | -#define MMU_IDX_KERNEL MMU_PLV_KERNEL |
| 19 | #define dh_alias_void void | 23 | -#define MMU_IDX_USER MMU_PLV_USER |
| 20 | #define dh_alias_noreturn noreturn | 24 | -#define MMU_IDX_DA 4 |
| 21 | #define dh_alias(t) glue(dh_alias_, t) | 25 | +#define MMU_KERNEL_IDX MMU_PLV_KERNEL |
| 22 | @@ -XXX,XX +XXX,XX @@ | 26 | +#define MMU_USER_IDX MMU_PLV_USER |
| 23 | #define dh_ctype_ptr void * | 27 | +#define MMU_DA_IDX 4 |
| 24 | #define dh_ctype_cptr const void * | 28 | |
| 25 | #define dh_ctype_env CPUArchState * | 29 | int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch); |
| 26 | +#define dh_ctype_fpst float_status * | 30 | static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) |
| 27 | #define dh_ctype_void void | 31 | { |
| 28 | #define dh_ctype_noreturn G_NORETURN void | 32 | #ifdef CONFIG_USER_ONLY |
| 29 | #define dh_ctype(t) dh_ctype_##t | 33 | - return MMU_IDX_USER; |
| 30 | @@ -XXX,XX +XXX,XX @@ | 34 | + return MMU_USER_IDX; |
| 31 | #define dh_typecode_f64 dh_typecode_i64 | 35 | #else |
| 32 | #define dh_typecode_cptr dh_typecode_ptr | 36 | return loongarch_cpu_mmu_index(env_cpu(env), ifetch); |
| 33 | #define dh_typecode_env dh_typecode_ptr | 37 | #endif |
| 34 | +#define dh_typecode_fpst dh_typecode_ptr | 38 | diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c |
| 35 | #define dh_typecode(t) dh_typecode_##t | 39 | index XXXXXXX..XXXXXXX 100644 |
| 36 | 40 | --- a/target/loongarch/cpu.c | |
| 37 | #define dh_callflag_i32 0 | 41 | +++ b/target/loongarch/cpu.c |
| 42 | @@ -XXX,XX +XXX,XX @@ int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) | ||
| 43 | if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { | ||
| 44 | return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); | ||
| 45 | } | ||
| 46 | - return MMU_IDX_DA; | ||
| 47 | + return MMU_DA_IDX; | ||
| 48 | } | ||
| 49 | |||
| 50 | static void loongarch_la464_initfn(Object *obj) | ||
| 51 | diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c | ||
| 52 | index XXXXXXX..XXXXXXX 100644 | ||
| 53 | --- a/target/loongarch/cpu_helper.c | ||
| 54 | +++ b/target/loongarch/cpu_helper.c | ||
| 55 | @@ -XXX,XX +XXX,XX @@ int get_physical_address(CPULoongArchState *env, hwaddr *physical, | ||
| 56 | int *prot, target_ulong address, | ||
| 57 | MMUAccessType access_type, int mmu_idx) | ||
| 58 | { | ||
| 59 | - int user_mode = mmu_idx == MMU_IDX_USER; | ||
| 60 | - int kernel_mode = mmu_idx == MMU_IDX_KERNEL; | ||
| 61 | + int user_mode = mmu_idx == MMU_USER_IDX; | ||
| 62 | + int kernel_mode = mmu_idx == MMU_KERNEL_IDX; | ||
| 63 | uint32_t plv, base_c, base_v; | ||
| 64 | int64_t addr_high; | ||
| 65 | uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA); | ||
| 66 | diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c | ||
| 67 | index XXXXXXX..XXXXXXX 100644 | ||
| 68 | --- a/target/loongarch/tcg/translate.c | ||
| 69 | +++ b/target/loongarch/tcg/translate.c | ||
| 70 | @@ -XXX,XX +XXX,XX @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase, | ||
| 71 | if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) { | ||
| 72 | ctx->mem_idx = ctx->plv; | ||
| 73 | } else { | ||
| 74 | - ctx->mem_idx = MMU_IDX_DA; | ||
| 75 | + ctx->mem_idx = MMU_DA_IDX; | ||
| 76 | } | ||
| 77 | |||
| 78 | /* Bound the number of insns to execute to those left on the page. */ | ||
| 79 | diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | ||
| 80 | index XXXXXXX..XXXXXXX 100644 | ||
| 81 | --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | ||
| 82 | +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | ||
| 83 | @@ -XXX,XX +XXX,XX @@ TRANS(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_d) | ||
| 84 | |||
| 85 | static void check_mmu_idx(DisasContext *ctx) | ||
| 86 | { | ||
| 87 | - if (ctx->mem_idx != MMU_IDX_DA) { | ||
| 88 | + if (ctx->mem_idx != MMU_DA_IDX) { | ||
| 89 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4); | ||
| 90 | ctx->base.is_jmp = DISAS_EXIT; | ||
| 91 | } | ||
| 38 | -- | 92 | -- |
| 39 | 2.43.0 | 93 | 2.34.1 |
| 40 | 94 | ||
| 41 | 95 | diff view generated by jsdifflib |
| 1 | From: Roman Artemev <roman.artemev@syntacore.com> | 1 | Because there are more call clobbered registers than |
|---|---|---|---|
| 2 | call saved registers, we begin with all registers as | ||
| 3 | call clobbered and then reset those that are saved. | ||
| 2 | 4 | ||
| 3 | On RISC-V to StoreStore barrier corresponds | 5 | This was missed when we introduced the LSX support. |
| 4 | `fence w, w` not `fence r, r` | ||
| 5 | 6 | ||
| 6 | Cc: qemu-stable@nongnu.org | 7 | Cc: qemu-stable@nongnu.org |
| 7 | Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions") | 8 | Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX") |
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2136 |
| 9 | Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com> | ||
| 10 | Signed-off-by: Roman Artemev <roman.artemev@syntacore.com> | ||
| 11 | Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com> | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 11 | Reviewed-by: Song Gao <gaosong@loongson.cn> | ||
| 12 | Message-Id: <20240201233414.500588-1-richard.henderson@linaro.org> | ||
| 13 | --- | 13 | --- |
| 14 | tcg/riscv/tcg-target.c.inc | 2 +- | 14 | tcg/loongarch64/tcg-target.c.inc | 2 +- |
| 15 | 1 file changed, 1 insertion(+), 1 deletion(-) | 15 | 1 file changed, 1 insertion(+), 1 deletion(-) |
| 16 | 16 | ||
| 17 | diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc | 17 | diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc |
| 18 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/tcg/riscv/tcg-target.c.inc | 19 | --- a/tcg/loongarch64/tcg-target.c.inc |
| 20 | +++ b/tcg/riscv/tcg-target.c.inc | 20 | +++ b/tcg/loongarch64/tcg-target.c.inc |
| 21 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) | 21 | @@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s) |
| 22 | insn |= 0x02100000; | 22 | tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; |
| 23 | } | 23 | tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; |
| 24 | if (a0 & TCG_MO_ST_ST) { | 24 | |
| 25 | - insn |= 0x02200000; | 25 | - tcg_target_call_clobber_regs = ALL_GENERAL_REGS; |
| 26 | + insn |= 0x01100000; | 26 | + tcg_target_call_clobber_regs = ALL_GENERAL_REGS | ALL_VECTOR_REGS; |
| 27 | } | 27 | tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); |
| 28 | tcg_out32(s, insn); | 28 | tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); |
| 29 | } | 29 | tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); |
| 30 | -- | 30 | -- |
| 31 | 2.43.0 | 31 | 2.34.1 | diff view generated by jsdifflib |
| 1 | When allocating new temps during tcg_optmize, do not re-use | 1 | Without this padding, an unwind through the signal handler |
|---|---|---|---|
| 2 | any EBB temps that were used within the TB. We do not have | 2 | will pick up the unwind info for the preceding syscall. |
| 3 | any idea what span of the TB in which the temp was live. | ||
| 4 | 3 | ||
| 5 | Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize, | 4 | This fixes gcc's 30_threads/thread/native_handle/cancel.cc. |
| 6 | as well as replacing the equivalent in plugin_gen_inject and | ||
| 7 | tcg_func_start. | ||
| 8 | 5 | ||
| 9 | Cc: qemu-stable@nongnu.org | 6 | Cc: qemu-stable@nongnu.org |
| 10 | Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported") | 7 | Fixes: ee95fae075c6 ("linux-user/aarch64: Add vdso") |
| 11 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711 | 8 | Resolves: https://linaro.atlassian.net/browse/GNU-974 |
| 12 | Reported-by: wannacu <wannacu2049@gmail.com> | ||
| 13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 14 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | 10 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
| 15 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 11 | Message-Id: <20240202034427.504686-1-richard.henderson@linaro.org> |
| 16 | --- | 12 | --- |
| 17 | include/tcg/tcg-temp-internal.h | 6 ++++++ | 13 | linux-user/aarch64/vdso-be.so | Bin 3216 -> 3224 bytes |
| 18 | accel/tcg/plugin-gen.c | 2 +- | 14 | linux-user/aarch64/vdso-le.so | Bin 3216 -> 3224 bytes |
| 19 | tcg/tcg.c | 5 ++++- | 15 | linux-user/aarch64/vdso.S | 4 ++++ |
| 20 | 3 files changed, 11 insertions(+), 2 deletions(-) | 16 | 3 files changed, 4 insertions(+) |
| 21 | 17 | ||
| 22 | diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h | 18 | diff --git a/linux-user/aarch64/vdso-be.so b/linux-user/aarch64/vdso-be.so |
| 19 | index XXXXXXX..XXXXXXX 100755 | ||
| 20 | GIT binary patch | ||
| 21 | delta 121 | ||
| 22 | zcmbOrIYV-SKI4pu2Kk&{7{Gw#%fuBAMC1c?^>~k}v|avdxNjSSLfftVb3bgJ!|2S& | ||
| 23 | z_-6A1CJrVZc?IUH8G;R$7#SF@Om<{a*v!K!&BXX-vIe^~TWO|cva$K*Om;sOMw`hy | ||
| 24 | ZxXl@VO#Z-a&zLdUfXALuXmSCM0s#EKC)of1 | ||
| 25 | |||
| 26 | delta 116 | ||
| 27 | zcmbOsIYDxQKI4Rm2Kk&H7{Gw#!^9O2L>8U?-5V_M@!kH(Sx4vJn|*ujLPgija~Pc& | ||
| 28 | z8DDIEz{J5c`3;N8W)W6tCdL<&4cM*OEF8_<v%@zRviq?xT1-B`ZO-^%@(*r%#)Qch | ||
| 29 | RJocPi5ThAdCO2?N002V6C;<Qf | ||
| 30 | |||
| 31 | diff --git a/linux-user/aarch64/vdso-le.so b/linux-user/aarch64/vdso-le.so | ||
| 32 | index XXXXXXX..XXXXXXX 100755 | ||
| 33 | GIT binary patch | ||
| 34 | delta 129 | ||
| 35 | zcmbOrIYV-S2IGv0n)#exSQx<I%fyAxMZTVBQ(04AP_*V|Vxp|@=@;x8zb9;-!)U|E | ||
| 36 | z_-6A>CVnO!c?IUH8G;R$7#SF@Om<{a*v!K!!o>JyvLd?^n`3BUW_royOm=q`Mw`hS | ||
| 37 | dxy>1WOn%92&zLb;lgFM@hy!9z%j7~Xc>tTxDQW-! | ||
| 38 | |||
| 39 | delta 108 | ||
| 40 | zcmbOsIYDxQ2IGW@n)#d`SQx<I!^DNpMK&+G&+g_}w9WI@dn@@euKVesZ-h6`VYFdn | ||
| 41 | ze6jf^6F<}BH!LcfMOa0c7+*}*WOrgKEO1Fl%G+GX?#{w!F?lDqIpc@PAGz%r6DAw- | ||
| 42 | M*fVlXF62=M06owo?*IS* | ||
| 43 | |||
| 44 | diff --git a/linux-user/aarch64/vdso.S b/linux-user/aarch64/vdso.S | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | 45 | index XXXXXXX..XXXXXXX 100644 |
| 24 | --- a/include/tcg/tcg-temp-internal.h | 46 | --- a/linux-user/aarch64/vdso.S |
| 25 | +++ b/include/tcg/tcg-temp-internal.h | 47 | +++ b/linux-user/aarch64/vdso.S |
| 26 | @@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void); | 48 | @@ -XXX,XX +XXX,XX @@ vdso_syscall __kernel_clock_getres, __NR_clock_getres |
| 27 | TCGv_ptr tcg_temp_ebb_new_ptr(void); | 49 | * For now, elide the unwind info for __kernel_rt_sigreturn and rely on |
| 28 | TCGv_i128 tcg_temp_ebb_new_i128(void); | 50 | * the libgcc fallback routine as we have always done. This requires |
| 29 | 51 | * that the code sequence used be exact. | |
| 30 | +/* Forget all freed EBB temps, so that new allocations produce new temps. */ | 52 | + * |
| 31 | +static inline void tcg_temp_ebb_reset_freed(TCGContext *s) | 53 | + * Add a nop as a spacer to ensure that unwind does not pick up the |
| 32 | +{ | 54 | + * unwind info from the preceding syscall. |
| 33 | + memset(s->free_temps, 0, sizeof(s->free_temps)); | 55 | */ |
| 34 | +} | 56 | + nop |
| 35 | + | 57 | __kernel_rt_sigreturn: |
| 36 | #endif /* TCG_TEMP_FREE_H */ | 58 | /* No BTI C insn here -- we arrive via RET. */ |
| 37 | diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c | 59 | mov x8, #__NR_rt_sigreturn |
| 38 | index XXXXXXX..XXXXXXX 100644 | ||
| 39 | --- a/accel/tcg/plugin-gen.c | ||
| 40 | +++ b/accel/tcg/plugin-gen.c | ||
| 41 | @@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb) | ||
| 42 | * that might be live within the existing opcode stream. | ||
| 43 | * The simplest solution is to release them all and create new. | ||
| 44 | */ | ||
| 45 | - memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps)); | ||
| 46 | + tcg_temp_ebb_reset_freed(tcg_ctx); | ||
| 47 | |||
| 48 | QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) { | ||
| 49 | switch (op->opc) { | ||
| 50 | diff --git a/tcg/tcg.c b/tcg/tcg.c | ||
| 51 | index XXXXXXX..XXXXXXX 100644 | ||
| 52 | --- a/tcg/tcg.c | ||
| 53 | +++ b/tcg/tcg.c | ||
| 54 | @@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s) | ||
| 55 | s->nb_temps = s->nb_globals; | ||
| 56 | |||
| 57 | /* No temps have been previously allocated for size or locality. */ | ||
| 58 | - memset(s->free_temps, 0, sizeof(s->free_temps)); | ||
| 59 | + tcg_temp_ebb_reset_freed(s); | ||
| 60 | |||
| 61 | /* No constant temps have been previously allocated. */ | ||
| 62 | for (int i = 0; i < TCG_TYPE_COUNT; ++i) { | ||
| 63 | @@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) | ||
| 64 | } | ||
| 65 | #endif | ||
| 66 | |||
| 67 | + /* Do not reuse any EBB that may be allocated within the TB. */ | ||
| 68 | + tcg_temp_ebb_reset_freed(s); | ||
| 69 | + | ||
| 70 | tcg_optimize(s); | ||
| 71 | |||
| 72 | reachable_code_pass(s); | ||
| 73 | -- | 60 | -- |
| 74 | 2.43.0 | 61 | 2.34.1 |
| 75 | 62 | ||
| 76 | 63 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 2 | 1 | ||
| 3 | Rather than manually copying each register, use | ||
| 4 | the libc memcpy(), which is well optimized nowadays. | ||
| 5 | |||
| 6 | Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
| 7 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 10 | Message-ID: <20241205205418.67613-1-philmd@linaro.org> | ||
| 11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 12 | --- | ||
| 13 | target/sparc/win_helper.c | 26 ++++++++------------------ | ||
| 14 | 1 file changed, 8 insertions(+), 18 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/sparc/win_helper.c | ||
| 19 | +++ b/target/sparc/win_helper.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ | ||
| 21 | #include "exec/helper-proto.h" | ||
| 22 | #include "trace.h" | ||
| 23 | |||
| 24 | -static inline void memcpy32(target_ulong *dst, const target_ulong *src) | ||
| 25 | -{ | ||
| 26 | - dst[0] = src[0]; | ||
| 27 | - dst[1] = src[1]; | ||
| 28 | - dst[2] = src[2]; | ||
| 29 | - dst[3] = src[3]; | ||
| 30 | - dst[4] = src[4]; | ||
| 31 | - dst[5] = src[5]; | ||
| 32 | - dst[6] = src[6]; | ||
| 33 | - dst[7] = src[7]; | ||
| 34 | -} | ||
| 35 | - | ||
| 36 | void cpu_set_cwp(CPUSPARCState *env, int new_cwp) | ||
| 37 | { | ||
| 38 | /* put the modified wrap registers at their proper location */ | ||
| 39 | if (env->cwp == env->nwindows - 1) { | ||
| 40 | - memcpy32(env->regbase, env->regbase + env->nwindows * 16); | ||
| 41 | + memcpy(env->regbase, env->regbase + env->nwindows * 16, | ||
| 42 | + sizeof(env->gregs)); | ||
| 43 | } | ||
| 44 | env->cwp = new_cwp; | ||
| 45 | |||
| 46 | /* put the wrap registers at their temporary location */ | ||
| 47 | if (new_cwp == env->nwindows - 1) { | ||
| 48 | - memcpy32(env->regbase + env->nwindows * 16, env->regbase); | ||
| 49 | + memcpy(env->regbase + env->nwindows * 16, env->regbase, | ||
| 50 | + sizeof(env->gregs)); | ||
| 51 | } | ||
| 52 | env->regwptr = env->regbase + (new_cwp * 16); | ||
| 53 | } | ||
| 54 | @@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl) | ||
| 55 | dst = get_gl_gregset(env, env->gl); | ||
| 56 | |||
| 57 | if (src != dst) { | ||
| 58 | - memcpy32(dst, env->gregs); | ||
| 59 | - memcpy32(env->gregs, src); | ||
| 60 | + memcpy(dst, env->gregs, sizeof(env->gregs)); | ||
| 61 | + memcpy(env->gregs, src, sizeof(env->gregs)); | ||
| 62 | } | ||
| 63 | } | ||
| 64 | |||
| 65 | @@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate) | ||
| 66 | /* Switch global register bank */ | ||
| 67 | src = get_gregset(env, new_pstate_regs); | ||
| 68 | dst = get_gregset(env, pstate_regs); | ||
| 69 | - memcpy32(dst, env->gregs); | ||
| 70 | - memcpy32(env->gregs, src); | ||
| 71 | + memcpy(dst, env->gregs, sizeof(env->gregs)); | ||
| 72 | + memcpy(env->gregs, src, sizeof(env->gregs)); | ||
| 73 | } else { | ||
| 74 | trace_win_helper_no_switch_pstate(new_pstate_regs); | ||
| 75 | } | ||
| 76 | -- | ||
| 77 | 2.43.0 | ||
| 78 | |||
| 79 | diff view generated by jsdifflib |