[PULL 0/4] tcg patch queue
[PATCH v2 00/48] tcg patch queue
1
Pretty small still, but there are two patches that ought
1
The following changes since commit 50e7a40af372ee5931c99ef7390f5d3d6fbf6ec4:
2
to get backported to stable, so no point in delaying.
3
2
4
r~
3
Merge tag 'pull-target-arm-20230824' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-08-24 10:08:33 -0400)
5
6
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
7
8
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
9
4
10
are available in the Git repository at:
5
are available in the Git repository at:
11
6
12
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230823-2
13
8
14
for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:
9
for you to fetch changes up to 4daad8d9d6b9d426beb8ce505d2164ba36ea3168:
15
10
16
target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)
11
tcg: spelling fixes (2023-08-24 11:22:42 -0700)
17
12
18
----------------------------------------------------------------
13
----------------------------------------------------------------
19
tcg: Reset free_temps before tcg_optimize
14
accel/*: Widen pc/saved_insn for *_sw_breakpoint
20
tcg/riscv: Fix StoreStore barrier generation
15
accel/tcg: Replace remaining target_ulong in system-mode accel
21
include/exec: Introduce fpst alias in helper-head.h.inc
16
tcg: spelling fixes
22
target/sparc: Use memcpy() and remove memcpy32()
17
tcg: Document bswap, hswap, wswap byte patterns
18
tcg: Introduce negsetcond opcodes
19
tcg: Fold deposit with zero to and
20
tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32
21
tcg/i386: Drop BYTEH deposits for 64-bit
22
tcg/i386: Allow immediate as input to deposit
23
target/*: Use tcg_gen_negsetcond_*
23
24
24
----------------------------------------------------------------
25
----------------------------------------------------------------
25
Philippe Mathieu-Daudé (1):
26
Anton Johansson (9):
26
target/sparc: Use memcpy() and remove memcpy32()
27
accel/kvm: Widen pc/saved_insn for kvm_sw_breakpoint
28
accel/hvf: Widen pc/saved_insn for hvf_sw_breakpoint
29
sysemu/kvm: Use vaddr for kvm_arch_[insert|remove]_hw_breakpoint
30
sysemu/hvf: Use vaddr for hvf_arch_[insert|remove]_hw_breakpoint
31
include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*()
32
include/exec: typedef abi_ptr to vaddr in softmmu
33
include/exec: Widen tlb_hit/tlb_hit_page()
34
accel/tcg: Widen address arg in tlb_compare_set()
35
accel/tcg: Update run_on_cpu_data static assert
27
36
28
Richard Henderson (2):
37
Mark Cave-Ayland (1):
29
tcg: Reset free_temps before tcg_optimize
38
docs/devel/tcg-ops: fix missing newlines in "Host vector operations"
30
include/exec: Introduce fpst alias in helper-head.h.inc
31
39
32
Roman Artemev (1):
40
Michael Tokarev (1):
33
tcg/riscv: Fix StoreStore barrier generation
41
tcg: spelling fixes
34
42
35
include/tcg/tcg-temp-internal.h | 6 ++++++
43
Philippe Mathieu-Daudé (9):
36
accel/tcg/plugin-gen.c | 2 +-
44
docs/devel/tcg-ops: Bury mentions of trunc_shr_i64_i32()
37
target/sparc/win_helper.c | 26 ++++++++------------------
45
tcg/tcg-op: Document bswap16_i32() byte pattern
38
tcg/tcg.c | 5 ++++-
46
tcg/tcg-op: Document bswap16_i64() byte pattern
39
include/exec/helper-head.h.inc | 3 +++
47
tcg/tcg-op: Document bswap32_i32() byte pattern
40
tcg/riscv/tcg-target.c.inc | 2 +-
48
tcg/tcg-op: Document bswap32_i64() byte pattern
41
6 files changed, 23 insertions(+), 21 deletions(-)
49
tcg/tcg-op: Document bswap64_i64() byte pattern
50
tcg/tcg-op: Document hswap_i32/64() byte pattern
51
tcg/tcg-op: Document wswap_i64() byte pattern
52
target/cris: Fix a typo in gen_swapr()
42
53
54
Richard Henderson (28):
55
target/m68k: Use tcg_gen_deposit_i32 in gen_partset_reg
56
tcg/i386: Drop BYTEH deposits for 64-bit
57
tcg: Fold deposit with zero to and
58
tcg/i386: Allow immediate as input to deposit_*
59
tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32
60
tcg: Introduce negsetcond opcodes
61
tcg: Use tcg_gen_negsetcond_*
62
target/alpha: Use tcg_gen_movcond_i64 in gen_fold_mzero
63
target/arm: Use tcg_gen_negsetcond_*
64
target/m68k: Use tcg_gen_negsetcond_*
65
target/openrisc: Use tcg_gen_negsetcond_*
66
target/ppc: Use tcg_gen_negsetcond_*
67
target/sparc: Use tcg_gen_movcond_i64 in gen_edge
68
target/tricore: Replace gen_cond_w with tcg_gen_negsetcond_tl
69
tcg/ppc: Implement negsetcond_*
70
tcg/ppc: Use the Set Boolean Extension
71
tcg/aarch64: Implement negsetcond_*
72
tcg/arm: Implement negsetcond_i32
73
tcg/riscv: Implement negsetcond_*
74
tcg/s390x: Implement negsetcond_*
75
tcg/sparc64: Implement negsetcond_*
76
tcg/i386: Merge tcg_out_brcond{32,64}
77
tcg/i386: Merge tcg_out_setcond{32,64}
78
tcg/i386: Merge tcg_out_movcond{32,64}
79
tcg/i386: Use CMP+SBB in tcg_out_setcond
80
tcg/i386: Clear dest first in tcg_out_setcond if possible
81
tcg/i386: Use shift in tcg_out_setcond
82
tcg/i386: Implement negsetcond_*
83
84
docs/devel/tcg-ops.rst | 15 +-
85
accel/tcg/atomic_template.h | 16 +-
86
include/exec/cpu-all.h | 4 +-
87
include/exec/cpu_ldst.h | 28 +--
88
include/sysemu/hvf.h | 12 +-
89
include/sysemu/kvm.h | 12 +-
90
include/tcg/tcg-op-common.h | 4 +
91
include/tcg/tcg-op.h | 2 +
92
include/tcg/tcg-opc.h | 6 +-
93
include/tcg/tcg.h | 4 +-
94
tcg/aarch64/tcg-target.h | 5 +-
95
tcg/arm/tcg-target.h | 1 +
96
tcg/i386/tcg-target-con-set.h | 2 +-
97
tcg/i386/tcg-target-con-str.h | 1 -
98
tcg/i386/tcg-target.h | 9 +-
99
tcg/loongarch64/tcg-target.h | 6 +-
100
tcg/mips/tcg-target.h | 5 +-
101
tcg/ppc/tcg-target.h | 5 +-
102
tcg/riscv/tcg-target.h | 5 +-
103
tcg/s390x/tcg-target.h | 5 +-
104
tcg/sparc64/tcg-target.h | 5 +-
105
tcg/tci/tcg-target.h | 5 +-
106
accel/hvf/hvf-accel-ops.c | 4 +-
107
accel/hvf/hvf-all.c | 2 +-
108
accel/kvm/kvm-all.c | 3 +-
109
accel/tcg/cputlb.c | 17 +-
110
target/alpha/translate.c | 7 +-
111
target/arm/hvf/hvf.c | 4 +-
112
target/arm/kvm64.c | 6 +-
113
target/arm/tcg/translate-a64.c | 22 +--
114
target/arm/tcg/translate.c | 12 +-
115
target/cris/translate.c | 20 +-
116
target/i386/hvf/hvf.c | 4 +-
117
target/i386/kvm/kvm.c | 8 +-
118
target/m68k/translate.c | 35 ++--
119
target/openrisc/translate.c | 6 +-
120
target/ppc/kvm.c | 13 +-
121
target/riscv/vector_helper.c | 2 +-
122
target/rx/op_helper.c | 6 +-
123
target/s390x/kvm/kvm.c | 6 +-
124
target/sparc/translate.c | 17 +-
125
target/tricore/translate.c | 16 +-
126
tcg/optimize.c | 78 +++++++-
127
tcg/tcg-op-gvec.c | 6 +-
128
tcg/tcg-op.c | 151 ++++++++++++---
129
tcg/tcg.c | 9 +-
130
target/ppc/translate/fixedpoint-impl.c.inc | 6 +-
131
target/ppc/translate/vmx-impl.c.inc | 8 +-
132
tcg/aarch64/tcg-target.c.inc | 14 +-
133
tcg/arm/tcg-target.c.inc | 19 +-
134
tcg/i386/tcg-target.c.inc | 291 ++++++++++++++++++-----------
135
tcg/ppc/tcg-target.c.inc | 149 ++++++++++-----
136
tcg/riscv/tcg-target.c.inc | 49 ++++-
137
tcg/s390x/tcg-target.c.inc | 78 +++++---
138
tcg/sparc64/tcg-target.c.inc | 40 +++-
139
55 files changed, 832 insertions(+), 433 deletions(-)
140
diff view generated by jsdifflib
[PULL 1/4] tcg: Reset free_temps before tcg_optimize
Deleted patch
1
When allocating new temps during tcg_optmize, do not re-use
2
any EBB temps that were used within the TB. We do not have
3
any idea what span of the TB in which the temp was live.
4
1
5
Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
6
as well as replacing the equivalent in plugin_gen_inject and
7
tcg_func_start.
8
9
Cc: qemu-stable@nongnu.org
10
Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
11
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
12
Reported-by: wannacu <wannacu2049@gmail.com>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
---
17
include/tcg/tcg-temp-internal.h | 6 ++++++
18
accel/tcg/plugin-gen.c | 2 +-
19
tcg/tcg.c | 5 ++++-
20
3 files changed, 11 insertions(+), 2 deletions(-)
21
22
diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/include/tcg/tcg-temp-internal.h
25
+++ b/include/tcg/tcg-temp-internal.h
26
@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
27
TCGv_ptr tcg_temp_ebb_new_ptr(void);
28
TCGv_i128 tcg_temp_ebb_new_i128(void);
29
30
+/* Forget all freed EBB temps, so that new allocations produce new temps. */
31
+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
32
+{
33
+ memset(s->free_temps, 0, sizeof(s->free_temps));
34
+}
35
+
36
#endif /* TCG_TEMP_FREE_H */
37
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/accel/tcg/plugin-gen.c
40
+++ b/accel/tcg/plugin-gen.c
41
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
42
* that might be live within the existing opcode stream.
43
* The simplest solution is to release them all and create new.
44
*/
45
- memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
46
+ tcg_temp_ebb_reset_freed(tcg_ctx);
47
48
QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
49
switch (op->opc) {
50
diff --git a/tcg/tcg.c b/tcg/tcg.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/tcg/tcg.c
53
+++ b/tcg/tcg.c
54
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
55
s->nb_temps = s->nb_globals;
56
57
/* No temps have been previously allocated for size or locality. */
58
- memset(s->free_temps, 0, sizeof(s->free_temps));
59
+ tcg_temp_ebb_reset_freed(s);
60
61
/* No constant temps have been previously allocated. */
62
for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
63
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
64
}
65
#endif
66
67
+ /* Do not reuse any EBB that may be allocated within the TB. */
68
+ tcg_temp_ebb_reset_freed(s);
69
+
70
tcg_optimize(s);
71
72
reachable_code_pass(s);
73
--
74
2.43.0
75
76
diff view generated by jsdifflib
[PULL 2/4] tcg/riscv: Fix StoreStore barrier generation
Deleted patch
1
From: Roman Artemev <roman.artemev@syntacore.com>
2
1
3
On RISC-V to StoreStore barrier corresponds
4
`fence w, w` not `fence r, r`
5
6
Cc: qemu-stable@nongnu.org
7
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
10
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
11
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
14
tcg/riscv/tcg-target.c.inc | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
18
index XXXXXXX..XXXXXXX 100644
19
--- a/tcg/riscv/tcg-target.c.inc
20
+++ b/tcg/riscv/tcg-target.c.inc
21
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
22
insn |= 0x02100000;
23
}
24
if (a0 & TCG_MO_ST_ST) {
25
- insn |= 0x02200000;
26
+ insn |= 0x01100000;
27
}
28
tcg_out32(s, insn);
29
}
30
--
31
2.43.0
diff view generated by jsdifflib
[PULL 3/4] include/exec: Introduce fpst alias in helper-head.h.inc
Deleted patch
1
This allows targets to declare that the helper requires a
2
float_status pointer and instead of a generic void pointer.
3
1
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
include/exec/helper-head.h.inc | 3 +++
8
1 file changed, 3 insertions(+)
9
10
diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/include/exec/helper-head.h.inc
13
+++ b/include/exec/helper-head.h.inc
14
@@ -XXX,XX +XXX,XX @@
15
#define dh_alias_ptr ptr
16
#define dh_alias_cptr ptr
17
#define dh_alias_env ptr
18
+#define dh_alias_fpst ptr
19
#define dh_alias_void void
20
#define dh_alias_noreturn noreturn
21
#define dh_alias(t) glue(dh_alias_, t)
22
@@ -XXX,XX +XXX,XX @@
23
#define dh_ctype_ptr void *
24
#define dh_ctype_cptr const void *
25
#define dh_ctype_env CPUArchState *
26
+#define dh_ctype_fpst float_status *
27
#define dh_ctype_void void
28
#define dh_ctype_noreturn G_NORETURN void
29
#define dh_ctype(t) dh_ctype_##t
30
@@ -XXX,XX +XXX,XX @@
31
#define dh_typecode_f64 dh_typecode_i64
32
#define dh_typecode_cptr dh_typecode_ptr
33
#define dh_typecode_env dh_typecode_ptr
34
+#define dh_typecode_fpst dh_typecode_ptr
35
#define dh_typecode(t) dh_typecode_##t
36
37
#define dh_callflag_i32 0
38
--
39
2.43.0
40
41
diff view generated by jsdifflib
[PULL 4/4] target/sparc: Use memcpy() and remove memcpy32()
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Rather than manually copying each register, use
4
the libc memcpy(), which is well optimized nowadays.
5
6
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-ID: <20241205205418.67613-1-philmd@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
13
target/sparc/win_helper.c | 26 ++++++++------------------
14
1 file changed, 8 insertions(+), 18 deletions(-)
15
16
diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/sparc/win_helper.c
19
+++ b/target/sparc/win_helper.c
20
@@ -XXX,XX +XXX,XX @@
21
#include "exec/helper-proto.h"
22
#include "trace.h"
23
24
-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
25
-{
26
- dst[0] = src[0];
27
- dst[1] = src[1];
28
- dst[2] = src[2];
29
- dst[3] = src[3];
30
- dst[4] = src[4];
31
- dst[5] = src[5];
32
- dst[6] = src[6];
33
- dst[7] = src[7];
34
-}
35
-
36
void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
37
{
38
/* put the modified wrap registers at their proper location */
39
if (env->cwp == env->nwindows - 1) {
40
- memcpy32(env->regbase, env->regbase + env->nwindows * 16);
41
+ memcpy(env->regbase, env->regbase + env->nwindows * 16,
42
+ sizeof(env->gregs));
43
}
44
env->cwp = new_cwp;
45
46
/* put the wrap registers at their temporary location */
47
if (new_cwp == env->nwindows - 1) {
48
- memcpy32(env->regbase + env->nwindows * 16, env->regbase);
49
+ memcpy(env->regbase + env->nwindows * 16, env->regbase,
50
+ sizeof(env->gregs));
51
}
52
env->regwptr = env->regbase + (new_cwp * 16);
53
}
54
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
55
dst = get_gl_gregset(env, env->gl);
56
57
if (src != dst) {
58
- memcpy32(dst, env->gregs);
59
- memcpy32(env->gregs, src);
60
+ memcpy(dst, env->gregs, sizeof(env->gregs));
61
+ memcpy(env->gregs, src, sizeof(env->gregs));
62
}
63
}
64
65
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
66
/* Switch global register bank */
67
src = get_gregset(env, new_pstate_regs);
68
dst = get_gregset(env, pstate_regs);
69
- memcpy32(dst, env->gregs);
70
- memcpy32(env->gregs, src);
71
+ memcpy(dst, env->gregs, sizeof(env->gregs));
72
+ memcpy(env->gregs, src, sizeof(env->gregs));
73
} else {
74
trace_win_helper_no_switch_pstate(new_pstate_regs);
75
}
76
--
77
2.43.0
78
79
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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