[PULL 0/4] tcg patch queue
[PULL v2 00/74] tcg patch queue
1
Pretty small still, but there are two patches that ought
1
v2: Drop a few patches, which showed regressions in CI
2
to get backported to stable, so no point in delaying.
2
for jobs that are not run for forks. :-/
3
3
4
4
r~
5
r~
5
6
6
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
7
7
8
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
8
The following changes since commit f9d58e0ca53b3f470b84725a7b5e47fcf446a2ea:
9
10
Merge tag 'pull-9p-20230516' of https://github.com/cschoenebeck/qemu into staging (2023-05-16 10:21:44 -0700)
9
11
10
are available in the Git repository at:
12
are available in the Git repository at:
11
13
12
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212
14
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230516-2
13
15
14
for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:
16
for you to fetch changes up to 44fe8f47fce3bdc8dcf49e3f001519a375ecc88a:
15
17
16
target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)
18
tcg: Split out exec/user/guest-base.h (2023-05-16 16:31:05 -0700)
17
19
18
----------------------------------------------------------------
20
----------------------------------------------------------------
19
tcg: Reset free_temps before tcg_optimize
21
tcg/i386: Fix tcg_out_addi_ptr for win64
20
tcg/riscv: Fix StoreStore barrier generation
22
tcg: Implement atomicity for TCGv_i128
21
include/exec: Introduce fpst alias in helper-head.h.inc
23
tcg: First quarter of cleanups for building tcg once
22
target/sparc: Use memcpy() and remove memcpy32()
23
24
24
----------------------------------------------------------------
25
----------------------------------------------------------------
25
Philippe Mathieu-Daudé (1):
26
Richard Henderson (74):
26
target/sparc: Use memcpy() and remove memcpy32()
27
tcg/i386: Set P_REXW in tcg_out_addi_ptr
28
include/exec/memop: Add MO_ATOM_*
29
accel/tcg: Honor atomicity of loads
30
accel/tcg: Honor atomicity of stores
31
tcg: Unify helper_{be,le}_{ld,st}*
32
accel/tcg: Implement helper_{ld,st}*_mmu for user-only
33
tcg/tci: Use helper_{ld,st}*_mmu for user-only
34
tcg: Add 128-bit guest memory primitives
35
meson: Detect atomic128 support with optimization
36
tcg/i386: Add have_atomic16
37
tcg/aarch64: Detect have_lse, have_lse2 for linux
38
tcg/aarch64: Detect have_lse, have_lse2 for darwin
39
tcg/i386: Use full load/store helpers in user-only mode
40
tcg/aarch64: Use full load/store helpers in user-only mode
41
tcg/ppc: Use full load/store helpers in user-only mode
42
tcg/loongarch64: Use full load/store helpers in user-only mode
43
tcg/riscv: Use full load/store helpers in user-only mode
44
tcg/arm: Adjust constraints on qemu_ld/st
45
tcg/arm: Use full load/store helpers in user-only mode
46
tcg/mips: Use full load/store helpers in user-only mode
47
tcg/s390x: Use full load/store helpers in user-only mode
48
tcg/sparc64: Allocate %g2 as a third temporary
49
tcg/sparc64: Rename tcg_out_movi_imm13 to tcg_out_movi_s13
50
target/sparc64: Remove tcg_out_movi_s13 case from tcg_out_movi_imm32
51
tcg/sparc64: Rename tcg_out_movi_imm32 to tcg_out_movi_u32
52
tcg/sparc64: Split out tcg_out_movi_s32
53
tcg/sparc64: Use standard slow path for softmmu
54
accel/tcg: Remove helper_unaligned_{ld,st}
55
tcg/loongarch64: Check the host supports unaligned accesses
56
tcg/loongarch64: Support softmmu unaligned accesses
57
tcg/riscv: Support softmmu unaligned accesses
58
tcg: Introduce tcg_target_has_memory_bswap
59
tcg: Add INDEX_op_qemu_{ld,st}_i128
60
tcg: Introduce tcg_out_movext3
61
tcg: Merge tcg_out_helper_load_regs into caller
62
tcg: Support TCG_TYPE_I128 in tcg_out_{ld,st}_helper_{args,ret}
63
tcg: Introduce atom_and_align_for_opc
64
tcg/i386: Use atom_and_align_for_opc
65
tcg/aarch64: Use atom_and_align_for_opc
66
tcg/arm: Use atom_and_align_for_opc
67
tcg/loongarch64: Use atom_and_align_for_opc
68
tcg/mips: Use atom_and_align_for_opc
69
tcg/ppc: Use atom_and_align_for_opc
70
tcg/riscv: Use atom_and_align_for_opc
71
tcg/s390x: Use atom_and_align_for_opc
72
tcg/sparc64: Use atom_and_align_for_opc
73
tcg: Split out memory ops to tcg-op-ldst.c
74
tcg: Widen gen_insn_data to uint64_t
75
accel/tcg: Widen tcg-ldst.h addresses to uint64_t
76
tcg: Widen helper_{ld,st}_i128 addresses to uint64_t
77
tcg: Widen helper_atomic_* addresses to uint64_t
78
tcg: Widen tcg_gen_code pc_start argument to uint64_t
79
accel/tcg: Merge gen_mem_wrapped with plugin_gen_empty_mem_callback
80
accel/tcg: Merge do_gen_mem_cb into caller
81
tcg: Reduce copies for plugin_gen_mem_callbacks
82
accel/tcg: Widen plugin_gen_empty_mem_callback to i64
83
tcg: Add addr_type to TCGContext
84
tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_*
85
tcg: Remove TCGv from tcg_gen_atomic_*
86
tcg: Split INDEX_op_qemu_{ld,st}* for guest address size
87
tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong
88
tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32
89
tcg/i386: Conditionalize tcg_out_extu_i32_i64
90
tcg/i386: Adjust type of tlb_mask
91
tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TL
92
tcg/arm: Remove TARGET_LONG_BITS
93
tcg/aarch64: Remove USE_GUEST_BASE
94
tcg/aarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
95
tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
96
tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TL
97
tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL
98
tcg: Add page_bits and page_mask to TCGContext
99
tcg: Add tlb_dyn_max_bits to TCGContext
100
tcg: Split out exec/user/guest-base.h
27
101
28
Richard Henderson (2):
102
docs/devel/loads-stores.rst | 36 +-
29
tcg: Reset free_temps before tcg_optimize
103
docs/devel/tcg-ops.rst | 11 +-
30
include/exec: Introduce fpst alias in helper-head.h.inc
104
meson.build | 52 +-
31
105
accel/tcg/tcg-runtime.h | 49 +-
32
Roman Artemev (1):
106
include/exec/cpu-all.h | 5 +-
33
tcg/riscv: Fix StoreStore barrier generation
107
include/exec/memop.h | 37 ++
34
108
include/exec/plugin-gen.h | 4 +-
35
include/tcg/tcg-temp-internal.h | 6 ++++++
109
include/exec/user/guest-base.h | 12 +
36
accel/tcg/plugin-gen.c | 2 +-
110
include/qemu/cpuid.h | 18 +
37
target/sparc/win_helper.c | 26 ++++++++------------------
111
include/tcg/tcg-ldst.h | 72 +--
38
tcg/tcg.c | 5 ++++-
112
include/tcg/tcg-op.h | 273 ++++++---
39
include/exec/helper-head.h.inc | 3 +++
113
include/tcg/tcg-opc.h | 41 +-
40
tcg/riscv/tcg-target.c.inc | 2 +-
114
include/tcg/tcg.h | 39 +-
41
6 files changed, 23 insertions(+), 21 deletions(-)
115
tcg/aarch64/tcg-target.h | 6 +-
42
116
tcg/arm/tcg-target-con-set.h | 16 +-
117
tcg/arm/tcg-target-con-str.h | 5 +-
118
tcg/arm/tcg-target.h | 3 +-
119
tcg/i386/tcg-target.h | 12 +-
120
tcg/loongarch64/tcg-target.h | 3 +-
121
tcg/mips/tcg-target.h | 4 +-
122
tcg/ppc/tcg-target.h | 3 +-
123
tcg/riscv/tcg-target.h | 4 +-
124
tcg/s390x/tcg-target.h | 4 +-
125
tcg/sparc64/tcg-target-con-set.h | 2 -
126
tcg/sparc64/tcg-target-con-str.h | 1 -
127
tcg/sparc64/tcg-target.h | 4 +-
128
tcg/tcg-internal.h | 2 +
129
tcg/tci/tcg-target.h | 4 +-
130
accel/tcg/cputlb.c | 839 ++++++++++++++++---------
131
accel/tcg/plugin-gen.c | 68 +-
132
accel/tcg/translate-all.c | 35 +-
133
accel/tcg/user-exec.c | 488 ++++++++++-----
134
tcg/optimize.c | 19 +-
135
tcg/tcg-op-ldst.c | 1234 +++++++++++++++++++++++++++++++++++++
136
tcg/tcg-op.c | 864 --------------------------
137
tcg/tcg.c | 631 +++++++++++++++----
138
tcg/tci.c | 243 +++-----
139
accel/tcg/atomic_common.c.inc | 14 +-
140
accel/tcg/ldst_atomicity.c.inc | 1262 ++++++++++++++++++++++++++++++++++++++
141
tcg/aarch64/tcg-target.c.inc | 207 +++----
142
tcg/arm/tcg-target.c.inc | 246 +++-----
143
tcg/i386/tcg-target.c.inc | 240 ++++----
144
tcg/loongarch64/tcg-target.c.inc | 123 ++--
145
tcg/mips/tcg-target.c.inc | 216 +++----
146
tcg/ppc/tcg-target.c.inc | 189 +++---
147
tcg/riscv/tcg-target.c.inc | 161 ++---
148
tcg/s390x/tcg-target.c.inc | 104 +---
149
tcg/sparc64/tcg-target.c.inc | 731 ++++++++--------------
150
tcg/tci/tcg-target.c.inc | 58 +-
151
tcg/meson.build | 1 +
152
50 files changed, 5345 insertions(+), 3350 deletions(-)
153
create mode 100644 include/exec/user/guest-base.h
154
create mode 100644 tcg/tcg-op-ldst.c
155
create mode 100644 accel/tcg/ldst_atomicity.c.inc
diff view generated by jsdifflib
[PULL 1/4] tcg: Reset free_temps before tcg_optimize
Deleted patch
1
When allocating new temps during tcg_optmize, do not re-use
2
any EBB temps that were used within the TB. We do not have
3
any idea what span of the TB in which the temp was live.
4
1
5
Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
6
as well as replacing the equivalent in plugin_gen_inject and
7
tcg_func_start.
8
9
Cc: qemu-stable@nongnu.org
10
Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
11
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
12
Reported-by: wannacu <wannacu2049@gmail.com>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
---
17
include/tcg/tcg-temp-internal.h | 6 ++++++
18
accel/tcg/plugin-gen.c | 2 +-
19
tcg/tcg.c | 5 ++++-
20
3 files changed, 11 insertions(+), 2 deletions(-)
21
22
diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/include/tcg/tcg-temp-internal.h
25
+++ b/include/tcg/tcg-temp-internal.h
26
@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
27
TCGv_ptr tcg_temp_ebb_new_ptr(void);
28
TCGv_i128 tcg_temp_ebb_new_i128(void);
29
30
+/* Forget all freed EBB temps, so that new allocations produce new temps. */
31
+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
32
+{
33
+ memset(s->free_temps, 0, sizeof(s->free_temps));
34
+}
35
+
36
#endif /* TCG_TEMP_FREE_H */
37
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/accel/tcg/plugin-gen.c
40
+++ b/accel/tcg/plugin-gen.c
41
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
42
* that might be live within the existing opcode stream.
43
* The simplest solution is to release them all and create new.
44
*/
45
- memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
46
+ tcg_temp_ebb_reset_freed(tcg_ctx);
47
48
QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
49
switch (op->opc) {
50
diff --git a/tcg/tcg.c b/tcg/tcg.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/tcg/tcg.c
53
+++ b/tcg/tcg.c
54
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
55
s->nb_temps = s->nb_globals;
56
57
/* No temps have been previously allocated for size or locality. */
58
- memset(s->free_temps, 0, sizeof(s->free_temps));
59
+ tcg_temp_ebb_reset_freed(s);
60
61
/* No constant temps have been previously allocated. */
62
for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
63
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
64
}
65
#endif
66
67
+ /* Do not reuse any EBB that may be allocated within the TB. */
68
+ tcg_temp_ebb_reset_freed(s);
69
+
70
tcg_optimize(s);
71
72
reachable_code_pass(s);
73
--
74
2.43.0
75
76
diff view generated by jsdifflib
[PULL 2/4] tcg/riscv: Fix StoreStore barrier generation
Deleted patch
1
From: Roman Artemev <roman.artemev@syntacore.com>
2
1
3
On RISC-V to StoreStore barrier corresponds
4
`fence w, w` not `fence r, r`
5
6
Cc: qemu-stable@nongnu.org
7
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
10
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
11
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
14
tcg/riscv/tcg-target.c.inc | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
18
index XXXXXXX..XXXXXXX 100644
19
--- a/tcg/riscv/tcg-target.c.inc
20
+++ b/tcg/riscv/tcg-target.c.inc
21
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
22
insn |= 0x02100000;
23
}
24
if (a0 & TCG_MO_ST_ST) {
25
- insn |= 0x02200000;
26
+ insn |= 0x01100000;
27
}
28
tcg_out32(s, insn);
29
}
30
--
31
2.43.0
diff view generated by jsdifflib
[PULL 3/4] include/exec: Introduce fpst alias in helper-head.h.inc
Deleted patch
1
This allows targets to declare that the helper requires a
2
float_status pointer and instead of a generic void pointer.
3
1
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
include/exec/helper-head.h.inc | 3 +++
8
1 file changed, 3 insertions(+)
9
10
diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/include/exec/helper-head.h.inc
13
+++ b/include/exec/helper-head.h.inc
14
@@ -XXX,XX +XXX,XX @@
15
#define dh_alias_ptr ptr
16
#define dh_alias_cptr ptr
17
#define dh_alias_env ptr
18
+#define dh_alias_fpst ptr
19
#define dh_alias_void void
20
#define dh_alias_noreturn noreturn
21
#define dh_alias(t) glue(dh_alias_, t)
22
@@ -XXX,XX +XXX,XX @@
23
#define dh_ctype_ptr void *
24
#define dh_ctype_cptr const void *
25
#define dh_ctype_env CPUArchState *
26
+#define dh_ctype_fpst float_status *
27
#define dh_ctype_void void
28
#define dh_ctype_noreturn G_NORETURN void
29
#define dh_ctype(t) dh_ctype_##t
30
@@ -XXX,XX +XXX,XX @@
31
#define dh_typecode_f64 dh_typecode_i64
32
#define dh_typecode_cptr dh_typecode_ptr
33
#define dh_typecode_env dh_typecode_ptr
34
+#define dh_typecode_fpst dh_typecode_ptr
35
#define dh_typecode(t) dh_typecode_##t
36
37
#define dh_callflag_i32 0
38
--
39
2.43.0
40
41
diff view generated by jsdifflib
[PULL 4/4] target/sparc: Use memcpy() and remove memcpy32()
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Rather than manually copying each register, use
4
the libc memcpy(), which is well optimized nowadays.
5
6
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-ID: <20241205205418.67613-1-philmd@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
13
target/sparc/win_helper.c | 26 ++++++++------------------
14
1 file changed, 8 insertions(+), 18 deletions(-)
15
16
diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/sparc/win_helper.c
19
+++ b/target/sparc/win_helper.c
20
@@ -XXX,XX +XXX,XX @@
21
#include "exec/helper-proto.h"
22
#include "trace.h"
23
24
-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
25
-{
26
- dst[0] = src[0];
27
- dst[1] = src[1];
28
- dst[2] = src[2];
29
- dst[3] = src[3];
30
- dst[4] = src[4];
31
- dst[5] = src[5];
32
- dst[6] = src[6];
33
- dst[7] = src[7];
34
-}
35
-
36
void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
37
{
38
/* put the modified wrap registers at their proper location */
39
if (env->cwp == env->nwindows - 1) {
40
- memcpy32(env->regbase, env->regbase + env->nwindows * 16);
41
+ memcpy(env->regbase, env->regbase + env->nwindows * 16,
42
+ sizeof(env->gregs));
43
}
44
env->cwp = new_cwp;
45
46
/* put the wrap registers at their temporary location */
47
if (new_cwp == env->nwindows - 1) {
48
- memcpy32(env->regbase + env->nwindows * 16, env->regbase);
49
+ memcpy(env->regbase + env->nwindows * 16, env->regbase,
50
+ sizeof(env->gregs));
51
}
52
env->regwptr = env->regbase + (new_cwp * 16);
53
}
54
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
55
dst = get_gl_gregset(env, env->gl);
56
57
if (src != dst) {
58
- memcpy32(dst, env->gregs);
59
- memcpy32(env->gregs, src);
60
+ memcpy(dst, env->gregs, sizeof(env->gregs));
61
+ memcpy(env->gregs, src, sizeof(env->gregs));
62
}
63
}
64
65
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
66
/* Switch global register bank */
67
src = get_gregset(env, new_pstate_regs);
68
dst = get_gregset(env, pstate_regs);
69
- memcpy32(dst, env->gregs);
70
- memcpy32(env->gregs, src);
71
+ memcpy(dst, env->gregs, sizeof(env->gregs));
72
+ memcpy(env->gregs, src, sizeof(env->gregs));
73
} else {
74
trace_win_helper_no_switch_pstate(new_pstate_regs);
75
}
76
--
77
2.43.0
78
79
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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