[PULL 0/4] tcg patch queue
[PULL v2 00/53] tcg patch queue
1
Pretty small still, but there are two patches that ought
1
v2: Remove poisoned symbol CONFIG_RISCV_DIS from disas.c.
2
to get backported to stable, so no point in delaying.
2
Wasn't visible from x86 with gcc or clang;
3
was visible from macos clang;
4
was visible from native riscv clang.
5
3
6
4
r~
7
r~
5
8
6
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
7
9
8
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
10
The following changes since commit fff86d48a2cdcdfa75f845cac3e0d3cdd848d9e4:
11
12
Merge tag 'migration-20230509-pull-request' of https://gitlab.com/juan.quintela/qemu into staging (2023-05-11 05:55:12 +0100)
9
13
10
are available in the Git repository at:
14
are available in the Git repository at:
11
15
12
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212
16
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230511-2
13
17
14
for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:
18
for you to fetch changes up to 335dfd253fc242b009a1b9b5d4fffbf4ea52928d:
15
19
16
target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)
20
target/loongarch: Do not include tcg-ldst.h (2023-05-11 09:53:41 +0100)
17
21
18
----------------------------------------------------------------
22
----------------------------------------------------------------
19
tcg: Reset free_temps before tcg_optimize
23
target/m68k: Fix gen_load_fp regression
20
tcg/riscv: Fix StoreStore barrier generation
24
accel/tcg: Ensure fairness with icount
21
include/exec: Introduce fpst alias in helper-head.h.inc
25
disas: Move disas.c into the target-independent source sets
22
target/sparc: Use memcpy() and remove memcpy32()
26
tcg: Use common routines for calling slow path helpers
27
tcg/*: Cleanups to qemu_ld/st constraints
28
tcg: Remove TARGET_ALIGNED_ONLY
29
accel/tcg: Reorg system mode load/store helpers
23
30
24
----------------------------------------------------------------
31
----------------------------------------------------------------
25
Philippe Mathieu-Daudé (1):
32
Jamie Iles (2):
26
target/sparc: Use memcpy() and remove memcpy32()
33
cpu: expose qemu_cpu_list_lock for lock-guard use
34
accel/tcg/tcg-accel-ops-rr: ensure fairness with icount
27
35
28
Richard Henderson (2):
36
Richard Henderson (49):
29
tcg: Reset free_temps before tcg_optimize
37
target/m68k: Fix gen_load_fp for OS_LONG
30
include/exec: Introduce fpst alias in helper-head.h.inc
38
accel/tcg: Fix atomic_mmu_lookup for reads
39
disas: Fix tabs and braces in disas.c
40
disas: Move disas.c to disas/
41
disas: Remove target_ulong from the interface
42
disas: Remove target-specific headers
43
tcg/i386: Introduce prepare_host_addr
44
tcg/i386: Use indexed addressing for softmmu fast path
45
tcg/aarch64: Introduce prepare_host_addr
46
tcg/arm: Introduce prepare_host_addr
47
tcg/loongarch64: Introduce prepare_host_addr
48
tcg/mips: Introduce prepare_host_addr
49
tcg/ppc: Introduce prepare_host_addr
50
tcg/riscv: Introduce prepare_host_addr
51
tcg/s390x: Introduce prepare_host_addr
52
tcg: Add routines for calling slow-path helpers
53
tcg/i386: Convert tcg_out_qemu_ld_slow_path
54
tcg/i386: Convert tcg_out_qemu_st_slow_path
55
tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path
56
tcg/arm: Convert tcg_out_qemu_{ld,st}_slow_path
57
tcg/loongarch64: Convert tcg_out_qemu_{ld,st}_slow_path
58
tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path
59
tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path
60
tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path
61
tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path
62
tcg/loongarch64: Simplify constraints on qemu_ld/st
63
tcg/mips: Remove MO_BSWAP handling
64
tcg/mips: Reorg tlb load within prepare_host_addr
65
tcg/mips: Simplify constraints on qemu_ld/st
66
tcg/ppc: Reorg tcg_out_tlb_read
67
tcg/ppc: Adjust constraints on qemu_ld/st
68
tcg/ppc: Remove unused constraints A, B, C, D
69
tcg/ppc: Remove unused constraint J
70
tcg/riscv: Simplify constraints on qemu_ld/st
71
tcg/s390x: Use ALGFR in constructing softmmu host address
72
tcg/s390x: Simplify constraints on qemu_ld/st
73
target/mips: Add MO_ALIGN to gen_llwp, gen_scwp
74
target/mips: Add missing default_tcg_memop_mask
75
target/mips: Use MO_ALIGN instead of 0
76
target/mips: Remove TARGET_ALIGNED_ONLY
77
target/nios2: Remove TARGET_ALIGNED_ONLY
78
target/sh4: Use MO_ALIGN where required
79
target/sh4: Remove TARGET_ALIGNED_ONLY
80
tcg: Remove TARGET_ALIGNED_ONLY
81
accel/tcg: Add cpu_in_serial_context
82
accel/tcg: Introduce tlb_read_idx
83
accel/tcg: Reorg system mode load helpers
84
accel/tcg: Reorg system mode store helpers
85
target/loongarch: Do not include tcg-ldst.h
31
86
32
Roman Artemev (1):
87
Thomas Huth (2):
33
tcg/riscv: Fix StoreStore barrier generation
88
disas: Move softmmu specific code to separate file
89
disas: Move disas.c into the target-independent source set
34
90
35
include/tcg/tcg-temp-internal.h | 6 ++++++
91
configs/targets/mips-linux-user.mak | 1 -
36
accel/tcg/plugin-gen.c | 2 +-
92
configs/targets/mips-softmmu.mak | 1 -
37
target/sparc/win_helper.c | 26 ++++++++------------------
93
configs/targets/mips64-linux-user.mak | 1 -
38
tcg/tcg.c | 5 ++++-
94
configs/targets/mips64-softmmu.mak | 1 -
39
include/exec/helper-head.h.inc | 3 +++
95
configs/targets/mips64el-linux-user.mak | 1 -
40
tcg/riscv/tcg-target.c.inc | 2 +-
96
configs/targets/mips64el-softmmu.mak | 1 -
41
6 files changed, 23 insertions(+), 21 deletions(-)
97
configs/targets/mipsel-linux-user.mak | 1 -
42
98
configs/targets/mipsel-softmmu.mak | 1 -
99
configs/targets/mipsn32-linux-user.mak | 1 -
100
configs/targets/mipsn32el-linux-user.mak | 1 -
101
configs/targets/nios2-softmmu.mak | 1 -
102
configs/targets/sh4-linux-user.mak | 1 -
103
configs/targets/sh4-softmmu.mak | 1 -
104
configs/targets/sh4eb-linux-user.mak | 1 -
105
configs/targets/sh4eb-softmmu.mak | 1 -
106
meson.build | 3 -
107
accel/tcg/internal.h | 9 +
108
accel/tcg/tcg-accel-ops-icount.h | 3 +-
109
disas/disas-internal.h | 21 +
110
include/disas/disas.h | 23 +-
111
include/exec/cpu-common.h | 1 +
112
include/exec/cpu-defs.h | 7 +-
113
include/exec/cpu_ldst.h | 26 +-
114
include/exec/memop.h | 13 +-
115
include/exec/poison.h | 1 -
116
tcg/loongarch64/tcg-target-con-set.h | 2 -
117
tcg/loongarch64/tcg-target-con-str.h | 1 -
118
tcg/mips/tcg-target-con-set.h | 13 +-
119
tcg/mips/tcg-target-con-str.h | 2 -
120
tcg/mips/tcg-target.h | 4 +-
121
tcg/ppc/tcg-target-con-set.h | 11 +-
122
tcg/ppc/tcg-target-con-str.h | 7 -
123
tcg/riscv/tcg-target-con-set.h | 2 -
124
tcg/riscv/tcg-target-con-str.h | 1 -
125
tcg/s390x/tcg-target-con-set.h | 2 -
126
tcg/s390x/tcg-target-con-str.h | 1 -
127
accel/tcg/cpu-exec-common.c | 3 +
128
accel/tcg/cputlb.c | 1113 ++++++++++++++++-------------
129
accel/tcg/tb-maint.c | 2 +-
130
accel/tcg/tcg-accel-ops-icount.c | 21 +-
131
accel/tcg/tcg-accel-ops-rr.c | 37 +-
132
bsd-user/elfload.c | 5 +-
133
cpus-common.c | 2 +-
134
disas/disas-mon.c | 65 ++
135
disas.c => disas/disas.c | 111 +--
136
linux-user/elfload.c | 18 +-
137
migration/dirtyrate.c | 26 +-
138
replay/replay.c | 3 +-
139
target/loongarch/csr_helper.c | 1 -
140
target/loongarch/iocsr_helper.c | 1 -
141
target/m68k/translate.c | 1 +
142
target/mips/tcg/mxu_translate.c | 3 +-
143
target/nios2/translate.c | 10 +
144
target/sh4/translate.c | 102 ++-
145
tcg/tcg.c | 480 ++++++++++++-
146
trace/control-target.c | 9 +-
147
target/mips/tcg/micromips_translate.c.inc | 24 +-
148
target/mips/tcg/mips16e_translate.c.inc | 18 +-
149
target/mips/tcg/nanomips_translate.c.inc | 32 +-
150
tcg/aarch64/tcg-target.c.inc | 347 ++++-----
151
tcg/arm/tcg-target.c.inc | 455 +++++-------
152
tcg/i386/tcg-target.c.inc | 453 +++++-------
153
tcg/loongarch64/tcg-target.c.inc | 313 +++-----
154
tcg/mips/tcg-target.c.inc | 870 +++++++---------------
155
tcg/ppc/tcg-target.c.inc | 512 ++++++-------
156
tcg/riscv/tcg-target.c.inc | 304 ++++----
157
tcg/s390x/tcg-target.c.inc | 314 ++++----
158
disas/meson.build | 6 +-
159
68 files changed, 2789 insertions(+), 3040 deletions(-)
160
create mode 100644 disas/disas-internal.h
161
create mode 100644 disas/disas-mon.c
162
rename disas.c => disas/disas.c (78%)
diff view generated by jsdifflib
[PULL 1/4] tcg: Reset free_temps before tcg_optimize
Deleted patch
1
When allocating new temps during tcg_optmize, do not re-use
2
any EBB temps that were used within the TB. We do not have
3
any idea what span of the TB in which the temp was live.
4
1
5
Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
6
as well as replacing the equivalent in plugin_gen_inject and
7
tcg_func_start.
8
9
Cc: qemu-stable@nongnu.org
10
Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
11
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
12
Reported-by: wannacu <wannacu2049@gmail.com>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
---
17
include/tcg/tcg-temp-internal.h | 6 ++++++
18
accel/tcg/plugin-gen.c | 2 +-
19
tcg/tcg.c | 5 ++++-
20
3 files changed, 11 insertions(+), 2 deletions(-)
21
22
diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/include/tcg/tcg-temp-internal.h
25
+++ b/include/tcg/tcg-temp-internal.h
26
@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
27
TCGv_ptr tcg_temp_ebb_new_ptr(void);
28
TCGv_i128 tcg_temp_ebb_new_i128(void);
29
30
+/* Forget all freed EBB temps, so that new allocations produce new temps. */
31
+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
32
+{
33
+ memset(s->free_temps, 0, sizeof(s->free_temps));
34
+}
35
+
36
#endif /* TCG_TEMP_FREE_H */
37
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/accel/tcg/plugin-gen.c
40
+++ b/accel/tcg/plugin-gen.c
41
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
42
* that might be live within the existing opcode stream.
43
* The simplest solution is to release them all and create new.
44
*/
45
- memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
46
+ tcg_temp_ebb_reset_freed(tcg_ctx);
47
48
QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
49
switch (op->opc) {
50
diff --git a/tcg/tcg.c b/tcg/tcg.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/tcg/tcg.c
53
+++ b/tcg/tcg.c
54
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
55
s->nb_temps = s->nb_globals;
56
57
/* No temps have been previously allocated for size or locality. */
58
- memset(s->free_temps, 0, sizeof(s->free_temps));
59
+ tcg_temp_ebb_reset_freed(s);
60
61
/* No constant temps have been previously allocated. */
62
for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
63
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
64
}
65
#endif
66
67
+ /* Do not reuse any EBB that may be allocated within the TB. */
68
+ tcg_temp_ebb_reset_freed(s);
69
+
70
tcg_optimize(s);
71
72
reachable_code_pass(s);
73
--
74
2.43.0
75
76
diff view generated by jsdifflib
[PULL 2/4] tcg/riscv: Fix StoreStore barrier generation
Deleted patch
1
From: Roman Artemev <roman.artemev@syntacore.com>
2
1
3
On RISC-V to StoreStore barrier corresponds
4
`fence w, w` not `fence r, r`
5
6
Cc: qemu-stable@nongnu.org
7
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
10
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
11
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
14
tcg/riscv/tcg-target.c.inc | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
18
index XXXXXXX..XXXXXXX 100644
19
--- a/tcg/riscv/tcg-target.c.inc
20
+++ b/tcg/riscv/tcg-target.c.inc
21
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
22
insn |= 0x02100000;
23
}
24
if (a0 & TCG_MO_ST_ST) {
25
- insn |= 0x02200000;
26
+ insn |= 0x01100000;
27
}
28
tcg_out32(s, insn);
29
}
30
--
31
2.43.0
diff view generated by jsdifflib
[PULL 3/4] include/exec: Introduce fpst alias in helper-head.h.inc
Deleted patch
1
This allows targets to declare that the helper requires a
2
float_status pointer and instead of a generic void pointer.
3
1
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
include/exec/helper-head.h.inc | 3 +++
8
1 file changed, 3 insertions(+)
9
10
diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/include/exec/helper-head.h.inc
13
+++ b/include/exec/helper-head.h.inc
14
@@ -XXX,XX +XXX,XX @@
15
#define dh_alias_ptr ptr
16
#define dh_alias_cptr ptr
17
#define dh_alias_env ptr
18
+#define dh_alias_fpst ptr
19
#define dh_alias_void void
20
#define dh_alias_noreturn noreturn
21
#define dh_alias(t) glue(dh_alias_, t)
22
@@ -XXX,XX +XXX,XX @@
23
#define dh_ctype_ptr void *
24
#define dh_ctype_cptr const void *
25
#define dh_ctype_env CPUArchState *
26
+#define dh_ctype_fpst float_status *
27
#define dh_ctype_void void
28
#define dh_ctype_noreturn G_NORETURN void
29
#define dh_ctype(t) dh_ctype_##t
30
@@ -XXX,XX +XXX,XX @@
31
#define dh_typecode_f64 dh_typecode_i64
32
#define dh_typecode_cptr dh_typecode_ptr
33
#define dh_typecode_env dh_typecode_ptr
34
+#define dh_typecode_fpst dh_typecode_ptr
35
#define dh_typecode(t) dh_typecode_##t
36
37
#define dh_callflag_i32 0
38
--
39
2.43.0
40
41
diff view generated by jsdifflib
[PULL 4/4] target/sparc: Use memcpy() and remove memcpy32()
[PULL v2 08/53] disas: Move disas.c into the target-independent source set
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
Rather than manually copying each register, use
3
Use target_words_bigendian() instead of an ifdef.
4
the libc memcpy(), which is well optimized nowadays.
5
4
6
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
5
Remove CONFIG_RISCV_DIS from the check for riscv as a host; this is
7
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
6
a poisoned identifier, and anyway will always be set by meson.build
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
when building on a riscv host.
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
10
Message-ID: <20241205205418.67613-1-philmd@linaro.org>
9
Signed-off-by: Thomas Huth <thuth@redhat.com>
10
Message-Id: <20230508133745.109463-3-thuth@redhat.com>
11
[rth: Type change done in a separate patch]
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
13
---
13
target/sparc/win_helper.c | 26 ++++++++------------------
14
disas/disas.c | 12 ++++++------
14
1 file changed, 8 insertions(+), 18 deletions(-)
15
disas/meson.build | 3 ++-
16
2 files changed, 8 insertions(+), 7 deletions(-)
15
17
16
diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
18
diff --git a/disas/disas.c b/disas/disas.c
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/target/sparc/win_helper.c
20
--- a/disas/disas.c
19
+++ b/target/sparc/win_helper.c
21
+++ b/disas/disas.c
20
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ void disas_initialize_debug_target(CPUDebug *s, CPUState *cpu)
21
#include "exec/helper-proto.h"
23
s->cpu = cpu;
22
#include "trace.h"
24
s->info.read_memory_func = target_read_memory;
23
25
s->info.print_address_func = print_address;
24
-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
26
-#if TARGET_BIG_ENDIAN
25
-{
27
- s->info.endian = BFD_ENDIAN_BIG;
26
- dst[0] = src[0];
28
-#else
27
- dst[1] = src[1];
29
- s->info.endian = BFD_ENDIAN_LITTLE;
28
- dst[2] = src[2];
30
-#endif
29
- dst[3] = src[3];
31
+ if (target_words_bigendian()) {
30
- dst[4] = src[4];
32
+ s->info.endian = BFD_ENDIAN_BIG;
31
- dst[5] = src[5];
33
+ } else {
32
- dst[6] = src[6];
34
+ s->info.endian = BFD_ENDIAN_LITTLE;
33
- dst[7] = src[7];
35
+ }
34
-}
36
35
-
37
CPUClass *cc = CPU_GET_CLASS(cpu);
36
void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
38
if (cc->disas_set_info) {
37
{
39
@@ -XXX,XX +XXX,XX @@ static void initialize_debug_host(CPUDebug *s)
38
/* put the modified wrap registers at their proper location */
40
# ifdef _ARCH_PPC64
39
if (env->cwp == env->nwindows - 1) {
41
s->info.cap_mode = CS_MODE_64;
40
- memcpy32(env->regbase, env->regbase + env->nwindows * 16);
42
# endif
41
+ memcpy(env->regbase, env->regbase + env->nwindows * 16,
43
-#elif defined(__riscv) && defined(CONFIG_RISCV_DIS)
42
+ sizeof(env->gregs));
44
+#elif defined(__riscv)
43
}
45
#if defined(_ILP32) || (__riscv_xlen == 32)
44
env->cwp = new_cwp;
46
s->info.print_insn = print_insn_riscv32;
45
47
#elif defined(_LP64)
46
/* put the wrap registers at their temporary location */
48
diff --git a/disas/meson.build b/disas/meson.build
47
if (new_cwp == env->nwindows - 1) {
49
index XXXXXXX..XXXXXXX 100644
48
- memcpy32(env->regbase + env->nwindows * 16, env->regbase);
50
--- a/disas/meson.build
49
+ memcpy(env->regbase + env->nwindows * 16, env->regbase,
51
+++ b/disas/meson.build
50
+ sizeof(env->gregs));
52
@@ -XXX,XX +XXX,XX @@ common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))
51
}
53
common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c'))
52
env->regwptr = env->regbase + (new_cwp * 16);
54
common_ss.add(when: 'CONFIG_XTENSA_DIS', if_true: files('xtensa.c'))
53
}
55
common_ss.add(when: capstone, if_true: [files('capstone.c'), capstone])
54
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
56
+common_ss.add(files('disas.c'))
55
dst = get_gl_gregset(env, env->gl);
57
56
58
softmmu_ss.add(files('disas-mon.c'))
57
if (src != dst) {
59
-specific_ss.add(files('disas.c'), capstone)
58
- memcpy32(dst, env->gregs);
60
+specific_ss.add(capstone)
59
- memcpy32(env->gregs, src);
60
+ memcpy(dst, env->gregs, sizeof(env->gregs));
61
+ memcpy(env->gregs, src, sizeof(env->gregs));
62
}
63
}
64
65
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
66
/* Switch global register bank */
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src = get_gregset(env, new_pstate_regs);
68
dst = get_gregset(env, pstate_regs);
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- memcpy32(dst, env->gregs);
70
- memcpy32(env->gregs, src);
71
+ memcpy(dst, env->gregs, sizeof(env->gregs));
72
+ memcpy(env->gregs, src, sizeof(env->gregs));
73
} else {
74
trace_win_helper_no_switch_pstate(new_pstate_regs);
75
}
76
--
61
--
77
2.43.0
62
2.34.1
78
79
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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