1
Pretty small still, but there are two patches that ought
1
The following changes since commit c586691e676214eb7edf6a468e84e7ce3b314d43:
2
to get backported to stable, so no point in delaying.
3
2
4
r~
3
Merge tag 'pull-target-arm-20230502-2' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-05-02 16:38:29 +0100)
5
6
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
7
8
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
9
4
10
are available in the Git repository at:
5
are available in the Git repository at:
11
6
12
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230502-2
13
8
14
for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:
9
for you to fetch changes up to 129f1f9ee7df77d367d961b3c25353612d33cd83:
15
10
16
target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)
11
tcg: Introduce tcg_out_movext2 (2023-05-02 13:05:45 -0700)
17
12
18
----------------------------------------------------------------
13
----------------------------------------------------------------
19
tcg: Reset free_temps before tcg_optimize
14
Misc tcg-related patch queue.
20
tcg/riscv: Fix StoreStore barrier generation
15
21
include/exec: Introduce fpst alias in helper-head.h.inc
16
v2: Update bitops.h rotate patch.
22
target/sparc: Use memcpy() and remove memcpy32()
23
17
24
----------------------------------------------------------------
18
----------------------------------------------------------------
25
Philippe Mathieu-Daudé (1):
19
Dickon Hood (1):
26
target/sparc: Use memcpy() and remove memcpy32()
20
qemu/bitops.h: Limit rotate amounts
27
21
28
Richard Henderson (2):
22
Kiran Ostrolenk (1):
29
tcg: Reset free_temps before tcg_optimize
23
qemu/host-utils.h: Add clz and ctz functions for lower-bit integers
30
include/exec: Introduce fpst alias in helper-head.h.inc
31
24
32
Roman Artemev (1):
25
Nazar Kazakov (2):
33
tcg/riscv: Fix StoreStore barrier generation
26
tcg: Add tcg_gen_gvec_andcs
27
tcg: Add tcg_gen_gvec_rotrs
34
28
35
include/tcg/tcg-temp-internal.h | 6 ++++++
29
Richard Henderson (7):
36
accel/tcg/plugin-gen.c | 2 +-
30
softmmu: Tidy dirtylimit_dirty_ring_full_time
37
target/sparc/win_helper.c | 26 ++++++++------------------
31
qemu/int128: Re-shuffle Int128Alias members
38
tcg/tcg.c | 5 ++++-
32
migration/xbzrle: Use __attribute__((target)) for avx512
39
include/exec/helper-head.h.inc | 3 +++
33
accel/tcg: Add cpu_ld*_code_mmu
40
tcg/riscv/tcg-target.c.inc | 2 +-
34
tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64
41
6 files changed, 23 insertions(+), 21 deletions(-)
35
tcg/mips: Conditionalize tcg_out_exts_i32_i64
36
tcg: Introduce tcg_out_movext2
42
37
38
Weiwei Li (1):
39
accel/tcg: Uncache the host address for instruction fetch when tlb size < 1
40
41
meson.build | 5 +--
42
accel/tcg/tcg-runtime.h | 1 +
43
include/exec/cpu_ldst.h | 9 ++++++
44
include/qemu/bitops.h | 16 +++++-----
45
include/qemu/host-utils.h | 54 +++++++++++++++++++++++++++++++
46
include/qemu/int128.h | 4 +--
47
include/tcg/tcg-op-gvec.h | 4 +++
48
accel/tcg/cputlb.c | 53 ++++++++++++++++++++++++++++++
49
accel/tcg/tcg-runtime-gvec.c | 11 +++++++
50
accel/tcg/user-exec.c | 58 +++++++++++++++++++++++++++++++++
51
migration/xbzrle.c | 9 +++---
52
softmmu/dirtylimit.c | 15 ++++++---
53
tcg/tcg-op-gvec.c | 28 ++++++++++++++++
54
tcg/tcg.c | 69 +++++++++++++++++++++++++++++++++++++---
55
tcg/arm/tcg-target.c.inc | 44 +++++++++++--------------
56
tcg/i386/tcg-target.c.inc | 19 +++++------
57
tcg/loongarch64/tcg-target.c.inc | 4 ++-
58
tcg/mips/tcg-target.c.inc | 4 ++-
59
18 files changed, 339 insertions(+), 68 deletions(-)
diff view generated by jsdifflib
Deleted patch
1
When allocating new temps during tcg_optmize, do not re-use
2
any EBB temps that were used within the TB. We do not have
3
any idea what span of the TB in which the temp was live.
4
1
5
Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
6
as well as replacing the equivalent in plugin_gen_inject and
7
tcg_func_start.
8
9
Cc: qemu-stable@nongnu.org
10
Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
11
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
12
Reported-by: wannacu <wannacu2049@gmail.com>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
---
17
include/tcg/tcg-temp-internal.h | 6 ++++++
18
accel/tcg/plugin-gen.c | 2 +-
19
tcg/tcg.c | 5 ++++-
20
3 files changed, 11 insertions(+), 2 deletions(-)
21
22
diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/include/tcg/tcg-temp-internal.h
25
+++ b/include/tcg/tcg-temp-internal.h
26
@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
27
TCGv_ptr tcg_temp_ebb_new_ptr(void);
28
TCGv_i128 tcg_temp_ebb_new_i128(void);
29
30
+/* Forget all freed EBB temps, so that new allocations produce new temps. */
31
+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
32
+{
33
+ memset(s->free_temps, 0, sizeof(s->free_temps));
34
+}
35
+
36
#endif /* TCG_TEMP_FREE_H */
37
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/accel/tcg/plugin-gen.c
40
+++ b/accel/tcg/plugin-gen.c
41
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
42
* that might be live within the existing opcode stream.
43
* The simplest solution is to release them all and create new.
44
*/
45
- memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
46
+ tcg_temp_ebb_reset_freed(tcg_ctx);
47
48
QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
49
switch (op->opc) {
50
diff --git a/tcg/tcg.c b/tcg/tcg.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/tcg/tcg.c
53
+++ b/tcg/tcg.c
54
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
55
s->nb_temps = s->nb_globals;
56
57
/* No temps have been previously allocated for size or locality. */
58
- memset(s->free_temps, 0, sizeof(s->free_temps));
59
+ tcg_temp_ebb_reset_freed(s);
60
61
/* No constant temps have been previously allocated. */
62
for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
63
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
64
}
65
#endif
66
67
+ /* Do not reuse any EBB that may be allocated within the TB. */
68
+ tcg_temp_ebb_reset_freed(s);
69
+
70
tcg_optimize(s);
71
72
reachable_code_pass(s);
73
--
74
2.43.0
75
76
diff view generated by jsdifflib
Deleted patch
1
From: Roman Artemev <roman.artemev@syntacore.com>
2
1
3
On RISC-V to StoreStore barrier corresponds
4
`fence w, w` not `fence r, r`
5
6
Cc: qemu-stable@nongnu.org
7
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
10
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
11
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
14
tcg/riscv/tcg-target.c.inc | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
18
index XXXXXXX..XXXXXXX 100644
19
--- a/tcg/riscv/tcg-target.c.inc
20
+++ b/tcg/riscv/tcg-target.c.inc
21
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
22
insn |= 0x02100000;
23
}
24
if (a0 & TCG_MO_ST_ST) {
25
- insn |= 0x02200000;
26
+ insn |= 0x01100000;
27
}
28
tcg_out32(s, insn);
29
}
30
--
31
2.43.0
diff view generated by jsdifflib
Deleted patch
1
This allows targets to declare that the helper requires a
2
float_status pointer and instead of a generic void pointer.
3
1
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
include/exec/helper-head.h.inc | 3 +++
8
1 file changed, 3 insertions(+)
9
10
diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/include/exec/helper-head.h.inc
13
+++ b/include/exec/helper-head.h.inc
14
@@ -XXX,XX +XXX,XX @@
15
#define dh_alias_ptr ptr
16
#define dh_alias_cptr ptr
17
#define dh_alias_env ptr
18
+#define dh_alias_fpst ptr
19
#define dh_alias_void void
20
#define dh_alias_noreturn noreturn
21
#define dh_alias(t) glue(dh_alias_, t)
22
@@ -XXX,XX +XXX,XX @@
23
#define dh_ctype_ptr void *
24
#define dh_ctype_cptr const void *
25
#define dh_ctype_env CPUArchState *
26
+#define dh_ctype_fpst float_status *
27
#define dh_ctype_void void
28
#define dh_ctype_noreturn G_NORETURN void
29
#define dh_ctype(t) dh_ctype_##t
30
@@ -XXX,XX +XXX,XX @@
31
#define dh_typecode_f64 dh_typecode_i64
32
#define dh_typecode_cptr dh_typecode_ptr
33
#define dh_typecode_env dh_typecode_ptr
34
+#define dh_typecode_fpst dh_typecode_ptr
35
#define dh_typecode(t) dh_typecode_##t
36
37
#define dh_callflag_i32 0
38
--
39
2.43.0
40
41
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
From: Dickon Hood <dickon.hood@codethink.co.uk>
2
2
3
Rather than manually copying each register, use
3
Rotates have been fixed up to only allow for reasonable rotate amounts
4
the libc memcpy(), which is well optimized nowadays.
4
(ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv
5
vector rotate instructions.
5
6
6
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
7
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-Id: <20230428144757.57530-9-lawrence.hunter@codethink.co.uk>
10
Message-ID: <20241205205418.67613-1-philmd@linaro.org>
10
[rth: Mask shifts in both directions.]
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
12
---
13
target/sparc/win_helper.c | 26 ++++++++------------------
13
include/qemu/bitops.h | 16 ++++++++--------
14
1 file changed, 8 insertions(+), 18 deletions(-)
14
1 file changed, 8 insertions(+), 8 deletions(-)
15
15
16
diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
16
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/sparc/win_helper.c
18
--- a/include/qemu/bitops.h
19
+++ b/target/sparc/win_helper.c
19
+++ b/include/qemu/bitops.h
20
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static inline unsigned long find_first_zero_bit(const unsigned long *addr,
21
#include "exec/helper-proto.h"
21
*/
22
#include "trace.h"
22
static inline uint8_t rol8(uint8_t word, unsigned int shift)
23
24
-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
25
-{
26
- dst[0] = src[0];
27
- dst[1] = src[1];
28
- dst[2] = src[2];
29
- dst[3] = src[3];
30
- dst[4] = src[4];
31
- dst[5] = src[5];
32
- dst[6] = src[6];
33
- dst[7] = src[7];
34
-}
35
-
36
void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
37
{
23
{
38
/* put the modified wrap registers at their proper location */
24
- return (word << shift) | (word >> ((8 - shift) & 7));
39
if (env->cwp == env->nwindows - 1) {
25
+ return (word << (shift & 7)) | (word >> (-shift & 7));
40
- memcpy32(env->regbase, env->regbase + env->nwindows * 16);
41
+ memcpy(env->regbase, env->regbase + env->nwindows * 16,
42
+ sizeof(env->gregs));
43
}
44
env->cwp = new_cwp;
45
46
/* put the wrap registers at their temporary location */
47
if (new_cwp == env->nwindows - 1) {
48
- memcpy32(env->regbase + env->nwindows * 16, env->regbase);
49
+ memcpy(env->regbase + env->nwindows * 16, env->regbase,
50
+ sizeof(env->gregs));
51
}
52
env->regwptr = env->regbase + (new_cwp * 16);
53
}
26
}
54
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
27
55
dst = get_gl_gregset(env, env->gl);
28
/**
56
29
@@ -XXX,XX +XXX,XX @@ static inline uint8_t rol8(uint8_t word, unsigned int shift)
57
if (src != dst) {
30
*/
58
- memcpy32(dst, env->gregs);
31
static inline uint8_t ror8(uint8_t word, unsigned int shift)
59
- memcpy32(env->gregs, src);
32
{
60
+ memcpy(dst, env->gregs, sizeof(env->gregs));
33
- return (word >> shift) | (word << ((8 - shift) & 7));
61
+ memcpy(env->gregs, src, sizeof(env->gregs));
34
+ return (word >> (shift & 7)) | (word << (-shift & 7));
62
}
63
}
35
}
64
36
65
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
37
/**
66
/* Switch global register bank */
38
@@ -XXX,XX +XXX,XX @@ static inline uint8_t ror8(uint8_t word, unsigned int shift)
67
src = get_gregset(env, new_pstate_regs);
39
*/
68
dst = get_gregset(env, pstate_regs);
40
static inline uint16_t rol16(uint16_t word, unsigned int shift)
69
- memcpy32(dst, env->gregs);
41
{
70
- memcpy32(env->gregs, src);
42
- return (word << shift) | (word >> ((16 - shift) & 15));
71
+ memcpy(dst, env->gregs, sizeof(env->gregs));
43
+ return (word << (shift & 15)) | (word >> (-shift & 15));
72
+ memcpy(env->gregs, src, sizeof(env->gregs));
44
}
73
} else {
45
74
trace_win_helper_no_switch_pstate(new_pstate_regs);
46
/**
75
}
47
@@ -XXX,XX +XXX,XX @@ static inline uint16_t rol16(uint16_t word, unsigned int shift)
48
*/
49
static inline uint16_t ror16(uint16_t word, unsigned int shift)
50
{
51
- return (word >> shift) | (word << ((16 - shift) & 15));
52
+ return (word >> (shift & 15)) | (word << (-shift & 15));
53
}
54
55
/**
56
@@ -XXX,XX +XXX,XX @@ static inline uint16_t ror16(uint16_t word, unsigned int shift)
57
*/
58
static inline uint32_t rol32(uint32_t word, unsigned int shift)
59
{
60
- return (word << shift) | (word >> ((32 - shift) & 31));
61
+ return (word << (shift & 31)) | (word >> (-shift & 31));
62
}
63
64
/**
65
@@ -XXX,XX +XXX,XX @@ static inline uint32_t rol32(uint32_t word, unsigned int shift)
66
*/
67
static inline uint32_t ror32(uint32_t word, unsigned int shift)
68
{
69
- return (word >> shift) | (word << ((32 - shift) & 31));
70
+ return (word >> (shift & 31)) | (word << (-shift & 31));
71
}
72
73
/**
74
@@ -XXX,XX +XXX,XX @@ static inline uint32_t ror32(uint32_t word, unsigned int shift)
75
*/
76
static inline uint64_t rol64(uint64_t word, unsigned int shift)
77
{
78
- return (word << shift) | (word >> ((64 - shift) & 63));
79
+ return (word << (shift & 63)) | (word >> (-shift & 63));
80
}
81
82
/**
83
@@ -XXX,XX +XXX,XX @@ static inline uint64_t rol64(uint64_t word, unsigned int shift)
84
*/
85
static inline uint64_t ror64(uint64_t word, unsigned int shift)
86
{
87
- return (word >> shift) | (word << ((64 - shift) & 63));
88
+ return (word >> (shift & 63)) | (word << (-shift & 63));
89
}
90
91
/**
76
--
92
--
77
2.43.0
93
2.34.1
78
79
diff view generated by jsdifflib