Series comparison

-[PULL 0/4] tcg patch queue
+[PULL v3 00/91] tcg patch queue
-Pretty small still, but there are two patches that ought
+Version 3 fixes a rebase error from v2 affecting ARM BFC insn.
-to get backported to stable, so no point in delaying.
 r~
-The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
-  Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
+The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517:
   Merge tag 'linux-user-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2023-03-12 10:57:00 +0000)
 are available in the Git repository at:
-  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212
+  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230313
-for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:
+for you to fetch changes up to 0c8b6b9a6383e2e37ff3d1d12b40c58b7ed36c1c:
-  target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)
+  tcg: Drop tcg_const_* (2023-03-13 07:03:39 -0700)
 ----------------------------------------------------------------
-tcg: Reset free_temps before tcg_optimize
+accel/tcg: Fix NB_MMU_MODES to 16
-tcg/riscv: Fix StoreStore barrier generation
+Balance of the target/ patchset which eliminates tcg_temp_free
-include/exec: Introduce fpst alias in helper-head.h.inc
+Balance of the target/ patchset which eliminates tcg_const
 target/sparc: Use memcpy() and remove memcpy32()
 ----------------------------------------------------------------
-Philippe Mathieu-Daudé (1):
+Anton Johansson (23):
-      target/sparc: Use memcpy() and remove memcpy32()
+      include/exec: Set default `NB_MMU_MODES` to 16
       target/alpha: Remove `NB_MMU_MODES` define
       target/arm: Remove `NB_MMU_MODES` define
       target/avr: Remove `NB_MMU_MODES` define
       target/cris: Remove `NB_MMU_MODES` define
       target/hexagon: Remove `NB_MMU_MODES` define
       target/hppa: Remove `NB_MMU_MODES` define
       target/i386: Remove `NB_MMU_MODES` define
       target/loongarch: Remove `NB_MMU_MODES` define
       target/m68k: Remove `NB_MMU_MODES` define
       target/microblaze: Remove `NB_MMU_MODES` define
       target/mips: Remove `NB_MMU_MODES` define
       target/nios2: Remove `NB_MMU_MODES` define
       target/openrisc: Remove `NB_MMU_MODES` define
       target/ppc: Remove `NB_MMU_MODES` define
       target/riscv: Remove `NB_MMU_MODES` define
       target/rx: Remove `NB_MMU_MODES` define
       target/s390x: Remove `NB_MMU_MODES` define
       target/sh4: Remove `NB_MMU_MODES` define
       target/sparc: Remove `NB_MMU_MODES` define
       target/tricore: Remove `NB_MMU_MODES` define
       target/xtensa: Remove `NB_MMU_MODES` define
       include/exec: Remove guards around `NB_MMU_MODES`
-Richard Henderson (2):
+Richard Henderson (68):
-      tcg: Reset free_temps before tcg_optimize
+      target/mips: Drop tcg_temp_free from micromips_translate.c.inc
-      include/exec: Introduce fpst alias in helper-head.h.inc
+      target/mips: Drop tcg_temp_free from msa_translate.c
       target/mips: Drop tcg_temp_free from mxu_translate.c
       target/mips: Drop tcg_temp_free from nanomips_translate.c.inc
       target/mips: Drop tcg_temp_free from octeon_translate.c
       target/mips: Drop tcg_temp_free from translate_addr_const.c
       target/mips: Drop tcg_temp_free from tx79_translate.c
       target/mips: Drop tcg_temp_free from vr54xx_translate.c
       target/mips: Drop tcg_temp_free from translate.c
       target/s390x: Drop free_compare
       target/s390x: Drop tcg_temp_free from translate_vx.c.inc
       target/s390x: Drop tcg_temp_free from translate.c
       target/s390x: Remove assert vs g_in2
       target/s390x: Remove g_out, g_out2, g_in1, g_in2 from DisasContext
       tcg: Create tcg/tcg-temp-internal.h
       target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS
       target/avr: Avoid use of tcg_const_i32 throughout
       target/cris: Avoid use of tcg_const_i32 throughout
       target/hppa: Avoid tcg_const_i64 in trans_fid_f
       target/hppa: Avoid use of tcg_const_i32 throughout
       target/i386: Avoid use of tcg_const_* throughout
       target/m68k: Avoid tcg_const_i32 when modified
       target/m68k: Avoid tcg_const_i32 in bfop_reg
       target/m68k: Avoid tcg_const_* throughout
       target/mips: Split out gen_lxl
       target/mips: Split out gen_lxr
       target/mips: Avoid tcg_const_tl in gen_r6_ld
       target/mips: Avoid tcg_const_* throughout
       target/ppc: Split out gen_vx_vmul10
       target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad
       target/rx: Use tcg_gen_abs_i32
       target/rx: Use cpu_psw_z as temp in flags computation
       target/rx: Avoid tcg_const_i32 when new temp needed
       target/rx: Avoid tcg_const_i32
       target/s390x: Avoid tcg_const_i64
       target/sh4: Avoid tcg_const_i32 for TAS.B
       target/sh4: Avoid tcg_const_i32
       tcg/sparc: Avoid tcg_const_tl in gen_edge
       target/tricore: Split t_n as constant from temp as variable
       target/tricore: Rename t_off10 and use tcg_constant_i32
       target/tricore: Use setcondi instead of explicit allocation
       target/tricore: Drop some temp initialization
       target/tricore: Avoid tcg_const_i32
       tcg: Replace tcg_const_i64 in tcg-op.c
       target/arm: Use rmode >= 0 for need_rmode
       target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf
       target/arm: Improve arm_rmode_to_sf
       target/arm: Consistently use ARMFPRounding during translation
       target/arm: Create gen_set_rmode, gen_restore_rmode
       target/arm: Improve trans_BFCI
       target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
       target/arm: Avoid tcg_const_* in translate-mve.c
       target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
       target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
       target/arm: Avoid tcg_const_ptr in handle_rev
       target/m68k: Use tcg_constant_i32 in gen_ea_mode
       target/ppc: Avoid tcg_const_i64 in do_vcntmb
       target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
       target/ppc: Avoid tcg_const_* in xxeval
       target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
       target/ppc: Avoid tcg_const_* in fp-impl.c.inc
       target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
       target/ppc: Rewrite trans_ADDG6S
       target/ppc: Fix gen_tlbsx_booke206
       target/ppc: Avoid tcg_const_* in translate.c
       target/tricore: Use min/max for saturate
       tcg: Drop tcg_const_*_vec
       tcg: Drop tcg_const_*
-Roman Artemev (1):
+ include/exec/cpu-defs.h                    |   9 +-
-      tcg/riscv: Fix StoreStore barrier generation
+ include/tcg/tcg-op.h                       |   4 -
+ include/tcg/tcg-temp-internal.h            |  83 +++
- include/tcg/tcg-temp-internal.h |  6 ++++++
+ include/tcg/tcg.h                          |  64 ---
- accel/tcg/plugin-gen.c          |  2 +-
+ target/alpha/cpu-param.h                   |   2 -
- target/sparc/win_helper.c       | 26 ++++++++------------------
+ target/arm/cpu-param.h                     |   2 -
- tcg/tcg.c                       |  5 ++++-
+ target/arm/internals.h                     |  12 +-
- include/exec/helper-head.h.inc  |  3 +++
+ target/arm/tcg/translate.h                 |  17 +
- tcg/riscv/tcg-target.c.inc      |  2 +-
+ target/avr/cpu-param.h                     |   1 -
-files changed, 23 insertions(+), 21 deletions(-)
+ target/cris/cpu-param.h                    |   1 -
+ target/hexagon/cpu-param.h                 |   2 -
  target/hppa/cpu-param.h                    |   1 -
  target/i386/cpu-param.h                    |   1 -
  target/loongarch/cpu-param.h               |   1 -
  target/m68k/cpu-param.h                    |   1 -
  target/microblaze/cpu-param.h              |   1 -
  target/microblaze/cpu.h                    |   2 +-
  target/mips/cpu-param.h                    |   1 -
  target/nios2/cpu-param.h                   |   1 -
  target/openrisc/cpu-param.h                |   1 -
  target/ppc/cpu-param.h                     |   1 -
  target/riscv/cpu-param.h                   |   1 -
  target/rx/cpu-param.h                      |   2 -
  target/s390x/cpu-param.h                   |   1 -
  target/sh4/cpu-param.h                     |   1 -
  target/sparc/cpu-param.h                   |   2 -
  target/tricore/cpu-param.h                 |   1 -
  target/xtensa/cpu-param.h                  |   1 -
  accel/tcg/plugin-gen.c                     |   1 +
  target/arm/tcg/translate-a64.c             | 168 +++---
  target/arm/tcg/translate-mve.c             |  56 +-
  target/arm/tcg/translate-sve.c             |  28 +-
  target/arm/tcg/translate-vfp.c             |  26 +-
  target/arm/tcg/translate.c                 |  14 +-
  target/arm/vfp_helper.c                    |  35 +-
  target/avr/translate.c                     |  48 +-
  target/cris/translate.c                    |  46 +-
  target/hppa/translate.c                    |  35 +-
  target/i386/tcg/translate.c                |  83 +--
  target/m68k/translate.c                    | 231 ++++----
  target/mips/tcg/msa_translate.c            |   9 -
  target/mips/tcg/mxu_translate.c            |  55 +-
  target/mips/tcg/octeon_translate.c         |  23 -
  target/mips/tcg/translate.c                | 819 +++++------------------------
  target/mips/tcg/translate_addr_const.c     |   7 -
  target/mips/tcg/tx79_translate.c           |  45 +-
  target/mips/tcg/vr54xx_translate.c         |   4 -
  target/ppc/translate.c                     | 148 +++---
  target/rx/translate.c                      |  84 ++-
  target/s390x/tcg/translate.c               | 208 +-------
  target/sh4/translate.c                     |  35 +-
  target/sparc/translate.c                   |  14 +-
  target/tricore/translate.c                 | 476 ++++++++---------
  tcg/tcg-op-gvec.c                          |   1 +
  tcg/tcg-op-vec.c                           |  35 +-
  tcg/tcg-op.c                               |  13 +-
  tcg/tcg.c                                  |  17 +-
  target/cris/translate_v10.c.inc            |  26 +-
  target/mips/tcg/micromips_translate.c.inc  |  12 +-
  target/mips/tcg/nanomips_translate.c.inc   | 143 +----
  target/ppc/power8-pmu-regs.c.inc           |   4 +-
  target/ppc/translate/fixedpoint-impl.c.inc |  44 +-
  target/ppc/translate/fp-impl.c.inc         |  26 +-
  target/ppc/translate/vmx-impl.c.inc        | 130 ++---
  target/ppc/translate/vsx-impl.c.inc        |  36 +-
  target/s390x/tcg/translate_vx.c.inc        | 143 -----
  tcg/i386/tcg-target.c.inc                  |   9 +-
 files changed, 1166 insertions(+), 2388 deletions(-)
  create mode 100644 include/tcg/tcg-temp-internal.h

-[PULL 1/4] tcg: Reset free_temps before tcg_optimize
+Deleted patch
-When allocating new temps during tcg_optmize, do not re-use
-any EBB temps that were used within the TB.  We do not have
-any idea what span of the TB in which the temp was live.
-Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
-as well as replacing the equivalent in plugin_gen_inject and
-tcg_func_start.
-Cc: qemu-stable@nongnu.org
-Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
-Reported-by: wannacu <wannacu2049@gmail.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
----
- include/tcg/tcg-temp-internal.h | 6 ++++++
- accel/tcg/plugin-gen.c          | 2 +-
- tcg/tcg.c                       | 5 ++++-
-files changed, 11 insertions(+), 2 deletions(-)
-diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg-temp-internal.h
-+++ b/include/tcg/tcg-temp-internal.h
-@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
- TCGv_ptr tcg_temp_ebb_new_ptr(void);
- TCGv_i128 tcg_temp_ebb_new_i128(void);
-+/* Forget all freed EBB temps, so that new allocations produce new temps. */
-+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
-+{
-+    memset(s->free_temps, 0, sizeof(s->free_temps));
-+}
-+
- #endif /* TCG_TEMP_FREE_H */
-diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
-index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/plugin-gen.c
-+++ b/accel/tcg/plugin-gen.c
-@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
-      * that might be live within the existing opcode stream.
-      * The simplest solution is to release them all and create new.
-      */
--    memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
-+    tcg_temp_ebb_reset_freed(tcg_ctx);
-     QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
-         switch (op->opc) {
-diff --git a/tcg/tcg.c b/tcg/tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.c
-+++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
-     s->nb_temps = s->nb_globals;
-     /* No temps have been previously allocated for size or locality.  */
--    memset(s->free_temps, 0, sizeof(s->free_temps));
-+    tcg_temp_ebb_reset_freed(s);
-     /* No constant temps have been previously allocated. */
-     for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
-@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
-     }
- #endif
-+    /* Do not reuse any EBB that may be allocated within the TB. */
-+    tcg_temp_ebb_reset_freed(s);
-+
-     tcg_optimize(s);
-     reachable_code_pass(s);
---
-.43.0

-[PULL 2/4] tcg/riscv: Fix StoreStore barrier generation
+Deleted patch
-From: Roman Artemev <roman.artemev@syntacore.com>
-On RISC-V to StoreStore barrier corresponds
-`fence w, w` not `fence r, r`
-Cc: qemu-stable@nongnu.org
-Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
-Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
-Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/riscv/tcg-target.c.inc | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/riscv/tcg-target.c.inc
-+++ b/tcg/riscv/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
-         insn |= 0x02100000;
-     }
-     if (a0 & TCG_MO_ST_ST) {
--        insn |= 0x02200000;
-+        insn |= 0x01100000;
-     }
-     tcg_out32(s, insn);
- }
---
-.43.0

-[PULL 3/4] include/exec: Introduce fpst alias in helper-head.h.inc
+[PULL v3 73/91] target/arm: Improve trans_BFCI
-This allows targets to declare that the helper requires a
+Reorg temporary usage so that we can use tcg_constant_i32.
-float_status pointer and instead of a generic void pointer.
+tcg_gen_deposit_i32 already has a width == 32 special case,
 so remove the check here.
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- include/exec/helper-head.h.inc | 3 +++
+ target/arm/tcg/translate.c | 14 ++++++--------
-file changed, 3 insertions(+)
+file changed, 6 insertions(+), 8 deletions(-)
-diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
+diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/exec/helper-head.h.inc
+--- a/target/arm/tcg/translate.c
-+++ b/include/exec/helper-head.h.inc
++++ b/target/arm/tcg/translate.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static bool trans_UBFX(DisasContext *s, arg_UBFX *a)
- #define dh_alias_ptr ptr
- #define dh_alias_cptr ptr
+ static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
- #define dh_alias_env ptr
+ {
-+#define dh_alias_fpst ptr
+-    TCGv_i32 tmp;
- #define dh_alias_void void
+     int msb = a->msb, lsb = a->lsb;
- #define dh_alias_noreturn noreturn
++    TCGv_i32 t_in, t_rd;
- #define dh_alias(t) glue(dh_alias_, t)
+     int width;
-@@ -XXX,XX +XXX,XX @@
- #define dh_ctype_ptr void *
+     if (!ENABLE_ARCH_6T2) {
- #define dh_ctype_cptr const void *
+@@ -XXX,XX +XXX,XX @@ static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
- #define dh_ctype_env CPUArchState *
+     width = msb + 1 - lsb;
-+#define dh_ctype_fpst float_status *
+     if (a->rn == 15) {
- #define dh_ctype_void void
+         /* BFC */
- #define dh_ctype_noreturn G_NORETURN void
+-        tmp = tcg_const_i32(0);
- #define dh_ctype(t) dh_ctype_##t
++        t_in = tcg_constant_i32(0);
-@@ -XXX,XX +XXX,XX @@
+     } else {
- #define dh_typecode_f64 dh_typecode_i64
+         /* BFI */
- #define dh_typecode_cptr dh_typecode_ptr
+-        tmp = load_reg(s, a->rn);
- #define dh_typecode_env dh_typecode_ptr
++        t_in = load_reg(s, a->rn);
-+#define dh_typecode_fpst dh_typecode_ptr
+     }
- #define dh_typecode(t) dh_typecode_##t
+-    if (width != 32) {
+-        TCGv_i32 tmp2 = load_reg(s, a->rd);
- #define dh_callflag_i32  0
+-        tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width);
 -    }
 -    store_reg(s, a->rd, tmp);
 +    t_rd = load_reg(s, a->rd);
 +    tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width);
 +    store_reg(s, a->rd, t_rd);
      return true;
  }
 --
-.43.0
+.34.1

-[PULL 4/4] target/sparc: Use memcpy() and remove memcpy32()
+Deleted patch
-From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Rather than manually copying each register, use
-the libc memcpy(), which is well optimized nowadays.
-Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
-Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-ID: <20241205205418.67613-1-philmd@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- target/sparc/win_helper.c | 26 ++++++++------------------
-file changed, 8 insertions(+), 18 deletions(-)
-diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/sparc/win_helper.c
-+++ b/target/sparc/win_helper.c
-@@ -XXX,XX +XXX,XX @@
- #include "exec/helper-proto.h"
- #include "trace.h"
--static inline void memcpy32(target_ulong *dst, const target_ulong *src)
--{
--    dst[0] = src[0];
--    dst[1] = src[1];
--    dst[2] = src[2];
--    dst[3] = src[3];
--    dst[4] = src[4];
--    dst[5] = src[5];
--    dst[6] = src[6];
--    dst[7] = src[7];
--}
--
- void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
- {
-     /* put the modified wrap registers at their proper location */
-     if (env->cwp == env->nwindows - 1) {
--        memcpy32(env->regbase, env->regbase + env->nwindows * 16);
-+        memcpy(env->regbase, env->regbase + env->nwindows * 16,
-+               sizeof(env->gregs));
-     }
-     env->cwp = new_cwp;
-     /* put the wrap registers at their temporary location */
-     if (new_cwp == env->nwindows - 1) {
--        memcpy32(env->regbase + env->nwindows * 16, env->regbase);
-+        memcpy(env->regbase + env->nwindows * 16, env->regbase,
-+               sizeof(env->gregs));
-     }
-     env->regwptr = env->regbase + (new_cwp * 16);
- }
-@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
-     dst = get_gl_gregset(env, env->gl);
-     if (src != dst) {
--        memcpy32(dst, env->gregs);
--        memcpy32(env->gregs, src);
-+        memcpy(dst, env->gregs, sizeof(env->gregs));
-+        memcpy(env->gregs, src, sizeof(env->gregs));
-     }
- }
-@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
-         /* Switch global register bank */
-         src = get_gregset(env, new_pstate_regs);
-         dst = get_gregset(env, pstate_regs);
--        memcpy32(dst, env->gregs);
--        memcpy32(env->gregs, src);
-+        memcpy(dst, env->gregs, sizeof(env->gregs));
-+        memcpy(env->gregs, src, sizeof(env->gregs));
-     } else {
-         trace_win_helper_no_switch_pstate(new_pstate_regs);
-     }
---
-.43.0

Pretty small still, but there are two patches that ought
to get backported to stable, so no point in delaying.

The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:

Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212

for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:

target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)

----------------------------------------------------------------
tcg: Reset free_temps before tcg_optimize
tcg/riscv: Fix StoreStore barrier generation
include/exec: Introduce fpst alias in helper-head.h.inc
target/sparc: Use memcpy() and remove memcpy32()

----------------------------------------------------------------
Philippe Mathieu-Daudé (1):
      target/sparc: Use memcpy() and remove memcpy32()

Richard Henderson (2):
      tcg: Reset free_temps before tcg_optimize
      include/exec: Introduce fpst alias in helper-head.h.inc

Roman Artemev (1):
      tcg/riscv: Fix StoreStore barrier generation

When allocating new temps during tcg_optmize, do not re-use
any EBB temps that were used within the TB.  We do not have
any idea what span of the TB in which the temp was live.

Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
as well as replacing the equivalent in plugin_gen_inject and
tcg_func_start.

Cc: qemu-stable@nongnu.org
Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
Reported-by: wannacu <wannacu2049@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/tcg/tcg-temp-internal.h | 6 ++++++
 accel/tcg/plugin-gen.c          | 2 +-
 tcg/tcg.c                       | 5 ++++-
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-temp-internal.h
+++ b/include/tcg/tcg-temp-internal.h
@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
 TCGv_ptr tcg_temp_ebb_new_ptr(void);
 TCGv_i128 tcg_temp_ebb_new_i128(void);
 
+/* Forget all freed EBB temps, so that new allocations produce new temps. */
+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
+{
+    memset(s->free_temps, 0, sizeof(s->free_temps));
+}
+
 #endif /* TCG_TEMP_FREE_H */
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
      * that might be live within the existing opcode stream.
      * The simplest solution is to release them all and create new.
      */
-    memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
+    tcg_temp_ebb_reset_freed(tcg_ctx);
 
     QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
         switch (op->opc) {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
     s->nb_temps = s->nb_globals;
 
     /* No temps have been previously allocated for size or locality.  */
-    memset(s->free_temps, 0, sizeof(s->free_temps));
+    tcg_temp_ebb_reset_freed(s);
 
     /* No constant temps have been previously allocated. */
     for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
     }
 #endif
 
+    /* Do not reuse any EBB that may be allocated within the TB. */
+    tcg_temp_ebb_reset_freed(s);
+
     tcg_optimize(s);
 
     reachable_code_pass(s);
-- 
2.43.0

From: Roman Artemev <roman.artemev@syntacore.com>

On RISC-V to StoreStore barrier corresponds
`fence w, w` not `fence r, r`

Cc: qemu-stable@nongnu.org
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/riscv/tcg-target.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
         insn |= 0x02100000;
     }
     if (a0 & TCG_MO_ST_ST) {
-        insn |= 0x02200000;
+        insn |= 0x01100000;
     }
     tcg_out32(s, insn);
 }
-- 
2.43.0

This allows targets to declare that the helper requires a
float_status pointer and instead of a generic void pointer.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/helper-head.h.inc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/helper-head.h.inc
+++ b/include/exec/helper-head.h.inc
@@ -XXX,XX +XXX,XX @@
 #define dh_alias_ptr ptr
 #define dh_alias_cptr ptr
 #define dh_alias_env ptr
+#define dh_alias_fpst ptr
 #define dh_alias_void void
 #define dh_alias_noreturn noreturn
 #define dh_alias(t) glue(dh_alias_, t)
@@ -XXX,XX +XXX,XX @@
 #define dh_ctype_ptr void *
 #define dh_ctype_cptr const void *
 #define dh_ctype_env CPUArchState *
+#define dh_ctype_fpst float_status *
 #define dh_ctype_void void
 #define dh_ctype_noreturn G_NORETURN void
 #define dh_ctype(t) dh_ctype_##t
@@ -XXX,XX +XXX,XX @@
 #define dh_typecode_f64 dh_typecode_i64
 #define dh_typecode_cptr dh_typecode_ptr
 #define dh_typecode_env dh_typecode_ptr
+#define dh_typecode_fpst dh_typecode_ptr
 #define dh_typecode(t) dh_typecode_##t
 
 #define dh_callflag_i32  0
-- 
2.43.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Rather than manually copying each register, use
the libc memcpy(), which is well optimized nowadays.

Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20241205205418.67613-1-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/win_helper.c | 26 ++++++++------------------
 1 file changed, 8 insertions(+), 18 deletions(-)

diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sparc/win_helper.c
+++ b/target/sparc/win_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-proto.h"
 #include "trace.h"
 
-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
-{
-    dst[0] = src[0];
-    dst[1] = src[1];
-    dst[2] = src[2];
-    dst[3] = src[3];
-    dst[4] = src[4];
-    dst[5] = src[5];
-    dst[6] = src[6];
-    dst[7] = src[7];
-}
-
 void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
 {
     /* put the modified wrap registers at their proper location */
     if (env->cwp == env->nwindows - 1) {
-        memcpy32(env->regbase, env->regbase + env->nwindows * 16);
+        memcpy(env->regbase, env->regbase + env->nwindows * 16,
+               sizeof(env->gregs));
     }
     env->cwp = new_cwp;
 
     /* put the wrap registers at their temporary location */
     if (new_cwp == env->nwindows - 1) {
-        memcpy32(env->regbase + env->nwindows * 16, env->regbase);
+        memcpy(env->regbase + env->nwindows * 16, env->regbase,
+               sizeof(env->gregs));
     }
     env->regwptr = env->regbase + (new_cwp * 16);
 }
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
     dst = get_gl_gregset(env, env->gl);
 
     if (src != dst) {
-        memcpy32(dst, env->gregs);
-        memcpy32(env->gregs, src);
+        memcpy(dst, env->gregs, sizeof(env->gregs));
+        memcpy(env->gregs, src, sizeof(env->gregs));
     }
 }
 
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
         /* Switch global register bank */
         src = get_gregset(env, new_pstate_regs);
         dst = get_gregset(env, pstate_regs);
-        memcpy32(dst, env->gregs);
-        memcpy32(env->gregs, src);
+        memcpy(dst, env->gregs, sizeof(env->gregs));
+        memcpy(env->gregs, src, sizeof(env->gregs));
     } else {
         trace_win_helper_no_switch_pstate(new_pstate_regs);
     }
-- 
2.43.0

Version 3 fixes a rebase error from v2 affecting ARM BFC insn.

The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517:

Merge tag 'linux-user-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2023-03-12 10:57:00 +0000)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230313

for you to fetch changes up to 0c8b6b9a6383e2e37ff3d1d12b40c58b7ed36c1c:

tcg: Drop tcg_const_* (2023-03-13 07:03:39 -0700)

----------------------------------------------------------------
accel/tcg: Fix NB_MMU_MODES to 16
Balance of the target/ patchset which eliminates tcg_temp_free
Balance of the target/ patchset which eliminates tcg_const

----------------------------------------------------------------
Anton Johansson (23):
      include/exec: Set default `NB_MMU_MODES` to 16
      target/alpha: Remove `NB_MMU_MODES` define
      target/arm: Remove `NB_MMU_MODES` define
      target/avr: Remove `NB_MMU_MODES` define
      target/cris: Remove `NB_MMU_MODES` define
      target/hexagon: Remove `NB_MMU_MODES` define
      target/hppa: Remove `NB_MMU_MODES` define
      target/i386: Remove `NB_MMU_MODES` define
      target/loongarch: Remove `NB_MMU_MODES` define
      target/m68k: Remove `NB_MMU_MODES` define
      target/microblaze: Remove `NB_MMU_MODES` define
      target/mips: Remove `NB_MMU_MODES` define
      target/nios2: Remove `NB_MMU_MODES` define
      target/openrisc: Remove `NB_MMU_MODES` define
      target/ppc: Remove `NB_MMU_MODES` define
      target/riscv: Remove `NB_MMU_MODES` define
      target/rx: Remove `NB_MMU_MODES` define
      target/s390x: Remove `NB_MMU_MODES` define
      target/sh4: Remove `NB_MMU_MODES` define
      target/sparc: Remove `NB_MMU_MODES` define
      target/tricore: Remove `NB_MMU_MODES` define
      target/xtensa: Remove `NB_MMU_MODES` define
      include/exec: Remove guards around `NB_MMU_MODES`

Richard Henderson (68):
      target/mips: Drop tcg_temp_free from micromips_translate.c.inc
      target/mips: Drop tcg_temp_free from msa_translate.c
      target/mips: Drop tcg_temp_free from mxu_translate.c
      target/mips: Drop tcg_temp_free from nanomips_translate.c.inc
      target/mips: Drop tcg_temp_free from octeon_translate.c
      target/mips: Drop tcg_temp_free from translate_addr_const.c
      target/mips: Drop tcg_temp_free from tx79_translate.c
      target/mips: Drop tcg_temp_free from vr54xx_translate.c
      target/mips: Drop tcg_temp_free from translate.c
      target/s390x: Drop free_compare
      target/s390x: Drop tcg_temp_free from translate_vx.c.inc
      target/s390x: Drop tcg_temp_free from translate.c
      target/s390x: Remove assert vs g_in2
      target/s390x: Remove g_out, g_out2, g_in1, g_in2 from DisasContext
      tcg: Create tcg/tcg-temp-internal.h
      target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS
      target/avr: Avoid use of tcg_const_i32 throughout
      target/cris: Avoid use of tcg_const_i32 throughout
      target/hppa: Avoid tcg_const_i64 in trans_fid_f
      target/hppa: Avoid use of tcg_const_i32 throughout
      target/i386: Avoid use of tcg_const_* throughout
      target/m68k: Avoid tcg_const_i32 when modified
      target/m68k: Avoid tcg_const_i32 in bfop_reg
      target/m68k: Avoid tcg_const_* throughout
      target/mips: Split out gen_lxl
      target/mips: Split out gen_lxr
      target/mips: Avoid tcg_const_tl in gen_r6_ld
      target/mips: Avoid tcg_const_* throughout
      target/ppc: Split out gen_vx_vmul10
      target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad
      target/rx: Use tcg_gen_abs_i32
      target/rx: Use cpu_psw_z as temp in flags computation
      target/rx: Avoid tcg_const_i32 when new temp needed
      target/rx: Avoid tcg_const_i32
      target/s390x: Avoid tcg_const_i64
      target/sh4: Avoid tcg_const_i32 for TAS.B
      target/sh4: Avoid tcg_const_i32
      tcg/sparc: Avoid tcg_const_tl in gen_edge
      target/tricore: Split t_n as constant from temp as variable
      target/tricore: Rename t_off10 and use tcg_constant_i32
      target/tricore: Use setcondi instead of explicit allocation
      target/tricore: Drop some temp initialization
      target/tricore: Avoid tcg_const_i32
      tcg: Replace tcg_const_i64 in tcg-op.c
      target/arm: Use rmode >= 0 for need_rmode
      target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf
      target/arm: Improve arm_rmode_to_sf
      target/arm: Consistently use ARMFPRounding during translation
      target/arm: Create gen_set_rmode, gen_restore_rmode
      target/arm: Improve trans_BFCI
      target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
      target/arm: Avoid tcg_const_* in translate-mve.c
      target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
      target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
      target/arm: Avoid tcg_const_ptr in handle_rev
      target/m68k: Use tcg_constant_i32 in gen_ea_mode
      target/ppc: Avoid tcg_const_i64 in do_vcntmb
      target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
      target/ppc: Avoid tcg_const_* in xxeval
      target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
      target/ppc: Avoid tcg_const_* in fp-impl.c.inc
      target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
      target/ppc: Rewrite trans_ADDG6S
      target/ppc: Fix gen_tlbsx_booke206
      target/ppc: Avoid tcg_const_* in translate.c
      target/tricore: Use min/max for saturate
      tcg: Drop tcg_const_*_vec
      tcg: Drop tcg_const_*

Reorg temporary usage so that we can use tcg_constant_i32.
tcg_gen_deposit_i32 already has a width == 32 special case,
so remove the check here.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/tcg/translate.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_UBFX(DisasContext *s, arg_UBFX *a)
 
 static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
 {
-    TCGv_i32 tmp;
     int msb = a->msb, lsb = a->lsb;
+    TCGv_i32 t_in, t_rd;
     int width;
 
     if (!ENABLE_ARCH_6T2) {
@@ -XXX,XX +XXX,XX @@ static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
     width = msb + 1 - lsb;
     if (a->rn == 15) {
         /* BFC */
-        tmp = tcg_const_i32(0);
+        t_in = tcg_constant_i32(0);
     } else {
         /* BFI */
-        tmp = load_reg(s, a->rn);
+        t_in = load_reg(s, a->rn);
     }
-    if (width != 32) {
-        TCGv_i32 tmp2 = load_reg(s, a->rd);
-        tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width);
-    }
-    store_reg(s, a->rd, tmp);
+    t_rd = load_reg(s, a->rd);
+    tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width);
+    store_reg(s, a->rd, t_rd);
     return true;
 }
 
-- 
2.34.1