1
Pretty small still, but there are two patches that ought
1
The following changes since commit 79b677d658d3d35e1e776826ac4abb28cdce69b8:
2
to get backported to stable, so no point in delaying.
3
2
4
r~
3
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2023-02-21 11:28:31 +0000)
5
6
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
7
8
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
9
4
10
are available in the Git repository at:
5
are available in the Git repository at:
11
6
12
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230221
13
8
14
for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:
9
for you to fetch changes up to dbd672c87f19949bb62bfb1fb3a97b9729fd7560:
15
10
16
target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)
11
sysemu/os-win32: fix setjmp/longjmp on windows-arm64 (2023-02-21 13:45:48 -1000)
17
12
18
----------------------------------------------------------------
13
----------------------------------------------------------------
19
tcg: Reset free_temps before tcg_optimize
14
tcg: Allow first half of insn in ram, and second half in mmio
20
tcg/riscv: Fix StoreStore barrier generation
15
linux-user/sparc: SIGILL for unknown trap vectors
21
include/exec: Introduce fpst alias in helper-head.h.inc
16
linux-user/microblaze: SIGILL for privileged insns
22
target/sparc: Use memcpy() and remove memcpy32()
17
linux-user: Fix deadlock while exiting due to signal
18
target/microblaze: Add gdbstub xml
19
util: Adjust cacheflush for windows-arm64
20
include/sysemu/os-win32: Adjust setjmp/longjmp for windows-arm64
23
21
24
----------------------------------------------------------------
22
----------------------------------------------------------------
25
Philippe Mathieu-Daudé (1):
23
Ilya Leoshkevich (3):
26
target/sparc: Use memcpy() and remove memcpy32()
24
linux-user: Always exit from exclusive state in fork_end()
25
cpus: Make {start,end}_exclusive() recursive
26
linux-user/microblaze: Handle privileged exception
27
27
28
Richard Henderson (2):
28
Pierrick Bouvier (2):
29
tcg: Reset free_temps before tcg_optimize
29
util/cacheflush: fix cache on windows-arm64
30
include/exec: Introduce fpst alias in helper-head.h.inc
30
sysemu/os-win32: fix setjmp/longjmp on windows-arm64
31
31
32
Roman Artemev (1):
32
Richard Henderson (3):
33
tcg/riscv: Fix StoreStore barrier generation
33
accel/tcg: Allow the second page of an instruction to be MMIO
34
linux-user/sparc: Raise SIGILL for all unhandled software traps
35
target/microblaze: Add gdbstub xml
34
36
35
include/tcg/tcg-temp-internal.h | 6 ++++++
37
include/hw/core/cpu.h | 4 +-
36
accel/tcg/plugin-gen.c | 2 +-
38
include/sysemu/os-win32.h | 28 ++++++++++--
37
target/sparc/win_helper.c | 26 ++++++++------------------
39
target/microblaze/cpu.h | 2 +
38
tcg/tcg.c | 5 ++++-
40
accel/tcg/translator.c | 12 +++++-
39
include/exec/helper-head.h.inc | 3 +++
41
cpus-common.c | 12 +++++-
40
tcg/riscv/tcg-target.c.inc | 2 +-
42
linux-user/main.c | 10 +++--
41
6 files changed, 23 insertions(+), 21 deletions(-)
43
linux-user/microblaze/cpu_loop.c | 10 ++++-
42
44
linux-user/sparc/cpu_loop.c | 8 ++++
45
linux-user/syscall.c | 1 +
46
target/microblaze/cpu.c | 7 ++-
47
target/microblaze/gdbstub.c | 51 ++++++++++++++++------
48
util/cacheflush.c | 14 ++++--
49
configs/targets/microblaze-linux-user.mak | 1 +
50
configs/targets/microblaze-softmmu.mak | 1 +
51
configs/targets/microblazeel-linux-user.mak | 1 +
52
configs/targets/microblazeel-softmmu.mak | 1 +
53
gdb-xml/microblaze-core.xml | 67 +++++++++++++++++++++++++++++
54
gdb-xml/microblaze-stack-protect.xml | 12 ++++++
55
meson.build | 21 +++++++++
56
19 files changed, 229 insertions(+), 34 deletions(-)
57
create mode 100644 gdb-xml/microblaze-core.xml
58
create mode 100644 gdb-xml/microblaze-stack-protect.xml
diff view generated by jsdifflib
1
When allocating new temps during tcg_optmize, do not re-use
1
If an instruction straddles a page boundary, and the first page
2
any EBB temps that were used within the TB. We do not have
2
was ram, but the second page was MMIO, we would abort. Handle
3
any idea what span of the TB in which the temp was live.
3
this as if both pages are MMIO, by setting the ram_addr_t for
4
the first page to -1.
4
5
5
Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
6
Reported-by: Sid Manning <sidneym@quicinc.com>
6
as well as replacing the equivalent in plugin_gen_inject and
7
Reported-by: Jørgen Hansen <Jorgen.Hansen@wdc.com>
7
tcg_func_start.
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
accel/tcg/translator.c | 12 ++++++++++--
12
1 file changed, 10 insertions(+), 2 deletions(-)
8
13
9
Cc: qemu-stable@nongnu.org
14
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
10
Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
11
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
12
Reported-by: wannacu <wannacu2049@gmail.com>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
---
17
include/tcg/tcg-temp-internal.h | 6 ++++++
18
accel/tcg/plugin-gen.c | 2 +-
19
tcg/tcg.c | 5 ++++-
20
3 files changed, 11 insertions(+), 2 deletions(-)
21
22
diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
23
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
24
--- a/include/tcg/tcg-temp-internal.h
16
--- a/accel/tcg/translator.c
25
+++ b/include/tcg/tcg-temp-internal.h
17
+++ b/accel/tcg/translator.c
26
@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
18
@@ -XXX,XX +XXX,XX @@ static void *translator_access(CPUArchState *env, DisasContextBase *db,
27
TCGv_ptr tcg_temp_ebb_new_ptr(void);
19
if (host == NULL) {
28
TCGv_i128 tcg_temp_ebb_new_i128(void);
20
tb_page_addr_t phys_page =
29
21
get_page_addr_code_hostp(env, base, &db->host_addr[1]);
30
+/* Forget all freed EBB temps, so that new allocations produce new temps. */
22
- /* We cannot handle MMIO as second page. */
31
+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
23
- assert(phys_page != -1);
32
+{
33
+ memset(s->free_temps, 0, sizeof(s->free_temps));
34
+}
35
+
24
+
36
#endif /* TCG_TEMP_FREE_H */
25
+ /*
37
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
26
+ * If the second page is MMIO, treat as if the first page
38
index XXXXXXX..XXXXXXX 100644
27
+ * was MMIO as well, so that we do not cache the TB.
39
--- a/accel/tcg/plugin-gen.c
28
+ */
40
+++ b/accel/tcg/plugin-gen.c
29
+ if (unlikely(phys_page == -1)) {
41
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
30
+ tb_set_page_addr0(tb, -1);
42
* that might be live within the existing opcode stream.
31
+ return NULL;
43
* The simplest solution is to release them all and create new.
32
+ }
44
*/
45
- memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
46
+ tcg_temp_ebb_reset_freed(tcg_ctx);
47
48
QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
49
switch (op->opc) {
50
diff --git a/tcg/tcg.c b/tcg/tcg.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/tcg/tcg.c
53
+++ b/tcg/tcg.c
54
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
55
s->nb_temps = s->nb_globals;
56
57
/* No temps have been previously allocated for size or locality. */
58
- memset(s->free_temps, 0, sizeof(s->free_temps));
59
+ tcg_temp_ebb_reset_freed(s);
60
61
/* No constant temps have been previously allocated. */
62
for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
63
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
64
}
65
#endif
66
67
+ /* Do not reuse any EBB that may be allocated within the TB. */
68
+ tcg_temp_ebb_reset_freed(s);
69
+
33
+
70
tcg_optimize(s);
34
tb_set_page_addr1(tb, phys_page);
71
35
#ifdef CONFIG_USER_ONLY
72
reachable_code_pass(s);
36
page_protect(end);
73
--
37
--
74
2.43.0
38
2.34.1
75
39
76
40
diff view generated by jsdifflib
New patch
1
The linux kernel's trap tables vector all unassigned trap
2
numbers to BAD_TRAP, which then raises SIGILL.
1
3
4
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
5
Reported-by: Ilya Leoshkevich <iii@linux.ibm.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
linux-user/sparc/cpu_loop.c | 8 ++++++++
9
1 file changed, 8 insertions(+)
10
11
diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/linux-user/sparc/cpu_loop.c
14
+++ b/linux-user/sparc/cpu_loop.c
15
@@ -XXX,XX +XXX,XX @@ void cpu_loop (CPUSPARCState *env)
16
cpu_exec_step_atomic(cs);
17
break;
18
default:
19
+ /*
20
+ * Most software trap numbers vector to BAD_TRAP.
21
+ * Handle anything not explicitly matched above.
22
+ */
23
+ if (trapnr >= TT_TRAP && trapnr <= TT_TRAP + 0x7f) {
24
+ force_sig_fault(TARGET_SIGILL, ILL_ILLTRP, env->pc);
25
+ break;
26
+ }
27
fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
28
cpu_dump_state(cs, stderr, 0);
29
exit(EXIT_FAILURE);
30
--
31
2.34.1
diff view generated by jsdifflib
1
From: Roman Artemev <roman.artemev@syntacore.com>
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
2
2
3
On RISC-V to StoreStore barrier corresponds
3
fork()ed processes currently start with
4
`fence w, w` not `fence r, r`
4
current_cpu->in_exclusive_context set, which is, strictly speaking, not
5
correct, but does not cause problems (even assertion failures).
5
6
6
Cc: qemu-stable@nongnu.org
7
With one of the next patches, the code begins to rely on this value, so
7
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
8
fix it by always calling end_exclusive() in fork_end().
9
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
12
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
11
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
13
Message-Id: <20230214140829.45392-2-iii@linux.ibm.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
15
---
14
tcg/riscv/tcg-target.c.inc | 2 +-
16
linux-user/main.c | 10 ++++++----
15
1 file changed, 1 insertion(+), 1 deletion(-)
17
linux-user/syscall.c | 1 +
18
2 files changed, 7 insertions(+), 4 deletions(-)
16
19
17
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
20
diff --git a/linux-user/main.c b/linux-user/main.c
18
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
19
--- a/tcg/riscv/tcg-target.c.inc
22
--- a/linux-user/main.c
20
+++ b/tcg/riscv/tcg-target.c.inc
23
+++ b/linux-user/main.c
21
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
24
@@ -XXX,XX +XXX,XX @@ void fork_end(int child)
22
insn |= 0x02100000;
25
}
26
qemu_init_cpu_list();
27
gdbserver_fork(thread_cpu);
28
- /* qemu_init_cpu_list() takes care of reinitializing the
29
- * exclusive state, so we don't need to end_exclusive() here.
30
- */
31
} else {
32
cpu_list_unlock();
33
- end_exclusive();
23
}
34
}
24
if (a0 & TCG_MO_ST_ST) {
35
+ /*
25
- insn |= 0x02200000;
36
+ * qemu_init_cpu_list() reinitialized the child exclusive state, but we
26
+ insn |= 0x01100000;
37
+ * also need to keep current_cpu consistent, so call end_exclusive() for
38
+ * both child and parent.
39
+ */
40
+ end_exclusive();
41
}
42
43
__thread CPUState *thread_cpu;
44
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/linux-user/syscall.c
47
+++ b/linux-user/syscall.c
48
@@ -XXX,XX +XXX,XX @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,
49
cpu_clone_regs_parent(env, flags);
50
fork_end(0);
51
}
52
+ g_assert(!cpu_in_exclusive_context(cpu));
27
}
53
}
28
tcg_out32(s, insn);
54
return ret;
29
}
55
}
30
--
56
--
31
2.43.0
57
2.34.1
58
59
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
2
2
3
Rather than manually copying each register, use
3
Currently dying to one of the core_dump_signal()s deadlocks, because
4
the libc memcpy(), which is well optimized nowadays.
4
dump_core_and_abort() calls start_exclusive() two times: first via
5
stop_all_tasks(), and then via preexit_cleanup() ->
6
qemu_plugin_user_exit().
5
7
6
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
8
There are a number of ways to solve this: resume after dumping core;
7
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
9
check cpu_in_exclusive_context() in qemu_plugin_user_exit(); or make
10
{start,end}_exclusive() recursive. Pick the last option, since it's
11
the most straightforward one.
12
13
Fixes: da91c1920242 ("linux-user: Clean up when exiting due to a signal")
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-ID: <20241205205418.67613-1-philmd@linaro.org>
16
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
17
Message-Id: <20230214140829.45392-3-iii@linux.ibm.com>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
18
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
19
---
13
target/sparc/win_helper.c | 26 ++++++++------------------
20
include/hw/core/cpu.h | 4 ++--
14
1 file changed, 8 insertions(+), 18 deletions(-)
21
cpus-common.c | 12 ++++++++++--
22
2 files changed, 12 insertions(+), 4 deletions(-)
15
23
16
diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
24
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
17
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
18
--- a/target/sparc/win_helper.c
26
--- a/include/hw/core/cpu.h
19
+++ b/target/sparc/win_helper.c
27
+++ b/include/hw/core/cpu.h
20
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@ struct CPUState {
21
#include "exec/helper-proto.h"
29
bool unplug;
22
#include "trace.h"
30
bool crash_occurred;
23
31
bool exit_request;
24
-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
32
- bool in_exclusive_context;
25
-{
33
+ int exclusive_context_count;
26
- dst[0] = src[0];
34
uint32_t cflags_next_tb;
27
- dst[1] = src[1];
35
/* updates protected by BQL */
28
- dst[2] = src[2];
36
uint32_t interrupt_request;
29
- dst[3] = src[3];
37
@@ -XXX,XX +XXX,XX @@ void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data
30
- dst[4] = src[4];
38
*/
31
- dst[5] = src[5];
39
static inline bool cpu_in_exclusive_context(const CPUState *cpu)
32
- dst[6] = src[6];
33
- dst[7] = src[7];
34
-}
35
-
36
void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
37
{
40
{
38
/* put the modified wrap registers at their proper location */
41
- return cpu->in_exclusive_context;
39
if (env->cwp == env->nwindows - 1) {
42
+ return cpu->exclusive_context_count;
40
- memcpy32(env->regbase, env->regbase + env->nwindows * 16);
41
+ memcpy(env->regbase, env->regbase + env->nwindows * 16,
42
+ sizeof(env->gregs));
43
}
44
env->cwp = new_cwp;
45
46
/* put the wrap registers at their temporary location */
47
if (new_cwp == env->nwindows - 1) {
48
- memcpy32(env->regbase + env->nwindows * 16, env->regbase);
49
+ memcpy(env->regbase + env->nwindows * 16, env->regbase,
50
+ sizeof(env->gregs));
51
}
52
env->regwptr = env->regbase + (new_cwp * 16);
53
}
43
}
54
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
44
55
dst = get_gl_gregset(env, env->gl);
45
/**
56
46
diff --git a/cpus-common.c b/cpus-common.c
57
if (src != dst) {
47
index XXXXXXX..XXXXXXX 100644
58
- memcpy32(dst, env->gregs);
48
--- a/cpus-common.c
59
- memcpy32(env->gregs, src);
49
+++ b/cpus-common.c
60
+ memcpy(dst, env->gregs, sizeof(env->gregs));
50
@@ -XXX,XX +XXX,XX @@ void start_exclusive(void)
61
+ memcpy(env->gregs, src, sizeof(env->gregs));
51
CPUState *other_cpu;
62
}
52
int running_cpus;
53
54
+ if (current_cpu->exclusive_context_count) {
55
+ current_cpu->exclusive_context_count++;
56
+ return;
57
+ }
58
+
59
qemu_mutex_lock(&qemu_cpu_list_lock);
60
exclusive_idle();
61
62
@@ -XXX,XX +XXX,XX @@ void start_exclusive(void)
63
*/
64
qemu_mutex_unlock(&qemu_cpu_list_lock);
65
66
- current_cpu->in_exclusive_context = true;
67
+ current_cpu->exclusive_context_count = 1;
63
}
68
}
64
69
65
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
70
/* Finish an exclusive operation. */
66
/* Switch global register bank */
71
void end_exclusive(void)
67
src = get_gregset(env, new_pstate_regs);
72
{
68
dst = get_gregset(env, pstate_regs);
73
- current_cpu->in_exclusive_context = false;
69
- memcpy32(dst, env->gregs);
74
+ current_cpu->exclusive_context_count--;
70
- memcpy32(env->gregs, src);
75
+ if (current_cpu->exclusive_context_count) {
71
+ memcpy(dst, env->gregs, sizeof(env->gregs));
76
+ return;
72
+ memcpy(env->gregs, src, sizeof(env->gregs));
77
+ }
73
} else {
78
74
trace_win_helper_no_switch_pstate(new_pstate_regs);
79
qemu_mutex_lock(&qemu_cpu_list_lock);
75
}
80
qatomic_set(&pending_cpus, 0);
76
--
81
--
77
2.43.0
82
2.34.1
78
83
79
84
diff view generated by jsdifflib
New patch
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
1
2
3
Follow what kernel's full_exception() is doing.
4
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
7
Message-Id: <20230214140829.45392-4-iii@linux.ibm.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
linux-user/microblaze/cpu_loop.c | 10 ++++++++--
11
1 file changed, 8 insertions(+), 2 deletions(-)
12
13
diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/linux-user/microblaze/cpu_loop.c
16
+++ b/linux-user/microblaze/cpu_loop.c
17
@@ -XXX,XX +XXX,XX @@
18
19
void cpu_loop(CPUMBState *env)
20
{
21
+ int trapnr, ret, si_code, sig;
22
CPUState *cs = env_cpu(env);
23
- int trapnr, ret, si_code;
24
25
while (1) {
26
cpu_exec_start(cs);
27
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUMBState *env)
28
env->iflags &= ~(IMM_FLAG | D_FLAG);
29
switch (env->esr & 31) {
30
case ESR_EC_DIVZERO:
31
+ sig = TARGET_SIGFPE;
32
si_code = TARGET_FPE_INTDIV;
33
break;
34
case ESR_EC_FPU:
35
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUMBState *env)
36
* if there's no recognized bit set. Possibly this
37
* implies that si_code is 0, but follow the structure.
38
*/
39
+ sig = TARGET_SIGFPE;
40
si_code = env->fsr;
41
if (si_code & FSR_IO) {
42
si_code = TARGET_FPE_FLTINV;
43
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUMBState *env)
44
si_code = TARGET_FPE_FLTRES;
45
}
46
break;
47
+ case ESR_EC_PRIVINSN:
48
+ sig = SIGILL;
49
+ si_code = ILL_PRVOPC;
50
+ break;
51
default:
52
fprintf(stderr, "Unhandled hw-exception: 0x%x\n",
53
env->esr & ESR_EC_MASK);
54
cpu_dump_state(cs, stderr, 0);
55
exit(EXIT_FAILURE);
56
}
57
- force_sig_fault(TARGET_SIGFPE, si_code, env->pc);
58
+ force_sig_fault(sig, si_code, env->pc);
59
break;
60
61
case EXCP_DEBUG:
62
--
63
2.34.1
diff view generated by jsdifflib
New patch
1
Mirroring the upstream gdb xml files, the two stack boundary
2
registers are separated out.
1
3
4
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
target/microblaze/cpu.h | 2 +
8
target/microblaze/cpu.c | 7 ++-
9
target/microblaze/gdbstub.c | 51 +++++++++++-----
10
configs/targets/microblaze-linux-user.mak | 1 +
11
configs/targets/microblaze-softmmu.mak | 1 +
12
configs/targets/microblazeel-linux-user.mak | 1 +
13
configs/targets/microblazeel-softmmu.mak | 1 +
14
gdb-xml/microblaze-core.xml | 67 +++++++++++++++++++++
15
gdb-xml/microblaze-stack-protect.xml | 12 ++++
16
9 files changed, 128 insertions(+), 15 deletions(-)
17
create mode 100644 gdb-xml/microblaze-core.xml
18
create mode 100644 gdb-xml/microblaze-stack-protect.xml
19
20
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/microblaze/cpu.h
23
+++ b/target/microblaze/cpu.h
24
@@ -XXX,XX +XXX,XX @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
25
MemTxAttrs *attrs);
26
int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
27
int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
28
+int mb_cpu_gdb_read_stack_protect(CPUArchState *cpu, GByteArray *buf, int reg);
29
+int mb_cpu_gdb_write_stack_protect(CPUArchState *cpu, uint8_t *buf, int reg);
30
31
static inline uint32_t mb_cpu_read_msr(const CPUMBState *env)
32
{
33
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/microblaze/cpu.c
36
+++ b/target/microblaze/cpu.c
37
@@ -XXX,XX +XXX,XX @@
38
#include "qemu/module.h"
39
#include "hw/qdev-properties.h"
40
#include "exec/exec-all.h"
41
+#include "exec/gdbstub.h"
42
#include "fpu/softfloat-helpers.h"
43
44
static const struct {
45
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_initfn(Object *obj)
46
CPUMBState *env = &cpu->env;
47
48
cpu_set_cpustate_pointers(cpu);
49
+ gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect,
50
+ mb_cpu_gdb_write_stack_protect, 2,
51
+ "microblaze-stack-protect.xml", 0);
52
53
set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
54
55
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
56
cc->sysemu_ops = &mb_sysemu_ops;
57
#endif
58
device_class_set_props(dc, mb_properties);
59
- cc->gdb_num_core_regs = 32 + 27;
60
+ cc->gdb_num_core_regs = 32 + 25;
61
+ cc->gdb_core_xml_file = "microblaze-core.xml";
62
63
cc->disas_set_info = mb_disas_set_info;
64
cc->tcg_ops = &mb_tcg_ops;
65
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/microblaze/gdbstub.c
68
+++ b/target/microblaze/gdbstub.c
69
@@ -XXX,XX +XXX,XX @@ enum {
70
GDB_PVR0 = 32 + 6,
71
GDB_PVR11 = 32 + 17,
72
GDB_EDR = 32 + 18,
73
- GDB_SLR = 32 + 25,
74
- GDB_SHR = 32 + 26,
75
+};
76
+
77
+enum {
78
+ GDB_SP_SHL,
79
+ GDB_SP_SHR,
80
};
81
82
int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
83
@@ -XXX,XX +XXX,XX @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
84
case GDB_EDR:
85
val = env->edr;
86
break;
87
- case GDB_SLR:
88
- val = env->slr;
89
- break;
90
- case GDB_SHR:
91
- val = env->shr;
92
- break;
93
default:
94
/* Other SRegs aren't modeled, so report a value of 0 */
95
val = 0;
96
@@ -XXX,XX +XXX,XX @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
97
return gdb_get_reg32(mem_buf, val);
98
}
99
100
+int mb_cpu_gdb_read_stack_protect(CPUMBState *env, GByteArray *mem_buf, int n)
101
+{
102
+ uint32_t val;
103
+
104
+ switch (n) {
105
+ case GDB_SP_SHL:
106
+ val = env->slr;
107
+ break;
108
+ case GDB_SP_SHR:
109
+ val = env->shr;
110
+ break;
111
+ default:
112
+ return 0;
113
+ }
114
+ return gdb_get_reg32(mem_buf, val);
115
+}
116
+
117
int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
118
{
119
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
120
@@ -XXX,XX +XXX,XX @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
121
case GDB_EDR:
122
env->edr = tmp;
123
break;
124
- case GDB_SLR:
125
- env->slr = tmp;
126
- break;
127
- case GDB_SHR:
128
- env->shr = tmp;
129
- break;
130
+ }
131
+ return 4;
132
+}
133
+
134
+int mb_cpu_gdb_write_stack_protect(CPUMBState *env, uint8_t *mem_buf, int n)
135
+{
136
+ switch (n) {
137
+ case GDB_SP_SHL:
138
+ env->slr = ldl_p(mem_buf);
139
+ break;
140
+ case GDB_SP_SHR:
141
+ env->shr = ldl_p(mem_buf);
142
+ break;
143
+ default:
144
+ return 0;
145
}
146
return 4;
147
}
148
diff --git a/configs/targets/microblaze-linux-user.mak b/configs/targets/microblaze-linux-user.mak
149
index XXXXXXX..XXXXXXX 100644
150
--- a/configs/targets/microblaze-linux-user.mak
151
+++ b/configs/targets/microblaze-linux-user.mak
152
@@ -XXX,XX +XXX,XX @@ TARGET_SYSTBL_ABI=common
153
TARGET_SYSTBL=syscall.tbl
154
TARGET_BIG_ENDIAN=y
155
TARGET_HAS_BFLT=y
156
+TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml
157
diff --git a/configs/targets/microblaze-softmmu.mak b/configs/targets/microblaze-softmmu.mak
158
index XXXXXXX..XXXXXXX 100644
159
--- a/configs/targets/microblaze-softmmu.mak
160
+++ b/configs/targets/microblaze-softmmu.mak
161
@@ -XXX,XX +XXX,XX @@ TARGET_ARCH=microblaze
162
TARGET_BIG_ENDIAN=y
163
TARGET_SUPPORTS_MTTCG=y
164
TARGET_NEED_FDT=y
165
+TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml
166
diff --git a/configs/targets/microblazeel-linux-user.mak b/configs/targets/microblazeel-linux-user.mak
167
index XXXXXXX..XXXXXXX 100644
168
--- a/configs/targets/microblazeel-linux-user.mak
169
+++ b/configs/targets/microblazeel-linux-user.mak
170
@@ -XXX,XX +XXX,XX @@ TARGET_ARCH=microblaze
171
TARGET_SYSTBL_ABI=common
172
TARGET_SYSTBL=syscall.tbl
173
TARGET_HAS_BFLT=y
174
+TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml
175
diff --git a/configs/targets/microblazeel-softmmu.mak b/configs/targets/microblazeel-softmmu.mak
176
index XXXXXXX..XXXXXXX 100644
177
--- a/configs/targets/microblazeel-softmmu.mak
178
+++ b/configs/targets/microblazeel-softmmu.mak
179
@@ -XXX,XX +XXX,XX @@
180
TARGET_ARCH=microblaze
181
TARGET_SUPPORTS_MTTCG=y
182
TARGET_NEED_FDT=y
183
+TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml
184
diff --git a/gdb-xml/microblaze-core.xml b/gdb-xml/microblaze-core.xml
185
new file mode 100644
186
index XXXXXXX..XXXXXXX
187
--- /dev/null
188
+++ b/gdb-xml/microblaze-core.xml
189
@@ -XXX,XX +XXX,XX @@
190
+<?xml version="1.0"?>
191
+<!-- Copyright (C) 2008 Free Software Foundation, Inc.
192
+
193
+ Copying and distribution of this file, with or without modification,
194
+ are permitted in any medium without royalty provided the copyright
195
+ notice and this notice are preserved. -->
196
+
197
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
198
+<feature name="org.gnu.gdb.microblaze.core">
199
+ <reg name="r0" bitsize="32" regnum="0"/>
200
+ <reg name="r1" bitsize="32" type="data_ptr"/>
201
+ <reg name="r2" bitsize="32"/>
202
+ <reg name="r3" bitsize="32"/>
203
+ <reg name="r4" bitsize="32"/>
204
+ <reg name="r5" bitsize="32"/>
205
+ <reg name="r6" bitsize="32"/>
206
+ <reg name="r7" bitsize="32"/>
207
+ <reg name="r8" bitsize="32"/>
208
+ <reg name="r9" bitsize="32"/>
209
+ <reg name="r10" bitsize="32"/>
210
+ <reg name="r11" bitsize="32"/>
211
+ <reg name="r12" bitsize="32"/>
212
+ <reg name="r13" bitsize="32"/>
213
+ <reg name="r14" bitsize="32"/>
214
+ <reg name="r15" bitsize="32"/>
215
+ <reg name="r16" bitsize="32"/>
216
+ <reg name="r17" bitsize="32"/>
217
+ <reg name="r18" bitsize="32"/>
218
+ <reg name="r19" bitsize="32"/>
219
+ <reg name="r20" bitsize="32"/>
220
+ <reg name="r21" bitsize="32"/>
221
+ <reg name="r22" bitsize="32"/>
222
+ <reg name="r23" bitsize="32"/>
223
+ <reg name="r24" bitsize="32"/>
224
+ <reg name="r25" bitsize="32"/>
225
+ <reg name="r26" bitsize="32"/>
226
+ <reg name="r27" bitsize="32"/>
227
+ <reg name="r28" bitsize="32"/>
228
+ <reg name="r29" bitsize="32"/>
229
+ <reg name="r30" bitsize="32"/>
230
+ <reg name="r31" bitsize="32"/>
231
+ <reg name="rpc" bitsize="32" type="code_ptr"/>
232
+ <reg name="rmsr" bitsize="32"/>
233
+ <reg name="rear" bitsize="32"/>
234
+ <reg name="resr" bitsize="32"/>
235
+ <reg name="rfsr" bitsize="32"/>
236
+ <reg name="rbtr" bitsize="32"/>
237
+ <reg name="rpvr0" bitsize="32"/>
238
+ <reg name="rpvr1" bitsize="32"/>
239
+ <reg name="rpvr2" bitsize="32"/>
240
+ <reg name="rpvr3" bitsize="32"/>
241
+ <reg name="rpvr4" bitsize="32"/>
242
+ <reg name="rpvr5" bitsize="32"/>
243
+ <reg name="rpvr6" bitsize="32"/>
244
+ <reg name="rpvr7" bitsize="32"/>
245
+ <reg name="rpvr8" bitsize="32"/>
246
+ <reg name="rpvr9" bitsize="32"/>
247
+ <reg name="rpvr10" bitsize="32"/>
248
+ <reg name="rpvr11" bitsize="32"/>
249
+ <reg name="redr" bitsize="32"/>
250
+ <reg name="rpid" bitsize="32"/>
251
+ <reg name="rzpr" bitsize="32"/>
252
+ <reg name="rtlbx" bitsize="32"/>
253
+ <reg name="rtlbsx" bitsize="32"/>
254
+ <reg name="rtlblo" bitsize="32"/>
255
+ <reg name="rtlbhi" bitsize="32"/>
256
+</feature>
257
diff --git a/gdb-xml/microblaze-stack-protect.xml b/gdb-xml/microblaze-stack-protect.xml
258
new file mode 100644
259
index XXXXXXX..XXXXXXX
260
--- /dev/null
261
+++ b/gdb-xml/microblaze-stack-protect.xml
262
@@ -XXX,XX +XXX,XX @@
263
+<?xml version="1.0"?>
264
+<!-- Copyright (C) 2008 Free Software Foundation, Inc.
265
+
266
+ Copying and distribution of this file, with or without modification,
267
+ are permitted in any medium without royalty provided the copyright
268
+ notice and this notice are preserved. -->
269
+
270
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
271
+<feature name="org.gnu.gdb.microblaze.stack-protect">
272
+ <reg name="rslr" bitsize="32"/>
273
+ <reg name="rshr" bitsize="32"/>
274
+</feature>
275
--
276
2.34.1
diff view generated by jsdifflib
New patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
1
2
3
ctr_el0 access is privileged on this platform and fails as an illegal
4
instruction.
5
6
Windows does not offer a way to flush data cache from userspace, and
7
only FlushInstructionCache is available in Windows API.
8
9
The generic implementation of flush_idcache_range uses,
10
__builtin___clear_cache, which already use the FlushInstructionCache
11
function. So we rely on that.
12
13
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-Id: <20230221153006.20300-2-pierrick.bouvier@linaro.org>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
---
18
util/cacheflush.c | 14 +++++++++++---
19
1 file changed, 11 insertions(+), 3 deletions(-)
20
21
diff --git a/util/cacheflush.c b/util/cacheflush.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/util/cacheflush.c
24
+++ b/util/cacheflush.c
25
@@ -XXX,XX +XXX,XX @@ static void sys_cache_info(int *isize, int *dsize)
26
static bool have_coherent_icache;
27
#endif
28
29
-#if defined(__aarch64__) && !defined(CONFIG_DARWIN)
30
-/* Apple does not expose CTR_EL0, so we must use system interfaces. */
31
+#if defined(__aarch64__) && !defined(CONFIG_DARWIN) && !defined(CONFIG_WIN32)
32
+/*
33
+ * Apple does not expose CTR_EL0, so we must use system interfaces.
34
+ * Windows neither, but we use a generic implementation of flush_idcache_range
35
+ * in this case.
36
+ */
37
static uint64_t save_ctr_el0;
38
static void arch_cache_info(int *isize, int *dsize)
39
{
40
@@ -XXX,XX +XXX,XX @@ static void __attribute__((constructor)) init_cache_info(void)
41
42
/* Caches are coherent and do not require flushing; symbol inline. */
43
44
-#elif defined(__aarch64__)
45
+#elif defined(__aarch64__) && !defined(CONFIG_WIN32)
46
+/*
47
+ * For Windows, we use generic implementation of flush_idcache_range, that
48
+ * performs a call to FlushInstructionCache, through __builtin___clear_cache.
49
+ */
50
51
#ifdef CONFIG_DARWIN
52
/* Apple does not expose CTR_EL0, so we must use system interfaces. */
53
--
54
2.34.1
diff view generated by jsdifflib
1
This allows targets to declare that the helper requires a
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
float_status pointer and instead of a generic void pointer.
2
3
Windows implementation of setjmp/longjmp is done in
4
C:/WINDOWS/system32/ucrtbase.dll. Alas, on arm64, it seems to *always*
5
perform stack unwinding, which crashes from generated code.
6
7
By using alternative implementation built in mingw, we avoid doing stack
8
unwinding and this fixes crash when calling longjmp.
3
9
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
12
Acked-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-Id: <20230221153006.20300-3-pierrick.bouvier@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
15
---
7
include/exec/helper-head.h.inc | 3 +++
16
include/sysemu/os-win32.h | 28 ++++++++++++++++++++++++----
8
1 file changed, 3 insertions(+)
17
meson.build | 21 +++++++++++++++++++++
18
2 files changed, 45 insertions(+), 4 deletions(-)
9
19
10
diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
20
diff --git a/include/sysemu/os-win32.h b/include/sysemu/os-win32.h
11
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
12
--- a/include/exec/helper-head.h.inc
22
--- a/include/sysemu/os-win32.h
13
+++ b/include/exec/helper-head.h.inc
23
+++ b/include/sysemu/os-win32.h
14
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ typedef struct sockaddr_un {
15
#define dh_alias_ptr ptr
25
extern "C" {
16
#define dh_alias_cptr ptr
26
#endif
17
#define dh_alias_env ptr
27
18
+#define dh_alias_fpst ptr
28
-#if defined(_WIN64)
19
#define dh_alias_void void
29
-/* On w64, setjmp is implemented by _setjmp which needs a second parameter.
20
#define dh_alias_noreturn noreturn
30
+#if defined(__aarch64__)
21
#define dh_alias(t) glue(dh_alias_, t)
31
+/*
22
@@ -XXX,XX +XXX,XX @@
32
+ * On windows-arm64, setjmp is available in only one variant, and longjmp always
23
#define dh_ctype_ptr void *
33
+ * does stack unwinding. This crash with generated code.
24
#define dh_ctype_cptr const void *
34
+ * Thus, we use another implementation of setjmp (not windows one), coming from
25
#define dh_ctype_env CPUArchState *
35
+ * mingw, which never performs stack unwinding.
26
+#define dh_ctype_fpst float_status *
36
+ */
27
#define dh_ctype_void void
37
+#undef setjmp
28
#define dh_ctype_noreturn G_NORETURN void
38
+#undef longjmp
29
#define dh_ctype(t) dh_ctype_##t
39
+/*
30
@@ -XXX,XX +XXX,XX @@
40
+ * These functions are not declared in setjmp.h because __aarch64__ defines
31
#define dh_typecode_f64 dh_typecode_i64
41
+ * setjmp to _setjmpex instead. However, they are still defined in libmingwex.a,
32
#define dh_typecode_cptr dh_typecode_ptr
42
+ * which gets linked automatically.
33
#define dh_typecode_env dh_typecode_ptr
43
+ */
34
+#define dh_typecode_fpst dh_typecode_ptr
44
+extern int __mingw_setjmp(jmp_buf);
35
#define dh_typecode(t) dh_typecode_##t
45
+extern void __attribute__((noreturn)) __mingw_longjmp(jmp_buf, int);
36
46
+#define setjmp(env) __mingw_setjmp(env)
37
#define dh_callflag_i32 0
47
+#define longjmp(env, val) __mingw_longjmp(env, val)
48
+#elif defined(_WIN64)
49
+/*
50
+ * On windows-x64, setjmp is implemented by _setjmp which needs a second parameter.
51
* If this parameter is NULL, longjump does no stack unwinding.
52
* That is what we need for QEMU. Passing the value of register rsp (default)
53
- * lets longjmp try a stack unwinding which will crash with generated code. */
54
+ * lets longjmp try a stack unwinding which will crash with generated code.
55
+ */
56
# undef setjmp
57
# define setjmp(env) _setjmp(env, NULL)
58
-#endif
59
+#endif /* __aarch64__ */
60
/* QEMU uses sigsetjmp()/siglongjmp() as the portable way to specify
61
* "longjmp and don't touch the signal masks". Since we know that the
62
* savemask parameter will always be zero we can safely define these
63
diff --git a/meson.build b/meson.build
64
index XXXXXXX..XXXXXXX 100644
65
--- a/meson.build
66
+++ b/meson.build
67
@@ -XXX,XX +XXX,XX @@ if targetos == 'windows'
68
}''', name: '_lock_file and _unlock_file'))
69
endif
70
71
+if targetos == 'windows'
72
+ mingw_has_setjmp_longjmp = cc.links('''
73
+ #include <setjmp.h>
74
+ int main(void) {
75
+ /*
76
+ * These functions are not available in setjmp header, but may be
77
+ * available at link time, from libmingwex.a.
78
+ */
79
+ extern int __mingw_setjmp(jmp_buf);
80
+ extern void __attribute__((noreturn)) __mingw_longjmp(jmp_buf, int);
81
+ jmp_buf env;
82
+ __mingw_setjmp(env);
83
+ __mingw_longjmp(env, 0);
84
+ }
85
+ ''', name: 'mingw setjmp and longjmp')
86
+
87
+ if cpu == 'aarch64' and not mingw_has_setjmp_longjmp
88
+ error('mingw must provide setjmp/longjmp for windows-arm64')
89
+ endif
90
+endif
91
+
92
########################
93
# Target configuration #
94
########################
38
--
95
--
39
2.43.0
96
2.34.1
40
97
41
98
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