[PULL 0/4] tcg patch queue
[PULL v2 00/20] tcg patch queue
1
Pretty small still, but there are two patches that ought
1
v2: Fix incorretly resolved rebase conflict in patch 16.
2
to get backported to stable, so no point in delaying.
2
3
3
4
r~
4
r~
5
5
6
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
7
6
8
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
7
The following changes since commit 61fd710b8da8aedcea9b4f197283dc38638e4b60:
8
9
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2022-09-02 13:24:28 -0400)
9
10
10
are available in the Git repository at:
11
are available in the Git repository at:
11
12
12
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212
13
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220904
13
14
14
for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:
15
for you to fetch changes up to cc64de1fdeb81bc1ab8bb6c7c24bfd4fc9b28ef2:
15
16
16
target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)
17
target/riscv: Make translator stop before the end of a page (2022-09-03 09:27:05 +0100)
17
18
18
----------------------------------------------------------------
19
----------------------------------------------------------------
19
tcg: Reset free_temps before tcg_optimize
20
Respect PROT_EXEC in user-only mode.
20
tcg/riscv: Fix StoreStore barrier generation
21
Fix s390x, i386 and riscv for translations crossing a page.
21
include/exec: Introduce fpst alias in helper-head.h.inc
22
target/sparc: Use memcpy() and remove memcpy32()
23
22
24
----------------------------------------------------------------
23
----------------------------------------------------------------
25
Philippe Mathieu-Daudé (1):
24
Ilya Leoshkevich (4):
26
target/sparc: Use memcpy() and remove memcpy32()
25
linux-user: Clear translations on mprotect()
26
accel/tcg: Introduce is_same_page()
27
target/s390x: Make translator stop before the end of a page
28
target/i386: Make translator stop before the end of a page
27
29
28
Richard Henderson (2):
30
Richard Henderson (16):
29
tcg: Reset free_temps before tcg_optimize
31
linux-user/arm: Mark the commpage executable
30
include/exec: Introduce fpst alias in helper-head.h.inc
32
linux-user/hppa: Allocate page zero as a commpage
33
linux-user/x86_64: Allocate vsyscall page as a commpage
34
linux-user: Honor PT_GNU_STACK
35
tests/tcg/i386: Move smc_code2 to an executable section
36
accel/tcg: Properly implement get_page_addr_code for user-only
37
accel/tcg: Unlock mmap_lock after longjmp
38
accel/tcg: Make tb_htable_lookup static
39
accel/tcg: Move qemu_ram_addr_from_host_nofail to physmem.c
40
accel/tcg: Use probe_access_internal for softmmu get_page_addr_code_hostp
41
accel/tcg: Document the faulting lookup in tb_lookup_cmp
42
accel/tcg: Remove translator_ldsw
43
accel/tcg: Add pc and host_pc params to gen_intermediate_code
44
accel/tcg: Add fast path for translator_ld*
45
target/riscv: Add MAX_INSN_LEN and insn_len
46
target/riscv: Make translator stop before the end of a page
31
47
32
Roman Artemev (1):
48
include/elf.h | 1 +
33
tcg/riscv: Fix StoreStore barrier generation
49
include/exec/cpu-common.h | 1 +
34
50
include/exec/exec-all.h | 89 ++++++++----------------
35
include/tcg/tcg-temp-internal.h | 6 ++++++
51
include/exec/translator.h | 96 ++++++++++++++++---------
36
accel/tcg/plugin-gen.c | 2 +-
52
linux-user/arm/target_cpu.h | 4 +-
37
target/sparc/win_helper.c | 26 ++++++++------------------
53
linux-user/qemu.h | 1 +
38
tcg/tcg.c | 5 ++++-
54
accel/tcg/cpu-exec.c | 143 ++++++++++++++++++++------------------
39
include/exec/helper-head.h.inc | 3 +++
55
accel/tcg/cputlb.c | 93 +++++++------------------
40
tcg/riscv/tcg-target.c.inc | 2 +-
56
accel/tcg/translate-all.c | 29 ++++----
41
6 files changed, 23 insertions(+), 21 deletions(-)
57
accel/tcg/translator.c | 135 ++++++++++++++++++++++++++---------
42
58
accel/tcg/user-exec.c | 17 ++++-
59
linux-user/elfload.c | 82 ++++++++++++++++++++--
60
linux-user/mmap.c | 6 +-
61
softmmu/physmem.c | 12 ++++
62
target/alpha/translate.c | 5 +-
63
target/arm/translate.c | 5 +-
64
target/avr/translate.c | 5 +-
65
target/cris/translate.c | 5 +-
66
target/hexagon/translate.c | 6 +-
67
target/hppa/translate.c | 5 +-
68
target/i386/tcg/translate.c | 71 +++++++++++--------
69
target/loongarch/translate.c | 6 +-
70
target/m68k/translate.c | 5 +-
71
target/microblaze/translate.c | 5 +-
72
target/mips/tcg/translate.c | 5 +-
73
target/nios2/translate.c | 5 +-
74
target/openrisc/translate.c | 6 +-
75
target/ppc/translate.c | 5 +-
76
target/riscv/translate.c | 32 +++++++--
77
target/rx/translate.c | 5 +-
78
target/s390x/tcg/translate.c | 20 ++++--
79
target/sh4/translate.c | 5 +-
80
target/sparc/translate.c | 5 +-
81
target/tricore/translate.c | 6 +-
82
target/xtensa/translate.c | 6 +-
83
tests/tcg/i386/test-i386.c | 2 +-
84
tests/tcg/riscv64/noexec.c | 79 +++++++++++++++++++++
85
tests/tcg/s390x/noexec.c | 106 ++++++++++++++++++++++++++++
86
tests/tcg/x86_64/noexec.c | 75 ++++++++++++++++++++
87
tests/tcg/multiarch/noexec.c.inc | 139 ++++++++++++++++++++++++++++++++++++
88
tests/tcg/riscv64/Makefile.target | 1 +
89
tests/tcg/s390x/Makefile.target | 1 +
90
tests/tcg/x86_64/Makefile.target | 3 +-
91
43 files changed, 966 insertions(+), 367 deletions(-)
92
create mode 100644 tests/tcg/riscv64/noexec.c
93
create mode 100644 tests/tcg/s390x/noexec.c
94
create mode 100644 tests/tcg/x86_64/noexec.c
95
create mode 100644 tests/tcg/multiarch/noexec.c.inc
diff view generated by jsdifflib
[PULL 1/4] tcg: Reset free_temps before tcg_optimize
Deleted patch
1
When allocating new temps during tcg_optmize, do not re-use
2
any EBB temps that were used within the TB. We do not have
3
any idea what span of the TB in which the temp was live.
4
1
5
Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
6
as well as replacing the equivalent in plugin_gen_inject and
7
tcg_func_start.
8
9
Cc: qemu-stable@nongnu.org
10
Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
11
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
12
Reported-by: wannacu <wannacu2049@gmail.com>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
---
17
include/tcg/tcg-temp-internal.h | 6 ++++++
18
accel/tcg/plugin-gen.c | 2 +-
19
tcg/tcg.c | 5 ++++-
20
3 files changed, 11 insertions(+), 2 deletions(-)
21
22
diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/include/tcg/tcg-temp-internal.h
25
+++ b/include/tcg/tcg-temp-internal.h
26
@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
27
TCGv_ptr tcg_temp_ebb_new_ptr(void);
28
TCGv_i128 tcg_temp_ebb_new_i128(void);
29
30
+/* Forget all freed EBB temps, so that new allocations produce new temps. */
31
+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
32
+{
33
+ memset(s->free_temps, 0, sizeof(s->free_temps));
34
+}
35
+
36
#endif /* TCG_TEMP_FREE_H */
37
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/accel/tcg/plugin-gen.c
40
+++ b/accel/tcg/plugin-gen.c
41
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
42
* that might be live within the existing opcode stream.
43
* The simplest solution is to release them all and create new.
44
*/
45
- memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
46
+ tcg_temp_ebb_reset_freed(tcg_ctx);
47
48
QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
49
switch (op->opc) {
50
diff --git a/tcg/tcg.c b/tcg/tcg.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/tcg/tcg.c
53
+++ b/tcg/tcg.c
54
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
55
s->nb_temps = s->nb_globals;
56
57
/* No temps have been previously allocated for size or locality. */
58
- memset(s->free_temps, 0, sizeof(s->free_temps));
59
+ tcg_temp_ebb_reset_freed(s);
60
61
/* No constant temps have been previously allocated. */
62
for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
63
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
64
}
65
#endif
66
67
+ /* Do not reuse any EBB that may be allocated within the TB. */
68
+ tcg_temp_ebb_reset_freed(s);
69
+
70
tcg_optimize(s);
71
72
reachable_code_pass(s);
73
--
74
2.43.0
75
76
diff view generated by jsdifflib
[PULL 2/4] tcg/riscv: Fix StoreStore barrier generation
Deleted patch
1
From: Roman Artemev <roman.artemev@syntacore.com>
2
1
3
On RISC-V to StoreStore barrier corresponds
4
`fence w, w` not `fence r, r`
5
6
Cc: qemu-stable@nongnu.org
7
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
10
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
11
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
14
tcg/riscv/tcg-target.c.inc | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
18
index XXXXXXX..XXXXXXX 100644
19
--- a/tcg/riscv/tcg-target.c.inc
20
+++ b/tcg/riscv/tcg-target.c.inc
21
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
22
insn |= 0x02100000;
23
}
24
if (a0 & TCG_MO_ST_ST) {
25
- insn |= 0x02200000;
26
+ insn |= 0x01100000;
27
}
28
tcg_out32(s, insn);
29
}
30
--
31
2.43.0
diff view generated by jsdifflib
[PULL 3/4] include/exec: Introduce fpst alias in helper-head.h.inc
Deleted patch
1
This allows targets to declare that the helper requires a
2
float_status pointer and instead of a generic void pointer.
3
1
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
include/exec/helper-head.h.inc | 3 +++
8
1 file changed, 3 insertions(+)
9
10
diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/include/exec/helper-head.h.inc
13
+++ b/include/exec/helper-head.h.inc
14
@@ -XXX,XX +XXX,XX @@
15
#define dh_alias_ptr ptr
16
#define dh_alias_cptr ptr
17
#define dh_alias_env ptr
18
+#define dh_alias_fpst ptr
19
#define dh_alias_void void
20
#define dh_alias_noreturn noreturn
21
#define dh_alias(t) glue(dh_alias_, t)
22
@@ -XXX,XX +XXX,XX @@
23
#define dh_ctype_ptr void *
24
#define dh_ctype_cptr const void *
25
#define dh_ctype_env CPUArchState *
26
+#define dh_ctype_fpst float_status *
27
#define dh_ctype_void void
28
#define dh_ctype_noreturn G_NORETURN void
29
#define dh_ctype(t) dh_ctype_##t
30
@@ -XXX,XX +XXX,XX @@
31
#define dh_typecode_f64 dh_typecode_i64
32
#define dh_typecode_cptr dh_typecode_ptr
33
#define dh_typecode_env dh_typecode_ptr
34
+#define dh_typecode_fpst dh_typecode_ptr
35
#define dh_typecode(t) dh_typecode_##t
36
37
#define dh_callflag_i32 0
38
--
39
2.43.0
40
41
diff view generated by jsdifflib
[PULL 4/4] target/sparc: Use memcpy() and remove memcpy32()
[PULL v2 16/20] accel/tcg: Add fast path for translator_ld*
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
Cache the translation from guest to host address, so we may
2
use direct loads when we hit on the primary translation page.
2
3
3
Rather than manually copying each register, use
4
Look up the second translation page only once, during translation.
4
the libc memcpy(), which is well optimized nowadays.
5
This obviates another lookup of the second page within tb_gen_code
6
after translation.
5
7
6
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
8
Fixes a bug in that plugin_insn_append should be passed the bytes
7
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
9
in the original memory order, not bswapped by pieces.
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
10
Message-ID: <20241205205418.67613-1-philmd@linaro.org>
12
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
14
---
13
target/sparc/win_helper.c | 26 ++++++++------------------
15
include/exec/translator.h | 63 +++++++++++--------
14
1 file changed, 8 insertions(+), 18 deletions(-)
16
accel/tcg/translate-all.c | 23 +++----
17
accel/tcg/translator.c | 126 +++++++++++++++++++++++++++++---------
18
3 files changed, 141 insertions(+), 71 deletions(-)
15
19
16
diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
20
diff --git a/include/exec/translator.h b/include/exec/translator.h
17
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
18
--- a/target/sparc/win_helper.c
22
--- a/include/exec/translator.h
19
+++ b/target/sparc/win_helper.c
23
+++ b/include/exec/translator.h
20
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ typedef enum DisasJumpType {
21
#include "exec/helper-proto.h"
25
* Architecture-agnostic disassembly context.
22
#include "trace.h"
26
*/
23
27
typedef struct DisasContextBase {
24
-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
28
- const TranslationBlock *tb;
29
+ TranslationBlock *tb;
30
target_ulong pc_first;
31
target_ulong pc_next;
32
DisasJumpType is_jmp;
33
int num_insns;
34
int max_insns;
35
bool singlestep_enabled;
36
-#ifdef CONFIG_USER_ONLY
37
- /*
38
- * Guest address of the last byte of the last protected page.
39
- *
40
- * Pages containing the translated instructions are made non-writable in
41
- * order to achieve consistency in case another thread is modifying the
42
- * code while translate_insn() fetches the instruction bytes piecemeal.
43
- * Such writer threads are blocked on mmap_lock() in page_unprotect().
44
- */
45
- target_ulong page_protect_end;
46
-#endif
47
+ void *host_addr[2];
48
} DisasContextBase;
49
50
/**
51
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
52
* the relevant information at translation time.
53
*/
54
55
-#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
56
- type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
57
- abi_ptr pc, bool do_swap); \
58
- static inline type fullname(CPUArchState *env, \
59
- DisasContextBase *dcbase, abi_ptr pc) \
60
- { \
61
- return fullname ## _swap(env, dcbase, pc, false); \
62
+uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
63
+uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
64
+uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
65
+uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
66
+
67
+static inline uint16_t
68
+translator_lduw_swap(CPUArchState *env, DisasContextBase *db,
69
+ abi_ptr pc, bool do_swap)
70
+{
71
+ uint16_t ret = translator_lduw(env, db, pc);
72
+ if (do_swap) {
73
+ ret = bswap16(ret);
74
}
75
+ return ret;
76
+}
77
78
-#define FOR_EACH_TRANSLATOR_LD(F) \
79
- F(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) \
80
- F(translator_lduw, uint16_t, cpu_lduw_code, bswap16) \
81
- F(translator_ldl, uint32_t, cpu_ldl_code, bswap32) \
82
- F(translator_ldq, uint64_t, cpu_ldq_code, bswap64)
83
+static inline uint32_t
84
+translator_ldl_swap(CPUArchState *env, DisasContextBase *db,
85
+ abi_ptr pc, bool do_swap)
86
+{
87
+ uint32_t ret = translator_ldl(env, db, pc);
88
+ if (do_swap) {
89
+ ret = bswap32(ret);
90
+ }
91
+ return ret;
92
+}
93
94
-FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
95
-
96
-#undef GEN_TRANSLATOR_LD
97
+static inline uint64_t
98
+translator_ldq_swap(CPUArchState *env, DisasContextBase *db,
99
+ abi_ptr pc, bool do_swap)
100
+{
101
+ uint64_t ret = translator_ldq(env, db, pc);
102
+ if (do_swap) {
103
+ ret = bswap64(ret);
104
+ }
105
+ return ret;
106
+}
107
108
/*
109
* Return whether addr is on the same page as where disassembly started.
110
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/accel/tcg/translate-all.c
113
+++ b/accel/tcg/translate-all.c
114
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
115
{
116
CPUArchState *env = cpu->env_ptr;
117
TranslationBlock *tb, *existing_tb;
118
- tb_page_addr_t phys_pc, phys_page2;
119
- target_ulong virt_page2;
120
+ tb_page_addr_t phys_pc;
121
tcg_insn_unit *gen_code_buf;
122
int gen_code_size, search_size, max_insns;
123
#ifdef CONFIG_PROFILER
124
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
125
tb->flags = flags;
126
tb->cflags = cflags;
127
tb->trace_vcpu_dstate = *cpu->trace_dstate;
128
+ tb->page_addr[0] = phys_pc;
129
+ tb->page_addr[1] = -1;
130
tcg_ctx->tb_cflags = cflags;
131
tb_overflow:
132
133
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
134
}
135
136
/*
137
- * If the TB is not associated with a physical RAM page then
138
- * it must be a temporary one-insn TB, and we have nothing to do
139
- * except fill in the page_addr[] fields. Return early before
140
- * attempting to link to other TBs or add to the lookup table.
141
+ * If the TB is not associated with a physical RAM page then it must be
142
+ * a temporary one-insn TB, and we have nothing left to do. Return early
143
+ * before attempting to link to other TBs or add to the lookup table.
144
*/
145
- if (phys_pc == -1) {
146
- tb->page_addr[0] = tb->page_addr[1] = -1;
147
+ if (tb->page_addr[0] == -1) {
148
return tb;
149
}
150
151
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
152
*/
153
tcg_tb_insert(tb);
154
155
- /* check next page if needed */
156
- virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
157
- phys_page2 = -1;
158
- if ((pc & TARGET_PAGE_MASK) != virt_page2) {
159
- phys_page2 = get_page_addr_code(env, virt_page2);
160
- }
161
/*
162
* No explicit memory barrier is required -- tb_link_page() makes the
163
* TB visible in a consistent state.
164
*/
165
- existing_tb = tb_link_page(tb, phys_pc, phys_page2);
166
+ existing_tb = tb_link_page(tb, tb->page_addr[0], tb->page_addr[1]);
167
/* if the TB already exists, discard what we just translated */
168
if (unlikely(existing_tb != tb)) {
169
uintptr_t orig_aligned = (uintptr_t)gen_code_buf;
170
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
171
index XXXXXXX..XXXXXXX 100644
172
--- a/accel/tcg/translator.c
173
+++ b/accel/tcg/translator.c
174
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest)
175
return ((db->pc_first ^ dest) & TARGET_PAGE_MASK) == 0;
176
}
177
178
-static inline void translator_page_protect(DisasContextBase *dcbase,
179
- target_ulong pc)
25
-{
180
-{
26
- dst[0] = src[0];
181
-#ifdef CONFIG_USER_ONLY
27
- dst[1] = src[1];
182
- dcbase->page_protect_end = pc | ~TARGET_PAGE_MASK;
28
- dst[2] = src[2];
183
- page_protect(pc);
29
- dst[3] = src[3];
184
-#endif
30
- dst[4] = src[4];
31
- dst[5] = src[5];
32
- dst[6] = src[6];
33
- dst[7] = src[7];
34
-}
185
-}
35
-
186
-
36
void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
187
void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
188
target_ulong pc, void *host_pc,
189
const TranslatorOps *ops, DisasContextBase *db)
190
@@ -XXX,XX +XXX,XX @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
191
db->num_insns = 0;
192
db->max_insns = max_insns;
193
db->singlestep_enabled = cflags & CF_SINGLE_STEP;
194
- translator_page_protect(db, db->pc_next);
195
+ db->host_addr[0] = host_pc;
196
+ db->host_addr[1] = NULL;
197
+
198
+#ifdef CONFIG_USER_ONLY
199
+ page_protect(pc);
200
+#endif
201
202
ops->init_disas_context(db, cpu);
203
tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
204
@@ -XXX,XX +XXX,XX @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
205
#endif
206
}
207
208
-static inline void translator_maybe_page_protect(DisasContextBase *dcbase,
209
- target_ulong pc, size_t len)
210
+static void *translator_access(CPUArchState *env, DisasContextBase *db,
211
+ target_ulong pc, size_t len)
37
{
212
{
38
/* put the modified wrap registers at their proper location */
213
-#ifdef CONFIG_USER_ONLY
39
if (env->cwp == env->nwindows - 1) {
214
- target_ulong end = pc + len - 1;
40
- memcpy32(env->regbase, env->regbase + env->nwindows * 16);
215
+ void *host;
41
+ memcpy(env->regbase, env->regbase + env->nwindows * 16,
216
+ target_ulong base, end;
42
+ sizeof(env->gregs));
217
+ TranslationBlock *tb;
43
}
218
44
env->cwp = new_cwp;
219
- if (end > dcbase->page_protect_end) {
45
220
- translator_page_protect(dcbase, end);
46
/* put the wrap registers at their temporary location */
221
+ tb = db->tb;
47
if (new_cwp == env->nwindows - 1) {
222
+
48
- memcpy32(env->regbase + env->nwindows * 16, env->regbase);
223
+ /* Use slow path if first page is MMIO. */
49
+ memcpy(env->regbase + env->nwindows * 16, env->regbase,
224
+ if (unlikely(tb->page_addr[0] == -1)) {
50
+ sizeof(env->gregs));
225
+ return NULL;
51
}
226
}
52
env->regwptr = env->regbase + (new_cwp * 16);
227
+
228
+ end = pc + len - 1;
229
+ if (likely(is_same_page(db, end))) {
230
+ host = db->host_addr[0];
231
+ base = db->pc_first;
232
+ } else {
233
+ host = db->host_addr[1];
234
+ base = TARGET_PAGE_ALIGN(db->pc_first);
235
+ if (host == NULL) {
236
+ tb->page_addr[1] =
237
+ get_page_addr_code_hostp(env, base, &db->host_addr[1]);
238
+#ifdef CONFIG_USER_ONLY
239
+ page_protect(end);
240
#endif
241
+ /* We cannot handle MMIO as second page. */
242
+ assert(tb->page_addr[1] != -1);
243
+ host = db->host_addr[1];
244
+ }
245
+
246
+ /* Use slow path when crossing pages. */
247
+ if (is_same_page(db, pc)) {
248
+ return NULL;
249
+ }
250
+ }
251
+
252
+ tcg_debug_assert(pc >= base);
253
+ return host + (pc - base);
53
}
254
}
54
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
255
55
dst = get_gl_gregset(env, env->gl);
256
-#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
56
257
- type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
57
if (src != dst) {
258
- abi_ptr pc, bool do_swap) \
58
- memcpy32(dst, env->gregs);
259
- { \
59
- memcpy32(env->gregs, src);
260
- translator_maybe_page_protect(dcbase, pc, sizeof(type)); \
60
+ memcpy(dst, env->gregs, sizeof(env->gregs));
261
- type ret = load_fn(env, pc); \
61
+ memcpy(env->gregs, src, sizeof(env->gregs));
262
- if (do_swap) { \
62
}
263
- ret = swap_fn(ret); \
63
}
264
- } \
64
265
- plugin_insn_append(pc, &ret, sizeof(ret)); \
65
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
266
- return ret; \
66
/* Switch global register bank */
267
+uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
67
src = get_gregset(env, new_pstate_regs);
268
+{
68
dst = get_gregset(env, pstate_regs);
269
+ uint8_t ret;
69
- memcpy32(dst, env->gregs);
270
+ void *p = translator_access(env, db, pc, sizeof(ret));
70
- memcpy32(env->gregs, src);
271
+
71
+ memcpy(dst, env->gregs, sizeof(env->gregs));
272
+ if (p) {
72
+ memcpy(env->gregs, src, sizeof(env->gregs));
273
+ plugin_insn_append(pc, p, sizeof(ret));
73
} else {
274
+ return ldub_p(p);
74
trace_win_helper_no_switch_pstate(new_pstate_regs);
275
}
75
}
276
+ ret = cpu_ldub_code(env, pc);
277
+ plugin_insn_append(pc, &ret, sizeof(ret));
278
+ return ret;
279
+}
280
281
-FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
282
+uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
283
+{
284
+ uint16_t ret, plug;
285
+ void *p = translator_access(env, db, pc, sizeof(ret));
286
287
-#undef GEN_TRANSLATOR_LD
288
+ if (p) {
289
+ plugin_insn_append(pc, p, sizeof(ret));
290
+ return lduw_p(p);
291
+ }
292
+ ret = cpu_lduw_code(env, pc);
293
+ plug = tswap16(ret);
294
+ plugin_insn_append(pc, &plug, sizeof(ret));
295
+ return ret;
296
+}
297
+
298
+uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
299
+{
300
+ uint32_t ret, plug;
301
+ void *p = translator_access(env, db, pc, sizeof(ret));
302
+
303
+ if (p) {
304
+ plugin_insn_append(pc, p, sizeof(ret));
305
+ return ldl_p(p);
306
+ }
307
+ ret = cpu_ldl_code(env, pc);
308
+ plug = tswap32(ret);
309
+ plugin_insn_append(pc, &plug, sizeof(ret));
310
+ return ret;
311
+}
312
+
313
+uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
314
+{
315
+ uint64_t ret, plug;
316
+ void *p = translator_access(env, db, pc, sizeof(ret));
317
+
318
+ if (p) {
319
+ plugin_insn_append(pc, p, sizeof(ret));
320
+ return ldq_p(p);
321
+ }
322
+ ret = cpu_ldq_code(env, pc);
323
+ plug = tswap64(ret);
324
+ plugin_insn_append(pc, &plug, sizeof(ret));
325
+ return ret;
326
+}
76
--
327
--
77
2.43.0
328
2.34.1
78
79
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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