[PULL 0/4] tcg patch queue
[PATCH v4 00/43] tcg patch queue
1
Pretty small still, but there are two patches that ought
1
Version 4: Drop the cpu_loop noreturn patch.
2
to get backported to stable, so no point in delaying.
2
3
3
4
r~
4
r~
5
5
6
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
7
6
8
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
7
The following changes since commit 4c9af1ea1457782cf0adb293179335ef6de942aa:
8
9
gitlab-ci: Make more custom runner jobs manual, and don't allow failure (2021-09-14 17:03:03 +0100)
9
10
10
are available in the Git repository at:
11
are available in the Git repository at:
11
12
12
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212
13
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210914-4
13
14
14
for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:
15
for you to fetch changes up to e028eada62dbfcba134ac5afdefc3aa343ae202f:
15
16
16
target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)
17
tcg/arm: More use of the TCGReg enum (2021-09-14 12:00:21 -0700)
17
18
18
----------------------------------------------------------------
19
----------------------------------------------------------------
19
tcg: Reset free_temps before tcg_optimize
20
Fix translation race condition for user-only.
20
tcg/riscv: Fix StoreStore barrier generation
21
Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ.
21
include/exec: Introduce fpst alias in helper-head.h.inc
22
Fix tcg/arm tcg_out_vec_op signature.
22
target/sparc: Use memcpy() and remove memcpy32()
23
Fix tcg/ppc (32bit) build with clang.
24
Remove dupluate TCG_KICK_PERIOD definition.
25
Remove unused tcg_global_reg_new.
26
Restrict cpu_exec_interrupt and its callees to sysemu.
27
Cleanups for tcg/arm.
23
28
24
----------------------------------------------------------------
29
----------------------------------------------------------------
25
Philippe Mathieu-Daudé (1):
30
Bin Meng (1):
26
target/sparc: Use memcpy() and remove memcpy32()
31
tcg: Remove tcg_global_reg_new defines
27
32
28
Richard Henderson (2):
33
Ilya Leoshkevich (3):
29
tcg: Reset free_temps before tcg_optimize
34
accel/tcg: Add DisasContextBase argument to translator_ld*
30
include/exec: Introduce fpst alias in helper-head.h.inc
35
accel/tcg: Clear PAGE_WRITE before translation
36
accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts
31
37
32
Roman Artemev (1):
38
Jose R. Ziviani (1):
33
tcg/riscv: Fix StoreStore barrier generation
39
tcg/arm: Fix tcg_out_vec_op function signature
34
40
35
include/tcg/tcg-temp-internal.h | 6 ++++++
41
Luc Michel (1):
36
accel/tcg/plugin-gen.c | 2 +-
42
accel/tcg: remove redundant TCG_KICK_PERIOD define
37
target/sparc/win_helper.c | 26 ++++++++------------------
38
tcg/tcg.c | 5 ++++-
39
include/exec/helper-head.h.inc | 3 +++
40
tcg/riscv/tcg-target.c.inc | 2 +-
41
6 files changed, 23 insertions(+), 21 deletions(-)
42
43
44
Philippe Mathieu-Daudé (24):
45
target/avr: Remove pointless use of CONFIG_USER_ONLY definition
46
target/i386: Restrict sysemu-only fpu_helper helpers
47
target/i386: Simplify TARGET_X86_64 #ifdef'ry
48
target/xtensa: Restrict do_transaction_failed() to sysemu
49
accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt
50
target/alpha: Restrict cpu_exec_interrupt() handler to sysemu
51
target/arm: Restrict cpu_exec_interrupt() handler to sysemu
52
target/cris: Restrict cpu_exec_interrupt() handler to sysemu
53
target/hppa: Restrict cpu_exec_interrupt() handler to sysemu
54
target/i386: Restrict cpu_exec_interrupt() handler to sysemu
55
target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder
56
target/m68k: Restrict cpu_exec_interrupt() handler to sysemu
57
target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu
58
target/mips: Restrict cpu_exec_interrupt() handler to sysemu
59
target/nios2: Restrict cpu_exec_interrupt() handler to sysemu
60
target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu
61
target/ppc: Restrict cpu_exec_interrupt() handler to sysemu
62
target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
63
target/sh4: Restrict cpu_exec_interrupt() handler to sysemu
64
target/sparc: Restrict cpu_exec_interrupt() handler to sysemu
65
target/rx: Restrict cpu_exec_interrupt() handler to sysemu
66
target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu
67
accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu
68
user: Remove cpu_get_pic_interrupt() stubs
69
70
Richard Henderson (13):
71
tcg/i386: Split P_VEXW from P_REXW
72
tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN
73
tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF
74
tcg/arm: Remove fallback definition of __ARM_ARCH
75
tcg/arm: Standardize on tcg_out_<branch>_{reg,imm}
76
tcg/arm: Simplify use_armv5t_instructions
77
tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call
78
tcg/arm: Split out tcg_out_ldstm
79
tcg/arm: Simplify usage of encode_imm
80
tcg/arm: Drop inline markers
81
tcg/arm: Give enum arm_cond_code_e a typedef and use it
82
tcg/arm: More use of the ARMInsn enum
83
tcg/arm: More use of the TCGReg enum
84
85
include/exec/translate-all.h | 1 +
86
include/exec/translator.h | 44 +--
87
include/hw/core/tcg-cpu-ops.h | 26 +-
88
include/tcg/tcg-op.h | 2 -
89
target/alpha/cpu.h | 2 +-
90
target/arm/arm_ldst.h | 12 +-
91
target/arm/cpu.h | 3 +-
92
target/cris/cpu.h | 2 +-
93
target/hppa/cpu.h | 4 +-
94
target/i386/cpu.h | 3 +
95
target/i386/tcg/helper-tcg.h | 2 +
96
target/m68k/cpu.h | 2 +
97
target/microblaze/cpu.h | 2 +
98
target/mips/tcg/tcg-internal.h | 5 +-
99
target/openrisc/cpu.h | 5 +-
100
target/ppc/cpu.h | 4 +-
101
target/riscv/cpu.h | 2 +-
102
target/rx/cpu.h | 2 +
103
target/sh4/cpu.h | 4 +-
104
target/xtensa/cpu.h | 2 +
105
tcg/arm/tcg-target.h | 27 +-
106
accel/tcg/cpu-exec.c | 14 +-
107
accel/tcg/tcg-accel-ops-rr.c | 2 -
108
accel/tcg/translate-all.c | 59 ++--
109
accel/tcg/translator.c | 39 +++
110
accel/tcg/user-exec.c | 48 ++-
111
bsd-user/i386/target_arch_cpu.c | 5 -
112
bsd-user/x86_64/target_arch_cpu.c | 5 -
113
linux-user/main.c | 7 -
114
target/alpha/cpu.c | 2 +-
115
target/alpha/helper.c | 5 +-
116
target/alpha/translate.c | 2 +-
117
target/arm/cpu.c | 7 +-
118
target/arm/cpu_tcg.c | 6 +-
119
target/arm/translate-a64.c | 2 +-
120
target/arm/translate.c | 9 +-
121
target/avr/cpu.c | 3 -
122
target/cris/cpu.c | 4 +-
123
target/cris/helper.c | 17 +-
124
target/hexagon/translate.c | 3 +-
125
target/hppa/cpu.c | 2 +-
126
target/hppa/int_helper.c | 7 +-
127
target/hppa/translate.c | 5 +-
128
target/i386/tcg/seg_helper.c | 74 +----
129
target/i386/tcg/sysemu/seg_helper.c | 62 ++++
130
target/i386/tcg/tcg-cpu.c | 8 +-
131
target/i386/tcg/translate.c | 10 +-
132
target/m68k/cpu.c | 2 +-
133
target/m68k/op_helper.c | 16 +-
134
target/m68k/translate.c | 2 +-
135
target/microblaze/cpu.c | 2 +-
136
target/microblaze/helper.c | 13 +-
137
target/mips/cpu.c | 2 +-
138
target/mips/tcg/exception.c | 18 --
139
target/mips/tcg/sysemu/tlb_helper.c | 18 ++
140
target/mips/tcg/translate.c | 8 +-
141
target/mips/tcg/user/tlb_helper.c | 5 -
142
target/nios2/cpu.c | 5 +-
143
target/openrisc/cpu.c | 2 +-
144
target/openrisc/interrupt.c | 2 -
145
target/openrisc/translate.c | 2 +-
146
target/ppc/cpu_init.c | 2 +-
147
target/ppc/excp_helper.c | 21 +-
148
target/ppc/translate.c | 5 +-
149
target/riscv/cpu.c | 2 +-
150
target/riscv/cpu_helper.c | 5 -
151
target/riscv/translate.c | 5 +-
152
target/rx/cpu.c | 2 +-
153
target/rx/helper.c | 4 +
154
target/s390x/tcg/translate.c | 16 +-
155
target/sh4/cpu.c | 2 +-
156
target/sh4/helper.c | 9 +-
157
target/sh4/translate.c | 4 +-
158
target/sparc/cpu.c | 4 +-
159
target/sparc/translate.c | 2 +-
160
target/xtensa/cpu.c | 2 +-
161
target/xtensa/exc_helper.c | 7 +-
162
target/xtensa/translate.c | 5 +-
163
target/mips/tcg/micromips_translate.c.inc | 2 +-
164
target/mips/tcg/mips16e_translate.c.inc | 4 +-
165
target/mips/tcg/nanomips_translate.c.inc | 4 +-
166
tcg/arm/tcg-target.c.inc | 517 ++++++++++++++++--------------
167
tcg/i386/tcg-target.c.inc | 13 +-
168
tcg/ppc/tcg-target.c.inc | 25 +-
169
target/openrisc/meson.build | 6 +-
170
85 files changed, 700 insertions(+), 628 deletions(-)
171
diff view generated by jsdifflib
[PULL 1/4] tcg: Reset free_temps before tcg_optimize
Deleted patch
1
When allocating new temps during tcg_optmize, do not re-use
2
any EBB temps that were used within the TB. We do not have
3
any idea what span of the TB in which the temp was live.
4
1
5
Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
6
as well as replacing the equivalent in plugin_gen_inject and
7
tcg_func_start.
8
9
Cc: qemu-stable@nongnu.org
10
Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
11
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
12
Reported-by: wannacu <wannacu2049@gmail.com>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
---
17
include/tcg/tcg-temp-internal.h | 6 ++++++
18
accel/tcg/plugin-gen.c | 2 +-
19
tcg/tcg.c | 5 ++++-
20
3 files changed, 11 insertions(+), 2 deletions(-)
21
22
diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/include/tcg/tcg-temp-internal.h
25
+++ b/include/tcg/tcg-temp-internal.h
26
@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
27
TCGv_ptr tcg_temp_ebb_new_ptr(void);
28
TCGv_i128 tcg_temp_ebb_new_i128(void);
29
30
+/* Forget all freed EBB temps, so that new allocations produce new temps. */
31
+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
32
+{
33
+ memset(s->free_temps, 0, sizeof(s->free_temps));
34
+}
35
+
36
#endif /* TCG_TEMP_FREE_H */
37
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/accel/tcg/plugin-gen.c
40
+++ b/accel/tcg/plugin-gen.c
41
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
42
* that might be live within the existing opcode stream.
43
* The simplest solution is to release them all and create new.
44
*/
45
- memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
46
+ tcg_temp_ebb_reset_freed(tcg_ctx);
47
48
QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
49
switch (op->opc) {
50
diff --git a/tcg/tcg.c b/tcg/tcg.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/tcg/tcg.c
53
+++ b/tcg/tcg.c
54
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
55
s->nb_temps = s->nb_globals;
56
57
/* No temps have been previously allocated for size or locality. */
58
- memset(s->free_temps, 0, sizeof(s->free_temps));
59
+ tcg_temp_ebb_reset_freed(s);
60
61
/* No constant temps have been previously allocated. */
62
for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
63
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
64
}
65
#endif
66
67
+ /* Do not reuse any EBB that may be allocated within the TB. */
68
+ tcg_temp_ebb_reset_freed(s);
69
+
70
tcg_optimize(s);
71
72
reachable_code_pass(s);
73
--
74
2.43.0
75
76
diff view generated by jsdifflib
[PULL 2/4] tcg/riscv: Fix StoreStore barrier generation
Deleted patch
1
From: Roman Artemev <roman.artemev@syntacore.com>
2
1
3
On RISC-V to StoreStore barrier corresponds
4
`fence w, w` not `fence r, r`
5
6
Cc: qemu-stable@nongnu.org
7
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
10
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
11
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
14
tcg/riscv/tcg-target.c.inc | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
18
index XXXXXXX..XXXXXXX 100644
19
--- a/tcg/riscv/tcg-target.c.inc
20
+++ b/tcg/riscv/tcg-target.c.inc
21
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
22
insn |= 0x02100000;
23
}
24
if (a0 & TCG_MO_ST_ST) {
25
- insn |= 0x02200000;
26
+ insn |= 0x01100000;
27
}
28
tcg_out32(s, insn);
29
}
30
--
31
2.43.0
diff view generated by jsdifflib
[PULL 3/4] include/exec: Introduce fpst alias in helper-head.h.inc
Deleted patch
1
This allows targets to declare that the helper requires a
2
float_status pointer and instead of a generic void pointer.
3
1
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
include/exec/helper-head.h.inc | 3 +++
8
1 file changed, 3 insertions(+)
9
10
diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/include/exec/helper-head.h.inc
13
+++ b/include/exec/helper-head.h.inc
14
@@ -XXX,XX +XXX,XX @@
15
#define dh_alias_ptr ptr
16
#define dh_alias_cptr ptr
17
#define dh_alias_env ptr
18
+#define dh_alias_fpst ptr
19
#define dh_alias_void void
20
#define dh_alias_noreturn noreturn
21
#define dh_alias(t) glue(dh_alias_, t)
22
@@ -XXX,XX +XXX,XX @@
23
#define dh_ctype_ptr void *
24
#define dh_ctype_cptr const void *
25
#define dh_ctype_env CPUArchState *
26
+#define dh_ctype_fpst float_status *
27
#define dh_ctype_void void
28
#define dh_ctype_noreturn G_NORETURN void
29
#define dh_ctype(t) dh_ctype_##t
30
@@ -XXX,XX +XXX,XX @@
31
#define dh_typecode_f64 dh_typecode_i64
32
#define dh_typecode_cptr dh_typecode_ptr
33
#define dh_typecode_env dh_typecode_ptr
34
+#define dh_typecode_fpst dh_typecode_ptr
35
#define dh_typecode(t) dh_typecode_##t
36
37
#define dh_callflag_i32 0
38
--
39
2.43.0
40
41
diff view generated by jsdifflib
[PULL 4/4] target/sparc: Use memcpy() and remove memcpy32()
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Rather than manually copying each register, use
4
the libc memcpy(), which is well optimized nowadays.
5
6
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-ID: <20241205205418.67613-1-philmd@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
13
target/sparc/win_helper.c | 26 ++++++++------------------
14
1 file changed, 8 insertions(+), 18 deletions(-)
15
16
diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/sparc/win_helper.c
19
+++ b/target/sparc/win_helper.c
20
@@ -XXX,XX +XXX,XX @@
21
#include "exec/helper-proto.h"
22
#include "trace.h"
23
24
-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
25
-{
26
- dst[0] = src[0];
27
- dst[1] = src[1];
28
- dst[2] = src[2];
29
- dst[3] = src[3];
30
- dst[4] = src[4];
31
- dst[5] = src[5];
32
- dst[6] = src[6];
33
- dst[7] = src[7];
34
-}
35
-
36
void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
37
{
38
/* put the modified wrap registers at their proper location */
39
if (env->cwp == env->nwindows - 1) {
40
- memcpy32(env->regbase, env->regbase + env->nwindows * 16);
41
+ memcpy(env->regbase, env->regbase + env->nwindows * 16,
42
+ sizeof(env->gregs));
43
}
44
env->cwp = new_cwp;
45
46
/* put the wrap registers at their temporary location */
47
if (new_cwp == env->nwindows - 1) {
48
- memcpy32(env->regbase + env->nwindows * 16, env->regbase);
49
+ memcpy(env->regbase + env->nwindows * 16, env->regbase,
50
+ sizeof(env->gregs));
51
}
52
env->regwptr = env->regbase + (new_cwp * 16);
53
}
54
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
55
dst = get_gl_gregset(env, env->gl);
56
57
if (src != dst) {
58
- memcpy32(dst, env->gregs);
59
- memcpy32(env->gregs, src);
60
+ memcpy(dst, env->gregs, sizeof(env->gregs));
61
+ memcpy(env->gregs, src, sizeof(env->gregs));
62
}
63
}
64
65
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
66
/* Switch global register bank */
67
src = get_gregset(env, new_pstate_regs);
68
dst = get_gregset(env, pstate_regs);
69
- memcpy32(dst, env->gregs);
70
- memcpy32(env->gregs, src);
71
+ memcpy(dst, env->gregs, sizeof(env->gregs));
72
+ memcpy(env->gregs, src, sizeof(env->gregs));
73
} else {
74
trace_win_helper_no_switch_pstate(new_pstate_regs);
75
}
76
--
77
2.43.0
78
79
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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