[PATCH] hw/cxl: Fix msix_notify: Assertion `vector < dev->msix_entries_nr`
[PATCH v2] hw/cxl: Fix msix_notify: Assertion `vector < dev->msix_entries_nr`
1
This assertion always happens when we sanitize the CXL memory device.
1
This assertion always happens when we sanitize the CXL memory device.
2
$ echo 1 > /sys/bus/cxl/devices/mem0/security/sanitize
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$ echo 1 > /sys/bus/cxl/devices/mem0/security/sanitize
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3
4
It is incorrect to register an MSIX number beyond the device's capability.
4
It is incorrect to register an MSIX number beyond the device's capability.
5
5
6
Expand the device's MSIX to 10 and introduce the `request_msix_number()`
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Expand the device's MSIX number and use the enum to maintain the *USED*
7
helper function to dynamically request an available MSIX number.
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and MAX MSIX number
8
8
9
Fixes: 43efb0bfad2b ("hw/cxl/mbox: Wire up interrupts for background completion")
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Fixes: 43efb0bfad2b ("hw/cxl/mbox: Wire up interrupts for background completion")
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Signed-off-by: Li Zhijian <lizhijian@fujitsu.com>
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Signed-off-by: Li Zhijian <lizhijian@fujitsu.com>
11
---
11
---
12
hw/cxl/cxl-device-utils.c | 3 ++-
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V2: just increase msix number and add enum to maintainer their values #
13
hw/mem/cxl_type3.c | 15 ++++++++++++++-
13
Jonathan
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include/hw/cxl/cxl_device.h | 2 ++
14
---
15
3 files changed, 18 insertions(+), 2 deletions(-)
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hw/cxl/cxl-device-utils.c | 6 ++----
16
hw/mem/cxl_type3.c | 10 +++++-----
17
include/hw/cxl/cxl_device.h | 7 +++++++
18
3 files changed, 14 insertions(+), 9 deletions(-)
16
19
17
diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c
20
diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c
18
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/cxl/cxl-device-utils.c
22
--- a/hw/cxl/cxl-device-utils.c
20
+++ b/hw/cxl/cxl-device-utils.c
23
+++ b/hw/cxl/cxl-device-utils.c
21
@@ -XXX,XX +XXX,XX @@ static void device_reg_init_common(CXLDeviceState *cxl_dstate)
24
@@ -XXX,XX +XXX,XX @@ static void device_reg_init_common(CXLDeviceState *cxl_dstate)
22
25
23
static void mailbox_reg_init_common(CXLDeviceState *cxl_dstate)
26
static void mailbox_reg_init_common(CXLDeviceState *cxl_dstate)
24
{
27
{
25
- const uint8_t msi_n = 9;
28
- const uint8_t msi_n = 9;
26
+ uint8_t msi_n = cxl_request_msi_number();
29
-
27
28
+ assert(msi_n > 0);
29
/* 2048 payload size */
30
/* 2048 payload size */
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ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
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ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
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PAYLOAD_SIZE, CXL_MAILBOX_PAYLOAD_SHIFT);
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PAYLOAD_SIZE, CXL_MAILBOX_PAYLOAD_SHIFT);
33
@@ -XXX,XX +XXX,XX @@ static void mailbox_reg_init_common(CXLDeviceState *cxl_dstate)
34
ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
35
BG_INT_CAP, 1);
36
ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
37
- MSI_N, msi_n);
38
- cxl_dstate->mbox_msi_n = msi_n;
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+ MSI_N, CXL_MSIX_MBOX);
40
+ cxl_dstate->mbox_msi_n = CXL_MSIX_MBOX;
41
ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
42
MBOX_READY_TIME, 0); /* Not reported */
43
ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
32
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
44
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
33
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/mem/cxl_type3.c
46
--- a/hw/mem/cxl_type3.c
35
+++ b/hw/mem/cxl_type3.c
47
+++ b/hw/mem/cxl_type3.c
36
@@ -XXX,XX +XXX,XX @@ static DOEProtocol doe_cdat_prot[] = {
37
{ }
38
};
39
40
+#define CT3_MSIX_NUM 10
41
+unsigned short cxl_request_msi_number(void)
42
+{
43
+ const unsigned short start = 6;
44
+ static unsigned short next = start;
45
+
46
+ if (next + 1 >= CT3_MSIX_NUM) {
47
+ return -1;
48
+ }
49
+
50
+ return ++next;
51
+}
52
+
53
static void ct3_realize(PCIDevice *pci_dev, Error **errp)
54
{
55
ERRP_GUARD();
56
@@ -XXX,XX +XXX,XX @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
48
@@ -XXX,XX +XXX,XX @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
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ComponentRegisters *regs = &cxl_cstate->crb;
49
ComponentRegisters *regs = &cxl_cstate->crb;
58
MemoryRegion *mr = &regs->component_registers;
50
MemoryRegion *mr = &regs->component_registers;
59
uint8_t *pci_conf = pci_dev->config;
51
uint8_t *pci_conf = pci_dev->config;
60
- unsigned short msix_num = 6;
52
- unsigned short msix_num = 6;
61
+ unsigned short msix_num = CT3_MSIX_NUM;
62
int i, rc;
53
int i, rc;
63
uint16_t count;
54
uint16_t count;
64
55
56
@@ -XXX,XX +XXX,XX @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
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&ct3d->cxl_dstate.device_registers);
58
59
/* MSI(-X) Initialization */
60
- rc = msix_init_exclusive_bar(pci_dev, msix_num, 4, NULL);
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+ rc = msix_init_exclusive_bar(pci_dev, CXL_MSIX_MAX, 4, NULL);
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if (rc) {
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goto err_address_space_free;
64
}
65
- for (i = 0; i < msix_num; i++) {
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+ for (i = 0; i < CXL_MSIX_MAX; i++) {
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msix_vector_use(pci_dev, i);
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}
69
70
/* DOE Initialization */
71
- pcie_doe_init(pci_dev, &ct3d->doe_cdat, 0x190, doe_cdat_prot, true, 0);
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+ pcie_doe_init(pci_dev, &ct3d->doe_cdat, 0x190, doe_cdat_prot, true,
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+ CXL_MSIX_PCIE_DOE);
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75
cxl_cstate->cdat.build_cdat_table = ct3_build_cdat_table;
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cxl_cstate->cdat.free_cdat_table = ct3_free_cdat_table;
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@@ -XXX,XX +XXX,XX @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
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if (rc) {
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goto err_release_cdat;
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}
81
- cxl_event_init(&ct3d->cxl_dstate, 2);
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+ cxl_event_init(&ct3d->cxl_dstate, CXL_MSIX_EVENT_START);
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84
/* Set default value for patrol scrub attributes */
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ct3d->patrol_scrub_attrs.scrub_cycle_cap =
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diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
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diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
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index XXXXXXX..XXXXXXX 100644
87
index XXXXXXX..XXXXXXX 100644
67
--- a/include/hw/cxl/cxl_device.h
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--- a/include/hw/cxl/cxl_device.h
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+++ b/include/hw/cxl/cxl_device.h
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+++ b/include/hw/cxl/cxl_device.h
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@@ -XXX,XX +XXX,XX @@ void ct3_clear_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,
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@@ -XXX,XX +XXX,XX @@ typedef enum {
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uint64_t len);
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CXL_MBOX_MAX = 0x20
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bool ct3_test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,
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} CXLRetCode;
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uint64_t len);
93
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+unsigned short cxl_request_msi_number(void);
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+enum {
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+ CXL_MSIX_PCIE_DOE = 0,
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+ CXL_MSIX_EVENT_START = 2,
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+ CXL_MSIX_MBOX = CXL_MSIX_EVENT_START + CXL_EVENT_TYPE_MAX,
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+ CXL_MSIX_MAX
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+};
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+
100
+
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#endif
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typedef struct CXLCCI CXLCCI;
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typedef struct cxl_device_state CXLDeviceState;
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struct cxl_cmd;
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--
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--
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2.41.0
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2.41.0
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