To prepare to support another USB PCI Host Controller, make some PCI
configuration dynamic.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 hw/usb/hcd-xhci-pci.h |  9 ++++++
 hw/usb/hcd-xhci-nec.c | 10 +++++++
 hw/usb/hcd-xhci-pci.c | 69 ++++++++++++++++++++++++++++++++++++-------
 3 files changed, 78 insertions(+), 10 deletions(-)

diff --git a/hw/usb/hcd-xhci-pci.h b/hw/usb/hcd-xhci-pci.h
index 08f70ce97cc..213076aabf6 100644
--- a/hw/usb/hcd-xhci-pci.h
+++ b/hw/usb/hcd-xhci-pci.h
@@ -40,6 +40,15 @@ typedef struct XHCIPciState {
     XHCIState xhci;
     OnOffAuto msi;
     OnOffAuto msix;
+    uint8_t cache_line_size;
+    uint8_t pm_cap_off;
+    uint8_t pcie_cap_off;
+    uint8_t msi_cap_off;
+    uint8_t msix_cap_off;
+    int msix_bar_nr;
+    uint64_t msix_bar_size;
+    uint32_t msix_table_off;
+    uint32_t msix_pba_off;
 } XHCIPciState;
 
 #endif
diff --git a/hw/usb/hcd-xhci-nec.c b/hw/usb/hcd-xhci-nec.c
index 0e61c6c4f06..6ac1dc7764c 100644
--- a/hw/usb/hcd-xhci-nec.c
+++ b/hw/usb/hcd-xhci-nec.c
@@ -52,6 +52,16 @@ static void nec_xhci_instance_init(Object *obj)
 
     pci->xhci.numintrs = nec->intrs;
     pci->xhci.numslots = nec->slots;
+
+    pci->cache_line_size = 0x10;
+    pci->pm_cap_off = 0;
+    pci->pcie_cap_off = 0xa0;
+    pci->msi_cap_off = 0x70;
+    pci->msix_cap_off = 0x90;
+    pci->msix_bar_nr = 0;
+    pci->msix_bar_size = 0;
+    pci->msix_table_off = 0x3000;
+    pci->msix_pba_off = 0x3800;
 }
 
 static void nec_xhci_class_init(ObjectClass *klass, void *data)
diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c
index a039f5778a6..948d75b7379 100644
--- a/hw/usb/hcd-xhci-pci.c
+++ b/hw/usb/hcd-xhci-pci.c
@@ -32,8 +32,9 @@
 #include "trace.h"
 #include "qapi/error.h"
 
-#define OFF_MSIX_TABLE  0x3000
-#define OFF_MSIX_PBA    0x3800
+#define MSIX_BAR_SIZE   0x800000
+#define OFF_MSIX_TABLE  0x0000
+#define OFF_MSIX_PBA    0x1000
 
 static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable)
 {
@@ -104,6 +105,31 @@ static int xhci_pci_vmstate_post_load(void *opaque, int version_id)
    return 0;
 }
 
+static int xhci_pci_add_pm_capability(PCIDevice *pci_dev, uint8_t offset,
+                                      Error **errp)
+{
+    int err;
+
+    err = pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset,
+                             PCI_PM_SIZEOF, errp);
+    if (err < 0) {
+        return err;
+    }
+
+    pci_set_word(pci_dev->config + offset + PCI_PM_PMC,
+                 PCI_PM_CAP_VER_1_2 |
+                 PCI_PM_CAP_D1 | PCI_PM_CAP_D2 |
+                 PCI_PM_CAP_PME_D0 | PCI_PM_CAP_PME_D1 |
+                 PCI_PM_CAP_PME_D2 | PCI_PM_CAP_PME_D3hot);
+    pci_set_word(pci_dev->wmask + offset + PCI_PM_PMC, 0);
+    pci_set_word(pci_dev->config + offset + PCI_PM_CTRL,
+                 PCI_PM_CTRL_NO_SOFT_RESET);
+    pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL,
+                 PCI_PM_CTRL_STATE_MASK);
+
+    return 0;
+}
+
 static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
 {
     int ret;
@@ -112,7 +138,7 @@ static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
 
     dev->config[PCI_CLASS_PROG] = 0x30;    /* xHCI */
     dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
-    dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
+    dev->config[PCI_CACHE_LINE_SIZE] = s->cache_line_size;
     dev->config[0x60] = 0x30; /* release number */
 
     object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL);
@@ -125,8 +151,16 @@ static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
         s->xhci.nec_quirks = true;
     }
 
+    if (s->pm_cap_off) {
+        if (xhci_pci_add_pm_capability(dev, s->pm_cap_off, &err)) {
+            error_propagate(errp, err);
+            return;
+        }
+    }
+
     if (s->msi != ON_OFF_AUTO_OFF) {
-        ret = msi_init(dev, 0x70, s->xhci.numintrs, true, false, &err);
+        ret = msi_init(dev, s->msi_cap_off, s->xhci.numintrs,
+                       true, false, &err);
         /*
          * Any error other than -ENOTSUP(board's MSI support is broken)
          * is a programming error
@@ -143,22 +177,37 @@ static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
         /* With msi=auto, we fall back to MSI off silently */
         error_free(err);
     }
+
     pci_register_bar(dev, 0,
                      PCI_BASE_ADDRESS_SPACE_MEMORY |
                      PCI_BASE_ADDRESS_MEM_TYPE_64,
                      &s->xhci.mem);
 
     if (pci_bus_is_express(pci_get_bus(dev))) {
-        ret = pcie_endpoint_cap_init(dev, 0xa0);
+        ret = pcie_endpoint_cap_init(dev, s->pcie_cap_off);
         assert(ret > 0);
     }
 
     if (s->msix != ON_OFF_AUTO_OFF) {
-        /* TODO check for errors, and should fail when msix=on */
-        msix_init(dev, s->xhci.numintrs,
-                  &s->xhci.mem, 0, OFF_MSIX_TABLE,
-                  &s->xhci.mem, 0, OFF_MSIX_PBA,
-                  0x90, NULL);
+        MemoryRegion *msix_bar = &s->xhci.mem;
+        if (s->msix_bar_nr != 0) {
+            memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev),
+                               "xhci-msix", s->msix_bar_size);
+            msix_bar = &dev->msix_exclusive_bar;
+        }
+
+        ret = msix_init(dev, s->xhci.numintrs,
+                        msix_bar, s->msix_bar_nr, s->msix_table_off,
+                        msix_bar, s->msix_bar_nr, s->msix_pba_off,
+                        s->msix_cap_off, errp);
+        if (ret) {
+            return;
+        }
+
+        pci_register_bar(dev, s->msix_bar_nr,
+                         PCI_BASE_ADDRESS_SPACE_MEMORY |
+                         PCI_BASE_ADDRESS_MEM_TYPE_64,
+                         msix_bar);
     }
     s->xhci.as = pci_get_address_space(dev);
 }
-- 
2.45.2

On 2024/12/12 17:52, Nicholas Piggin wrote:
> To prepare to support another USB PCI Host Controller, make some PCI
> configuration dynamic.
> 
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
>   hw/usb/hcd-xhci-pci.h |  9 ++++++
>   hw/usb/hcd-xhci-nec.c | 10 +++++++
>   hw/usb/hcd-xhci-pci.c | 69 ++++++++++++++++++++++++++++++++++++-------
>   3 files changed, 78 insertions(+), 10 deletions(-)
> 
> diff --git a/hw/usb/hcd-xhci-pci.h b/hw/usb/hcd-xhci-pci.h
> index 08f70ce97cc..213076aabf6 100644
> --- a/hw/usb/hcd-xhci-pci.h
> +++ b/hw/usb/hcd-xhci-pci.h
> @@ -40,6 +40,15 @@ typedef struct XHCIPciState {
>       XHCIState xhci;
>       OnOffAuto msi;
>       OnOffAuto msix;
> +    uint8_t cache_line_size;
> +    uint8_t pm_cap_off;
> +    uint8_t pcie_cap_off;
> +    uint8_t msi_cap_off;
> +    uint8_t msix_cap_off;
> +    int msix_bar_nr;
> +    uint64_t msix_bar_size;
> +    uint32_t msix_table_off;
> +    uint32_t msix_pba_off;

Let's make these class variables so that they won't be duplicated for 
each instance.

>   } XHCIPciState;
>   
>   #endif
> diff --git a/hw/usb/hcd-xhci-nec.c b/hw/usb/hcd-xhci-nec.c
> index 0e61c6c4f06..6ac1dc7764c 100644
> --- a/hw/usb/hcd-xhci-nec.c
> +++ b/hw/usb/hcd-xhci-nec.c
> @@ -52,6 +52,16 @@ static void nec_xhci_instance_init(Object *obj)
>   
>       pci->xhci.numintrs = nec->intrs;
>       pci->xhci.numslots = nec->slots;
> +
> +    pci->cache_line_size = 0x10;
> +    pci->pm_cap_off = 0;
> +    pci->pcie_cap_off = 0xa0;
> +    pci->msi_cap_off = 0x70;
> +    pci->msix_cap_off = 0x90;
> +    pci->msix_bar_nr = 0;
> +    pci->msix_bar_size = 0;
> +    pci->msix_table_off = 0x3000;
> +    pci->msix_pba_off = 0x3800;
>   }
>   
>   static void nec_xhci_class_init(ObjectClass *klass, void *data)
> diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c
> index a039f5778a6..948d75b7379 100644
> --- a/hw/usb/hcd-xhci-pci.c
> +++ b/hw/usb/hcd-xhci-pci.c
> @@ -32,8 +32,9 @@
>   #include "trace.h"
>   #include "qapi/error.h"
>   
> -#define OFF_MSIX_TABLE  0x3000
> -#define OFF_MSIX_PBA    0x3800
> +#define MSIX_BAR_SIZE   0x800000
> +#define OFF_MSIX_TABLE  0x0000
> +#define OFF_MSIX_PBA    0x1000
>   
>   static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable)
>   {
> @@ -104,6 +105,31 @@ static int xhci_pci_vmstate_post_load(void *opaque, int version_id)
>      return 0;
>   }
>   
> +static int xhci_pci_add_pm_capability(PCIDevice *pci_dev, uint8_t offset,
> +                                      Error **errp)
> +{
> +    int err;
> +
> +    err = pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset,
> +                             PCI_PM_SIZEOF, errp);
> +    if (err < 0) {
> +        return err;
> +    }
> +
> +    pci_set_word(pci_dev->config + offset + PCI_PM_PMC,
> +                 PCI_PM_CAP_VER_1_2 |
> +                 PCI_PM_CAP_D1 | PCI_PM_CAP_D2 |
> +                 PCI_PM_CAP_PME_D0 | PCI_PM_CAP_PME_D1 |
> +                 PCI_PM_CAP_PME_D2 | PCI_PM_CAP_PME_D3hot);
> +    pci_set_word(pci_dev->wmask + offset + PCI_PM_PMC, 0);
> +    pci_set_word(pci_dev->config + offset + PCI_PM_CTRL,
> +                 PCI_PM_CTRL_NO_SOFT_RESET);
> +    pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL,
> +                 PCI_PM_CTRL_STATE_MASK);
> +
> +    return 0;
> +}
> +
>   static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
>   {
>       int ret;
> @@ -112,7 +138,7 @@ static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
>   
>       dev->config[PCI_CLASS_PROG] = 0x30;    /* xHCI */
>       dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
> -    dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
> +    dev->config[PCI_CACHE_LINE_SIZE] = s->cache_line_size;
>       dev->config[0x60] = 0x30; /* release number */
>   
>       object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL);
> @@ -125,8 +151,16 @@ static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
>           s->xhci.nec_quirks = true;
>       }
>   
> +    if (s->pm_cap_off) {
> +        if (xhci_pci_add_pm_capability(dev, s->pm_cap_off, &err)) {
> +            error_propagate(errp, err);

Pass errp to xhci_pci_add_pm_capability() and avoid error_propagate().
include/qapi/error.h has more explanation.

> +            return;
> +        }
> +    }
> +
>       if (s->msi != ON_OFF_AUTO_OFF) {
> -        ret = msi_init(dev, 0x70, s->xhci.numintrs, true, false, &err);
> +        ret = msi_init(dev, s->msi_cap_off, s->xhci.numintrs,
> +                       true, false, &err);
>           /*
>            * Any error other than -ENOTSUP(board's MSI support is broken)
>            * is a programming error
> @@ -143,22 +177,37 @@ static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
>           /* With msi=auto, we fall back to MSI off silently */
>           error_free(err);
>       }
> +
>       pci_register_bar(dev, 0,
>                        PCI_BASE_ADDRESS_SPACE_MEMORY |
>                        PCI_BASE_ADDRESS_MEM_TYPE_64,
>                        &s->xhci.mem);
>   
>       if (pci_bus_is_express(pci_get_bus(dev))) {
> -        ret = pcie_endpoint_cap_init(dev, 0xa0);
> +        ret = pcie_endpoint_cap_init(dev, s->pcie_cap_off);
>           assert(ret > 0);
>       }
>   
>       if (s->msix != ON_OFF_AUTO_OFF) {
> -        /* TODO check for errors, and should fail when msix=on */
> -        msix_init(dev, s->xhci.numintrs,
> -                  &s->xhci.mem, 0, OFF_MSIX_TABLE,
> -                  &s->xhci.mem, 0, OFF_MSIX_PBA,
> -                  0x90, NULL);
> +        MemoryRegion *msix_bar = &s->xhci.mem;
> +        if (s->msix_bar_nr != 0) {
> +            memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev),
> +                               "xhci-msix", s->msix_bar_size);
> +            msix_bar = &dev->msix_exclusive_bar;
> +        }
> +
> +        ret = msix_init(dev, s->xhci.numintrs,
> +                        msix_bar, s->msix_bar_nr, s->msix_table_off,
> +                        msix_bar, s->msix_bar_nr, s->msix_pba_off,
> +                        s->msix_cap_off, errp);
> +        if (ret) {
> +            return;
> +        }
> +
> +        pci_register_bar(dev, s->msix_bar_nr,
> +                         PCI_BASE_ADDRESS_SPACE_MEMORY |
> +                         PCI_BASE_ADDRESS_MEM_TYPE_64,
> +                         msix_bar);
>       }
>       s->xhci.as = pci_get_address_space(dev);
>   }

Hey Nicholas,

I'm not an XHCI & PCI expert (yet?) so apologies if I've got some of this
wrong, but I've asked some questions and made some comments inline:

On Thu, 12 Dec 2024 at 09:52, Nicholas Piggin <npiggin@gmail.com> wrote:

> To prepare to support another USB PCI Host Controller, make some PCI
> configuration dynamic.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
>  hw/usb/hcd-xhci-pci.h |  9 ++++++
>  hw/usb/hcd-xhci-nec.c | 10 +++++++
>  hw/usb/hcd-xhci-pci.c | 69 ++++++++++++++++++++++++++++++++++++-------
>  3 files changed, 78 insertions(+), 10 deletions(-)
>
> diff --git a/hw/usb/hcd-xhci-pci.h b/hw/usb/hcd-xhci-pci.h
> index 08f70ce97cc..213076aabf6 100644
> --- a/hw/usb/hcd-xhci-pci.h
> +++ b/hw/usb/hcd-xhci-pci.h
> @@ -40,6 +40,15 @@ typedef struct XHCIPciState {
>      XHCIState xhci;
>      OnOffAuto msi;
>      OnOffAuto msix;
> +    uint8_t cache_line_size;
> +    uint8_t pm_cap_off;
> +    uint8_t pcie_cap_off;
> +    uint8_t msi_cap_off;
> +    uint8_t msix_cap_off;
> +    int msix_bar_nr;
> +    uint64_t msix_bar_size;
> +    uint32_t msix_table_off;
> +    uint32_t msix_pba_off;
>  } XHCIPciState;
>
>  #endif
> diff --git a/hw/usb/hcd-xhci-nec.c b/hw/usb/hcd-xhci-nec.c
> index 0e61c6c4f06..6ac1dc7764c 100644
> --- a/hw/usb/hcd-xhci-nec.c
> +++ b/hw/usb/hcd-xhci-nec.c
> @@ -52,6 +52,16 @@ static void nec_xhci_instance_init(Object *obj)
>
>      pci->xhci.numintrs = nec->intrs;
>      pci->xhci.numslots = nec->slots;
> +
> +    pci->cache_line_size = 0x10;
> +    pci->pm_cap_off = 0;
> +    pci->pcie_cap_off = 0xa0;
> +    pci->msi_cap_off = 0x70;
> +    pci->msix_cap_off = 0x90;
> +    pci->msix_bar_nr = 0;
> +    pci->msix_bar_size = 0;
> +    pci->msix_table_off = 0x3000;
> +    pci->msix_pba_off = 0x3800;
>  }


What about the "qemu-xhci" device, does that need similar treatment? I
suspect it does at least for a bunch of these settings. Perhaps
xhci_instance_init() in the abstract "pci-xhci" base might be a better
place for these "sensible defaults" and then override them only in the
specific implementations that need to do so, such as the new TI model?
And/or have suitably named helper init function for configuring single-BAR
PCI XHCI controllers so we can get some meaning behind all these magic
numbers?


>  static void nec_xhci_class_init(ObjectClass *klass, void *data)
> diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c
> index a039f5778a6..948d75b7379 100644
> --- a/hw/usb/hcd-xhci-pci.c
> +++ b/hw/usb/hcd-xhci-pci.c
> @@ -32,8 +32,9 @@
>  #include "trace.h"
>  #include "qapi/error.h"
>
> -#define OFF_MSIX_TABLE  0x3000
> -#define OFF_MSIX_PBA    0x3800
> +#define MSIX_BAR_SIZE   0x800000
>

MSIX_BAR_SIZE doesn't seem to be used anywhere, and patch 2/2 uses 0x800000
explicitly. (8 MiB also seems… huge? But I'm guessing you're matching this
with the physical TI controller hardware - either way I don't think it
belongs in this file.)


> +#define OFF_MSIX_TABLE  0x0000
> +#define OFF_MSIX_PBA    0x1000
>

Maybe instead of redefining these constants to only apply to the split BAR
device variants, there should be 2 variants of them, one for single-BAR
controllers, and one for controllers with separate BARs. That would also
help make sense of the "magic numbers" in nec_xhci_instance_init().



>  static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable)
>  {
> @@ -104,6 +105,31 @@ static int xhci_pci_vmstate_post_load(void *opaque,
> int version_id)
>     return 0;
>  }
>
> +static int xhci_pci_add_pm_capability(PCIDevice *pci_dev, uint8_t offset,
> +                                      Error **errp)
> +{
> +    int err;
> +
> +    err = pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset,
> +                             PCI_PM_SIZEOF, errp);
> +    if (err < 0) {
> +        return err;
> +    }
> +
> +    pci_set_word(pci_dev->config + offset + PCI_PM_PMC,
> +                 PCI_PM_CAP_VER_1_2 |
> +                 PCI_PM_CAP_D1 | PCI_PM_CAP_D2 |
> +                 PCI_PM_CAP_PME_D0 | PCI_PM_CAP_PME_D1 |
> +                 PCI_PM_CAP_PME_D2 | PCI_PM_CAP_PME_D3hot);
> +    pci_set_word(pci_dev->wmask + offset + PCI_PM_PMC, 0);
> +    pci_set_word(pci_dev->config + offset + PCI_PM_CTRL,
> +                 PCI_PM_CTRL_NO_SOFT_RESET);
> +    pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL,
> +                 PCI_PM_CTRL_STATE_MASK);
> +
> +    return 0;
> +}
> +
>  static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
>  {
>      int ret;
> @@ -112,7 +138,7 @@ static void usb_xhci_pci_realize(struct PCIDevice
> *dev, Error **errp)
>
>      dev->config[PCI_CLASS_PROG] = 0x30;    /* xHCI */
>      dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
> -    dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
> +    dev->config[PCI_CACHE_LINE_SIZE] = s->cache_line_size;
>      dev->config[0x60] = 0x30; /* release number */
>
>      object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL);
> @@ -125,8 +151,16 @@ static void usb_xhci_pci_realize(struct PCIDevice
> *dev, Error **errp)
>          s->xhci.nec_quirks = true;
>      }
>
> +    if (s->pm_cap_off) {
> +        if (xhci_pci_add_pm_capability(dev, s->pm_cap_off, &err)) {
> +            error_propagate(errp, err);
> +            return;
>

Can't we just pass errp straight to xhci_pci_add_pm_capability and skip the
error_propagate() here?


> +        }
> +    }
> +
>      if (s->msi != ON_OFF_AUTO_OFF) {
> -        ret = msi_init(dev, 0x70, s->xhci.numintrs, true, false, &err);
> +        ret = msi_init(dev, s->msi_cap_off, s->xhci.numintrs,
> +                       true, false, &err);
>          /*
>           * Any error other than -ENOTSUP(board's MSI support is broken)
>           * is a programming error
> @@ -143,22 +177,37 @@ static void usb_xhci_pci_realize(struct PCIDevice
> *dev, Error **errp)
>          /* With msi=auto, we fall back to MSI off silently */
>          error_free(err);
>      }
> +
>      pci_register_bar(dev, 0,
>                       PCI_BASE_ADDRESS_SPACE_MEMORY |
>                       PCI_BASE_ADDRESS_MEM_TYPE_64,
>                       &s->xhci.mem);
>
>      if (pci_bus_is_express(pci_get_bus(dev))) {
> -        ret = pcie_endpoint_cap_init(dev, 0xa0);
> +        ret = pcie_endpoint_cap_init(dev, s->pcie_cap_off);
>          assert(ret > 0);
>      }
>
>      if (s->msix != ON_OFF_AUTO_OFF) {
> -        /* TODO check for errors, and should fail when msix=on */
> -        msix_init(dev, s->xhci.numintrs,
> -                  &s->xhci.mem, 0, OFF_MSIX_TABLE,
> -                  &s->xhci.mem, 0, OFF_MSIX_PBA,
> -                  0x90, NULL);
> +        MemoryRegion *msix_bar = &s->xhci.mem;
> +        if (s->msix_bar_nr != 0) {
> +            memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev),
> +                               "xhci-msix", s->msix_bar_size);
> +            msix_bar = &dev->msix_exclusive_bar;
> +        }
> +
> +        ret = msix_init(dev, s->xhci.numintrs,
> +                        msix_bar, s->msix_bar_nr, s->msix_table_off,
> +                        msix_bar, s->msix_bar_nr, s->msix_pba_off,
> +                        s->msix_cap_off, errp);
> +        if (ret) {
> +            return;
> +        }
>

Surely we should only propagate the error and fail realize() iff s->msix is
ON_OFF_AUTO_ON?

For ON_OFF_AUTO_AUTO, msix_init returning failure isn't a critical error.


> +
> +        pci_register_bar(dev, s->msix_bar_nr,
> +                         PCI_BASE_ADDRESS_SPACE_MEMORY |
> +                         PCI_BASE_ADDRESS_MEM_TYPE_64,
> +                         msix_bar);
>

Is it safe to call pci_register_bar() again for the msix_bar_nr = 0 case?
Even if it is safe, is it sensible? If we're calling it twice for the same
BAR, and the arguments of either of the calls changes in future, the other
needs to change too. Doesn't seem ideal.


>      }
>      s->xhci.as = pci_get_address_space(dev);
>  }
> --
> 2.45.2
>
>

On Thu Dec 12, 2024 at 8:41 PM AEST, Phil Dennis-Jordan wrote:
> Hey Nicholas,
>
> I'm not an XHCI & PCI expert (yet?) so apologies if I've got some of this
> wrong, but I've asked some questions and made some comments inline:

Hey Phil,

Thanks for the review, looks like you are the expert now :)

>
> On Thu, 12 Dec 2024 at 09:52, Nicholas Piggin <npiggin@gmail.com> wrote:
>
> > To prepare to support another USB PCI Host Controller, make some PCI
> > configuration dynamic.
> >
> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> > ---
> >  hw/usb/hcd-xhci-pci.h |  9 ++++++
> >  hw/usb/hcd-xhci-nec.c | 10 +++++++
> >  hw/usb/hcd-xhci-pci.c | 69 ++++++++++++++++++++++++++++++++++++-------
> >  3 files changed, 78 insertions(+), 10 deletions(-)
> >
> > diff --git a/hw/usb/hcd-xhci-pci.h b/hw/usb/hcd-xhci-pci.h
> > index 08f70ce97cc..213076aabf6 100644
> > --- a/hw/usb/hcd-xhci-pci.h
> > +++ b/hw/usb/hcd-xhci-pci.h
> > @@ -40,6 +40,15 @@ typedef struct XHCIPciState {
> >      XHCIState xhci;
> >      OnOffAuto msi;
> >      OnOffAuto msix;
> > +    uint8_t cache_line_size;
> > +    uint8_t pm_cap_off;
> > +    uint8_t pcie_cap_off;
> > +    uint8_t msi_cap_off;
> > +    uint8_t msix_cap_off;
> > +    int msix_bar_nr;
> > +    uint64_t msix_bar_size;
> > +    uint32_t msix_table_off;
> > +    uint32_t msix_pba_off;
> >  } XHCIPciState;
> >
> >  #endif
> > diff --git a/hw/usb/hcd-xhci-nec.c b/hw/usb/hcd-xhci-nec.c
> > index 0e61c6c4f06..6ac1dc7764c 100644
> > --- a/hw/usb/hcd-xhci-nec.c
> > +++ b/hw/usb/hcd-xhci-nec.c
> > @@ -52,6 +52,16 @@ static void nec_xhci_instance_init(Object *obj)
> >
> >      pci->xhci.numintrs = nec->intrs;
> >      pci->xhci.numslots = nec->slots;
> > +
> > +    pci->cache_line_size = 0x10;
> > +    pci->pm_cap_off = 0;
> > +    pci->pcie_cap_off = 0xa0;
> > +    pci->msi_cap_off = 0x70;
> > +    pci->msix_cap_off = 0x90;
> > +    pci->msix_bar_nr = 0;
> > +    pci->msix_bar_size = 0;
> > +    pci->msix_table_off = 0x3000;
> > +    pci->msix_pba_off = 0x3800;
> >  }
>
>
> What about the "qemu-xhci" device, does that need similar treatment? I
> suspect it does at least for a bunch of these settings. Perhaps
> xhci_instance_init() in the abstract "pci-xhci" base might be a better
> place for these "sensible defaults" and then override them only in the
> specific implementations that need to do so, such as the new TI model?
> And/or have suitably named helper init function for configuring single-BAR
> PCI XHCI controllers so we can get some meaning behind all these magic
> numbers?

No you're right, I missed this entirely and the qemu-xhci dev is
indeed broken after this patch. Just moving it into the parent
instance init gets it to work.

> >  static void nec_xhci_class_init(ObjectClass *klass, void *data)
> > diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c
> > index a039f5778a6..948d75b7379 100644
> > --- a/hw/usb/hcd-xhci-pci.c
> > +++ b/hw/usb/hcd-xhci-pci.c
> > @@ -32,8 +32,9 @@
> >  #include "trace.h"
> >  #include "qapi/error.h"
> >
> > -#define OFF_MSIX_TABLE  0x3000
> > -#define OFF_MSIX_PBA    0x3800
> > +#define MSIX_BAR_SIZE   0x800000
> >
>
> MSIX_BAR_SIZE doesn't seem to be used anywhere, and patch 2/2 uses 0x800000
> explicitly. (8 MiB also seems… huge? But I'm guessing you're matching this
> with the physical TI controller hardware - either way I don't think it
> belongs in this file.)
>
>
> > +#define OFF_MSIX_TABLE  0x0000
> > +#define OFF_MSIX_PBA    0x1000
> >
>
> Maybe instead of redefining these constants to only apply to the split BAR
> device variants, there should be 2 variants of them, one for single-BAR
> controllers, and one for controllers with separate BARs. That would also
> help make sense of the "magic numbers" in nec_xhci_instance_init().

You're right on both counts, I tidied these up.

> >  static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable)
> >  {
> > @@ -104,6 +105,31 @@ static int xhci_pci_vmstate_post_load(void *opaque,
> > int version_id)
> >     return 0;
> >  }
> >
> > +static int xhci_pci_add_pm_capability(PCIDevice *pci_dev, uint8_t offset,
> > +                                      Error **errp)
> > +{
> > +    int err;
> > +
> > +    err = pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset,
> > +                             PCI_PM_SIZEOF, errp);
> > +    if (err < 0) {
> > +        return err;
> > +    }
> > +
> > +    pci_set_word(pci_dev->config + offset + PCI_PM_PMC,
> > +                 PCI_PM_CAP_VER_1_2 |
> > +                 PCI_PM_CAP_D1 | PCI_PM_CAP_D2 |
> > +                 PCI_PM_CAP_PME_D0 | PCI_PM_CAP_PME_D1 |
> > +                 PCI_PM_CAP_PME_D2 | PCI_PM_CAP_PME_D3hot);
> > +    pci_set_word(pci_dev->wmask + offset + PCI_PM_PMC, 0);
> > +    pci_set_word(pci_dev->config + offset + PCI_PM_CTRL,
> > +                 PCI_PM_CTRL_NO_SOFT_RESET);
> > +    pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL,
> > +                 PCI_PM_CTRL_STATE_MASK);
> > +
> > +    return 0;
> > +}
> > +
> >  static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
> >  {
> >      int ret;
> > @@ -112,7 +138,7 @@ static void usb_xhci_pci_realize(struct PCIDevice
> > *dev, Error **errp)
> >
> >      dev->config[PCI_CLASS_PROG] = 0x30;    /* xHCI */
> >      dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
> > -    dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
> > +    dev->config[PCI_CACHE_LINE_SIZE] = s->cache_line_size;
> >      dev->config[0x60] = 0x30; /* release number */
> >
> >      object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL);
> > @@ -125,8 +151,16 @@ static void usb_xhci_pci_realize(struct PCIDevice
> > *dev, Error **errp)
> >          s->xhci.nec_quirks = true;
> >      }
> >
> > +    if (s->pm_cap_off) {
> > +        if (xhci_pci_add_pm_capability(dev, s->pm_cap_off, &err)) {
> > +            error_propagate(errp, err);
> > +            return;
> >
>
> Can't we just pass errp straight to xhci_pci_add_pm_capability and skip the
> error_propagate() here?

Yes I think so.

> > +        }
> > +    }
> > +
> >      if (s->msi != ON_OFF_AUTO_OFF) {
> > -        ret = msi_init(dev, 0x70, s->xhci.numintrs, true, false, &err);
> > +        ret = msi_init(dev, s->msi_cap_off, s->xhci.numintrs,
> > +                       true, false, &err);
> >          /*
> >           * Any error other than -ENOTSUP(board's MSI support is broken)
> >           * is a programming error
> > @@ -143,22 +177,37 @@ static void usb_xhci_pci_realize(struct PCIDevice
> > *dev, Error **errp)
> >          /* With msi=auto, we fall back to MSI off silently */
> >          error_free(err);
> >      }
> > +
> >      pci_register_bar(dev, 0,
> >                       PCI_BASE_ADDRESS_SPACE_MEMORY |
> >                       PCI_BASE_ADDRESS_MEM_TYPE_64,
> >                       &s->xhci.mem);
> >
> >      if (pci_bus_is_express(pci_get_bus(dev))) {
> > -        ret = pcie_endpoint_cap_init(dev, 0xa0);
> > +        ret = pcie_endpoint_cap_init(dev, s->pcie_cap_off);
> >          assert(ret > 0);
> >      }
> >
> >      if (s->msix != ON_OFF_AUTO_OFF) {
> > -        /* TODO check for errors, and should fail when msix=on */
> > -        msix_init(dev, s->xhci.numintrs,
> > -                  &s->xhci.mem, 0, OFF_MSIX_TABLE,
> > -                  &s->xhci.mem, 0, OFF_MSIX_PBA,
> > -                  0x90, NULL);
> > +        MemoryRegion *msix_bar = &s->xhci.mem;
> > +        if (s->msix_bar_nr != 0) {
> > +            memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev),
> > +                               "xhci-msix", s->msix_bar_size);
> > +            msix_bar = &dev->msix_exclusive_bar;
> > +        }
> > +
> > +        ret = msix_init(dev, s->xhci.numintrs,
> > +                        msix_bar, s->msix_bar_nr, s->msix_table_off,
> > +                        msix_bar, s->msix_bar_nr, s->msix_pba_off,
> > +                        s->msix_cap_off, errp);
> > +        if (ret) {
> > +            return;
> > +        }
> >
>
> Surely we should only propagate the error and fail realize() iff s->msix is
> ON_OFF_AUTO_ON?
>
> For ON_OFF_AUTO_AUTO, msix_init returning failure isn't a critical error.

Yep you're right... you had been testing with msix disabled. I wonder if
there is a good way to force fail this in qtests?

> > +
> > +        pci_register_bar(dev, s->msix_bar_nr,
> > +                         PCI_BASE_ADDRESS_SPACE_MEMORY |
> > +                         PCI_BASE_ADDRESS_MEM_TYPE_64,
> > +                         msix_bar);
> >
>
> Is it safe to call pci_register_bar() again for the msix_bar_nr = 0 case?
> Even if it is safe, is it sensible? If we're calling it twice for the same
> BAR, and the arguments of either of the calls changes in future, the other
> needs to change too. Doesn't seem ideal.

Good catch. It looks like it "works" so long as the bar wasn't mapped,
but I'm sure bad practice... Interesting there is no assertion in
there though. I'll fix it though.

Thanks,
Nick

On Wed, 18 Dec 2024 at 02:19, Nicholas Piggin <npiggin@gmail.com> wrote:

> On Thu Dec 12, 2024 at 8:41 PM AEST, Phil Dennis-Jordan wrote:
> > Hey Nicholas,
> >
> > I'm not an XHCI & PCI expert (yet?) so apologies if I've got some of this
> > wrong, but I've asked some questions and made some comments inline:
>
> Hey Phil,
>
> Thanks for the review, looks like you are the expert now :)
>

The "hot potato" method for determining maintainership. :-)


> >
> > On Thu, 12 Dec 2024 at 09:52, Nicholas Piggin <npiggin@gmail.com> wrote:
> >
> > > To prepare to support another USB PCI Host Controller, make some PCI
> > > configuration dynamic.
> > >
> > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> > > ---
> > >  hw/usb/hcd-xhci-pci.h |  9 ++++++
> > >  hw/usb/hcd-xhci-nec.c | 10 +++++++
> > >  hw/usb/hcd-xhci-pci.c | 69 ++++++++++++++++++++++++++++++++++++-------
> > >  3 files changed, 78 insertions(+), 10 deletions(-)
> > >
> > > diff --git a/hw/usb/hcd-xhci-pci.h b/hw/usb/hcd-xhci-pci.h
> > > index 08f70ce97cc..213076aabf6 100644
> > > --- a/hw/usb/hcd-xhci-pci.h
> > > +++ b/hw/usb/hcd-xhci-pci.h
> > > @@ -40,6 +40,15 @@ typedef struct XHCIPciState {
> > >      XHCIState xhci;
> > >      OnOffAuto msi;
> > >      OnOffAuto msix;
> > > +    uint8_t cache_line_size;
> > > +    uint8_t pm_cap_off;
> > > +    uint8_t pcie_cap_off;
> > > +    uint8_t msi_cap_off;
> > > +    uint8_t msix_cap_off;
> > > +    int msix_bar_nr;
> > > +    uint64_t msix_bar_size;
> > > +    uint32_t msix_table_off;
> > > +    uint32_t msix_pba_off;
> > >  } XHCIPciState;
> > >
> > >  #endif
> > > diff --git a/hw/usb/hcd-xhci-nec.c b/hw/usb/hcd-xhci-nec.c
> > > index 0e61c6c4f06..6ac1dc7764c 100644
> > > --- a/hw/usb/hcd-xhci-nec.c
> > > +++ b/hw/usb/hcd-xhci-nec.c
> > > @@ -52,6 +52,16 @@ static void nec_xhci_instance_init(Object *obj)
> > >
> > >      pci->xhci.numintrs = nec->intrs;
> > >      pci->xhci.numslots = nec->slots;
> > > +
> > > +    pci->cache_line_size = 0x10;
> > > +    pci->pm_cap_off = 0;
> > > +    pci->pcie_cap_off = 0xa0;
> > > +    pci->msi_cap_off = 0x70;
> > > +    pci->msix_cap_off = 0x90;
> > > +    pci->msix_bar_nr = 0;
> > > +    pci->msix_bar_size = 0;
> > > +    pci->msix_table_off = 0x3000;
> > > +    pci->msix_pba_off = 0x3800;
> > >  }
> >
> >
> > What about the "qemu-xhci" device, does that need similar treatment? I
> > suspect it does at least for a bunch of these settings. Perhaps
> > xhci_instance_init() in the abstract "pci-xhci" base might be a better
> > place for these "sensible defaults" and then override them only in the
> > specific implementations that need to do so, such as the new TI model?
> > And/or have suitably named helper init function for configuring
> single-BAR
> > PCI XHCI controllers so we can get some meaning behind all these magic
> > numbers?
>
> No you're right, I missed this entirely and the qemu-xhci dev is
> indeed broken after this patch. Just moving it into the parent
> instance init gets it to work.
>
> > >  static void nec_xhci_class_init(ObjectClass *klass, void *data)
> > > diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c
> > > index a039f5778a6..948d75b7379 100644
> > > --- a/hw/usb/hcd-xhci-pci.c
> > > +++ b/hw/usb/hcd-xhci-pci.c
> > > @@ -32,8 +32,9 @@
> > >  #include "trace.h"
> > >  #include "qapi/error.h"
> > >
> > > -#define OFF_MSIX_TABLE  0x3000
> > > -#define OFF_MSIX_PBA    0x3800
> > > +#define MSIX_BAR_SIZE   0x800000
> > >
> >
> > MSIX_BAR_SIZE doesn't seem to be used anywhere, and patch 2/2 uses
> 0x800000
> > explicitly. (8 MiB also seems… huge? But I'm guessing you're matching
> this
> > with the physical TI controller hardware - either way I don't think it
> > belongs in this file.)
> >
> >
> > > +#define OFF_MSIX_TABLE  0x0000
> > > +#define OFF_MSIX_PBA    0x1000
> > >
> >
> > Maybe instead of redefining these constants to only apply to the split
> BAR
> > device variants, there should be 2 variants of them, one for single-BAR
> > controllers, and one for controllers with separate BARs. That would also
> > help make sense of the "magic numbers" in nec_xhci_instance_init().
>
> You're right on both counts, I tidied these up.
>
> > >  static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable)
> > >  {
> > > @@ -104,6 +105,31 @@ static int xhci_pci_vmstate_post_load(void
> *opaque,
> > > int version_id)
> > >     return 0;
> > >  }
> > >
> > > +static int xhci_pci_add_pm_capability(PCIDevice *pci_dev, uint8_t
> offset,
> > > +                                      Error **errp)
> > > +{
> > > +    int err;
> > > +
> > > +    err = pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset,
> > > +                             PCI_PM_SIZEOF, errp);
> > > +    if (err < 0) {
> > > +        return err;
> > > +    }
> > > +
> > > +    pci_set_word(pci_dev->config + offset + PCI_PM_PMC,
> > > +                 PCI_PM_CAP_VER_1_2 |
> > > +                 PCI_PM_CAP_D1 | PCI_PM_CAP_D2 |
> > > +                 PCI_PM_CAP_PME_D0 | PCI_PM_CAP_PME_D1 |
> > > +                 PCI_PM_CAP_PME_D2 | PCI_PM_CAP_PME_D3hot);
> > > +    pci_set_word(pci_dev->wmask + offset + PCI_PM_PMC, 0);
> > > +    pci_set_word(pci_dev->config + offset + PCI_PM_CTRL,
> > > +                 PCI_PM_CTRL_NO_SOFT_RESET);
> > > +    pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL,
> > > +                 PCI_PM_CTRL_STATE_MASK);
> > > +
> > > +    return 0;
> > > +}
> > > +
> > >  static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
> > >  {
> > >      int ret;
> > > @@ -112,7 +138,7 @@ static void usb_xhci_pci_realize(struct PCIDevice
> > > *dev, Error **errp)
> > >
> > >      dev->config[PCI_CLASS_PROG] = 0x30;    /* xHCI */
> > >      dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
> > > -    dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
> > > +    dev->config[PCI_CACHE_LINE_SIZE] = s->cache_line_size;
> > >      dev->config[0x60] = 0x30; /* release number */
> > >
> > >      object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s),
> NULL);
> > > @@ -125,8 +151,16 @@ static void usb_xhci_pci_realize(struct PCIDevice
> > > *dev, Error **errp)
> > >          s->xhci.nec_quirks = true;
> > >      }
> > >
> > > +    if (s->pm_cap_off) {
> > > +        if (xhci_pci_add_pm_capability(dev, s->pm_cap_off, &err)) {
> > > +            error_propagate(errp, err);
> > > +            return;
> > >
> >
> > Can't we just pass errp straight to xhci_pci_add_pm_capability and skip
> the
> > error_propagate() here?
>
> Yes I think so.
>
> > > +        }
> > > +    }
> > > +
> > >      if (s->msi != ON_OFF_AUTO_OFF) {
> > > -        ret = msi_init(dev, 0x70, s->xhci.numintrs, true, false,
> &err);
> > > +        ret = msi_init(dev, s->msi_cap_off, s->xhci.numintrs,
> > > +                       true, false, &err);
> > >          /*
> > >           * Any error other than -ENOTSUP(board's MSI support is
> broken)
> > >           * is a programming error
> > > @@ -143,22 +177,37 @@ static void usb_xhci_pci_realize(struct PCIDevice
> > > *dev, Error **errp)
> > >          /* With msi=auto, we fall back to MSI off silently */
> > >          error_free(err);
> > >      }
> > > +
> > >      pci_register_bar(dev, 0,
> > >                       PCI_BASE_ADDRESS_SPACE_MEMORY |
> > >                       PCI_BASE_ADDRESS_MEM_TYPE_64,
> > >                       &s->xhci.mem);
> > >
> > >      if (pci_bus_is_express(pci_get_bus(dev))) {
> > > -        ret = pcie_endpoint_cap_init(dev, 0xa0);
> > > +        ret = pcie_endpoint_cap_init(dev, s->pcie_cap_off);
> > >          assert(ret > 0);
> > >      }
> > >
> > >      if (s->msix != ON_OFF_AUTO_OFF) {
> > > -        /* TODO check for errors, and should fail when msix=on */
> > > -        msix_init(dev, s->xhci.numintrs,
> > > -                  &s->xhci.mem, 0, OFF_MSIX_TABLE,
> > > -                  &s->xhci.mem, 0, OFF_MSIX_PBA,
> > > -                  0x90, NULL);
> > > +        MemoryRegion *msix_bar = &s->xhci.mem;
> > > +        if (s->msix_bar_nr != 0) {
> > > +            memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev),
> > > +                               "xhci-msix", s->msix_bar_size);
> > > +            msix_bar = &dev->msix_exclusive_bar;
> > > +        }
> > > +
> > > +        ret = msix_init(dev, s->xhci.numintrs,
> > > +                        msix_bar, s->msix_bar_nr, s->msix_table_off,
> > > +                        msix_bar, s->msix_bar_nr, s->msix_pba_off,
> > > +                        s->msix_cap_off, errp);
> > > +        if (ret) {
> > > +            return;
> > > +        }
> > >
> >
> > Surely we should only propagate the error and fail realize() iff s->msix
> is
> > ON_OFF_AUTO_ON?
> >
> > For ON_OFF_AUTO_AUTO, msix_init returning failure isn't a critical error.
>
> Yep you're right... you had been testing with msix disabled. I wonder if
> there is a good way to force fail this in qtests?
>

I'm really the wrong person to ask about qtest, I'm only just beginning to
get to grips with it. It seems the only real reason msix_init fails other
than misconfiguration of the device/BAR is when msi_nonbroken = false.

At least on x86(-64), msi_nonbroken=true is unconditionally set in
apic_realize(). (I think real hardware would not support MSI(-X) on the
i440FX chipset - I was fairly certain it was the PCI root/southbridge
catching the writes to the reserved memory region, and I didn't think the
PIIX did this; but at least in QEMU it doesn't seem to be implemented in a
chipset-dependent way.) I'm not sure it's possible to run QEMU without an
APIC?

On aarch64, the GICv3 needs to explicitly enable support (via the ITS), so
perhaps it's possible to set up an aarch64 qtest with ITS disabled? It
looks like the 'virt' machine type only supports the ITS from version 6.2,
so older versions will disable it.

Sorry, clutching at straws here.


> > > +
> > > +        pci_register_bar(dev, s->msix_bar_nr,
> > > +                         PCI_BASE_ADDRESS_SPACE_MEMORY |
> > > +                         PCI_BASE_ADDRESS_MEM_TYPE_64,
> > > +                         msix_bar);
> > >
> >
> > Is it safe to call pci_register_bar() again for the msix_bar_nr = 0 case?
> > Even if it is safe, is it sensible? If we're calling it twice for the
> same
> > BAR, and the arguments of either of the calls changes in future, the
> other
> > needs to change too. Doesn't seem ideal.
>
> Good catch. It looks like it "works" so long as the bar wasn't mapped,
> but I'm sure bad practice... Interesting there is no assertion in
> there though. I'll fix it though.
>

I notice there's a msix_init_exclusive_bar()… I wonder if it'd be simpler
to use that and modify it so it allows you to choose a size and layout for
the BAR, rather than adding all that extra code to deal with the extra BAR
in the XHCI?
(It already calls pci_register_bar() and msix_init() internally, but seems
to set the BAR's size to 4096 and places the PBA at halfway through the
BAR. Perhaps rename it to something like
msix_init_exclusive_bar_with_layout and pass the bar_size and
bar_pba_offset in as parameters; then make msix_init_exclusive_bar() a
wrapper for that function with the existing defaults for those variables?)

Just kicking around some ideas here, I have no idea if that actually ends
up making things simpler…


> Thanks,
> Nick
>

On Wed, 18 Dec 2024, Phil Dennis-Jordan wrote:
> On Wed, 18 Dec 2024 at 02:19, Nicholas Piggin <npiggin@gmail.com> wrote:
>> On Thu Dec 12, 2024 at 8:41 PM AEST, Phil Dennis-Jordan wrote:
>>> Hey Nicholas,
>>>
>>> I'm not an XHCI & PCI expert (yet?) so apologies if I've got some of this
>>> wrong, but I've asked some questions and made some comments inline:
>>
>> Hey Phil,
>>
>> Thanks for the review, looks like you are the expert now :)
>>
>
> The "hot potato" method for determining maintainership. :-)

That's how I got some parts I'm maintainer of now. :-)

[...]
>>> On Thu, 12 Dec 2024 at 09:52, Nicholas Piggin <npiggin@gmail.com> wrote:
>>> Surely we should only propagate the error and fail realize() iff s->msix
>> is
>>> ON_OFF_AUTO_ON?
>>>
>>> For ON_OFF_AUTO_AUTO, msix_init returning failure isn't a critical error.
>>
>> Yep you're right... you had been testing with msix disabled. I wonder if
>> there is a good way to force fail this in qtests?
>>
>
> I'm really the wrong person to ask about qtest, I'm only just beginning to
> get to grips with it. It seems the only real reason msix_init fails other
> than misconfiguration of the device/BAR is when msi_nonbroken = false.
>
> At least on x86(-64), msi_nonbroken=true is unconditionally set in
> apic_realize(). (I think real hardware would not support MSI(-X) on the
> i440FX chipset - I was fairly certain it was the PCI root/southbridge
> catching the writes to the reserved memory region, and I didn't think the
> PIIX did this; but at least in QEMU it doesn't seem to be implemented in a
> chipset-dependent way.) I'm not sure it's possible to run QEMU without an
> APIC?

There's isapc but you can't attach PCI card to that. It seems according to 
-machine pc,help that there's a PIC=<OnOffAuto> option but no similar for 
APIC. Maybe that could be added but not sure it would work. (Adding 
Bernhard to cc to quickly pass on the potato.)

Regards,
BALATON Zoltan

> On aarch64, the GICv3 needs to explicitly enable support (via the ITS), so
> perhaps it's possible to set up an aarch64 qtest with ITS disabled? It
> looks like the 'virt' machine type only supports the ITS from version 6.2,
> so older versions will disable it.
>
> Sorry, clutching at straws here.
>
>
>>>> +
>>>> +        pci_register_bar(dev, s->msix_bar_nr,
>>>> +                         PCI_BASE_ADDRESS_SPACE_MEMORY |
>>>> +                         PCI_BASE_ADDRESS_MEM_TYPE_64,
>>>> +                         msix_bar);
>>>>
>>>
>>> Is it safe to call pci_register_bar() again for the msix_bar_nr = 0 case?
>>> Even if it is safe, is it sensible? If we're calling it twice for the
>> same
>>> BAR, and the arguments of either of the calls changes in future, the
>> other
>>> needs to change too. Doesn't seem ideal.
>>
>> Good catch. It looks like it "works" so long as the bar wasn't mapped,
>> but I'm sure bad practice... Interesting there is no assertion in
>> there though. I'll fix it though.
>>
>
> I notice there's a msix_init_exclusive_bar()… I wonder if it'd be simpler
> to use that and modify it so it allows you to choose a size and layout for
> the BAR, rather than adding all that extra code to deal with the extra BAR
> in the XHCI?
> (It already calls pci_register_bar() and msix_init() internally, but seems
> to set the BAR's size to 4096 and places the PBA at halfway through the
> BAR. Perhaps rename it to something like
> msix_init_exclusive_bar_with_layout and pass the bar_size and
> bar_pba_offset in as parameters; then make msix_init_exclusive_bar() a
> wrapper for that function with the existing defaults for those variables?)
>
> Just kicking around some ideas here, I have no idea if that actually ends
> up making things simpler…
>
>
>> Thanks,
>> Nick
>>
>

Am 19. Dezember 2024 09:23:13 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>:
>On Wed, 18 Dec 2024, Phil Dennis-Jordan wrote:
>> On Wed, 18 Dec 2024 at 02:19, Nicholas Piggin <npiggin@gmail.com> wrote:
>>> On Thu Dec 12, 2024 at 8:41 PM AEST, Phil Dennis-Jordan wrote:
>>>> Hey Nicholas,
>>>> 
>>>> I'm not an XHCI & PCI expert (yet?) so apologies if I've got some of this
>>>> wrong, but I've asked some questions and made some comments inline:
>>> 
>>> Hey Phil,
>>> 
>>> Thanks for the review, looks like you are the expert now :)
>>> 
>> 
>> The "hot potato" method for determining maintainership. :-)
>
>That's how I got some parts I'm maintainer of now. :-)
>
>[...]
>>>> On Thu, 12 Dec 2024 at 09:52, Nicholas Piggin <npiggin@gmail.com> wrote:
>>>> Surely we should only propagate the error and fail realize() iff s->msix
>>> is
>>>> ON_OFF_AUTO_ON?
>>>> 
>>>> For ON_OFF_AUTO_AUTO, msix_init returning failure isn't a critical error.
>>> 
>>> Yep you're right... you had been testing with msix disabled. I wonder if
>>> there is a good way to force fail this in qtests?
>>> 
>> 
>> I'm really the wrong person to ask about qtest, I'm only just beginning to
>> get to grips with it. It seems the only real reason msix_init fails other
>> than misconfiguration of the device/BAR is when msi_nonbroken = false.
>> 
>> At least on x86(-64), msi_nonbroken=true is unconditionally set in
>> apic_realize(). (I think real hardware would not support MSI(-X) on the
>> i440FX chipset - I was fairly certain it was the PCI root/southbridge
>> catching the writes to the reserved memory region, and I didn't think the
>> PIIX did this; but at least in QEMU it doesn't seem to be implemented in a
>> chipset-dependent way.) I'm not sure it's possible to run QEMU without an
>> APIC?
>
>There's isapc but you can't attach PCI card to that. It seems according to -machine pc,help that there's a PIC=<OnOffAuto> option but no similar for APIC. Maybe that could be added but not sure it would work. (Adding Bernhard to cc to quickly pass on the potato.)

I agree, the only x86 machine with no APIC is the isapc machine. All others (i440fx, q35, microvm) have it always enabled. I guess there is just no point in disabling it since the APIC is part of the architecture for ages and SMP requires it. Although PIIX3+ didn't have an APIC built-in it had interfaces for handling a dedicated one which is basically what QEMU emulates.

Best regards,
Bernhard

>
>Regards,
>BALATON Zoltan
>
>> On aarch64, the GICv3 needs to explicitly enable support (via the ITS), so
>> perhaps it's possible to set up an aarch64 qtest with ITS disabled? It
>> looks like the 'virt' machine type only supports the ITS from version 6.2,
>> so older versions will disable it.
>> 
>> Sorry, clutching at straws here.
>> 
>> 
>>>>> +
>>>>> +        pci_register_bar(dev, s->msix_bar_nr,
>>>>> +                         PCI_BASE_ADDRESS_SPACE_MEMORY |
>>>>> +                         PCI_BASE_ADDRESS_MEM_TYPE_64,
>>>>> +                         msix_bar);
>>>>> 
>>>> 
>>>> Is it safe to call pci_register_bar() again for the msix_bar_nr = 0 case?
>>>> Even if it is safe, is it sensible? If we're calling it twice for the
>>> same
>>>> BAR, and the arguments of either of the calls changes in future, the
>>> other
>>>> needs to change too. Doesn't seem ideal.
>>> 
>>> Good catch. It looks like it "works" so long as the bar wasn't mapped,
>>> but I'm sure bad practice... Interesting there is no assertion in
>>> there though. I'll fix it though.
>>> 
>> 
>> I notice there's a msix_init_exclusive_bar()… I wonder if it'd be simpler
>> to use that and modify it so it allows you to choose a size and layout for
>> the BAR, rather than adding all that extra code to deal with the extra BAR
>> in the XHCI?
>> (It already calls pci_register_bar() and msix_init() internally, but seems
>> to set the BAR's size to 4096 and places the PBA at halfway through the
>> BAR. Perhaps rename it to something like
>> msix_init_exclusive_bar_with_layout and pass the bar_size and
>> bar_pba_offset in as parameters; then make msix_init_exclusive_bar() a
>> wrapper for that function with the existing defaults for those variables?)
>> 
>> Just kicking around some ideas here, I have no idea if that actually ends
>> up making things simpler…
>> 
>> 
>>> Thanks,
>>> Nick
>>> 
>>

On Thu Dec 19, 2024 at 7:06 AM AEST, Phil Dennis-Jordan wrote:
> On Wed, 18 Dec 2024 at 02:19, Nicholas Piggin <npiggin@gmail.com> wrote:
>
> > On Thu Dec 12, 2024 at 8:41 PM AEST, Phil Dennis-Jordan wrote:

[...]

> > > > @@ -143,22 +177,37 @@ static void usb_xhci_pci_realize(struct PCIDevice
> > > > *dev, Error **errp)
> > > >          /* With msi=auto, we fall back to MSI off silently */
> > > >          error_free(err);
> > > >      }
> > > > +
> > > >      pci_register_bar(dev, 0,
> > > >                       PCI_BASE_ADDRESS_SPACE_MEMORY |
> > > >                       PCI_BASE_ADDRESS_MEM_TYPE_64,
> > > >                       &s->xhci.mem);
> > > >
> > > >      if (pci_bus_is_express(pci_get_bus(dev))) {
> > > > -        ret = pcie_endpoint_cap_init(dev, 0xa0);
> > > > +        ret = pcie_endpoint_cap_init(dev, s->pcie_cap_off);
> > > >          assert(ret > 0);
> > > >      }
> > > >
> > > >      if (s->msix != ON_OFF_AUTO_OFF) {
> > > > -        /* TODO check for errors, and should fail when msix=on */
> > > > -        msix_init(dev, s->xhci.numintrs,
> > > > -                  &s->xhci.mem, 0, OFF_MSIX_TABLE,
> > > > -                  &s->xhci.mem, 0, OFF_MSIX_PBA,
> > > > -                  0x90, NULL);
> > > > +        MemoryRegion *msix_bar = &s->xhci.mem;
> > > > +        if (s->msix_bar_nr != 0) {
> > > > +            memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev),
> > > > +                               "xhci-msix", s->msix_bar_size);
> > > > +            msix_bar = &dev->msix_exclusive_bar;
> > > > +        }
> > > > +
> > > > +        ret = msix_init(dev, s->xhci.numintrs,
> > > > +                        msix_bar, s->msix_bar_nr, s->msix_table_off,
> > > > +                        msix_bar, s->msix_bar_nr, s->msix_pba_off,
> > > > +                        s->msix_cap_off, errp);
> > > > +        if (ret) {
> > > > +            return;
> > > > +        }
> > > >
> > >
> > > Surely we should only propagate the error and fail realize() iff s->msix
> > is
> > > ON_OFF_AUTO_ON?
> > >
> > > For ON_OFF_AUTO_AUTO, msix_init returning failure isn't a critical error.
> >
> > Yep you're right... you had been testing with msix disabled. I wonder if
> > there is a good way to force fail this in qtests?
> >
>
> I'm really the wrong person to ask about qtest, I'm only just beginning to
> get to grips with it.

I'm not an expert in it, for the most part it can set up a machine as
usual, but the test case itself pokes at the machine directly by
talking to an interface on the host that can run memory access, qmp
commands, etc.

Can just make things easier and faster to set up and orchestrate than
doing it from within the target machine code.

> It seems the only real reason msix_init fails other
> than misconfiguration of the device/BAR is when msi_nonbroken = false.
>
> At least on x86(-64), msi_nonbroken=true is unconditionally set in
> apic_realize(). (I think real hardware would not support MSI(-X) on the
> i440FX chipset - I was fairly certain it was the PCI root/southbridge
> catching the writes to the reserved memory region, and I didn't think the
> PIIX did this; but at least in QEMU it doesn't seem to be implemented in a
> chipset-dependent way.) I'm not sure it's possible to run QEMU without an
> APIC?
>
> On aarch64, the GICv3 needs to explicitly enable support (via the ITS), so
> perhaps it's possible to set up an aarch64 qtest with ITS disabled? It
> looks like the 'virt' machine type only supports the ITS from version 6.2,
> so older versions will disable it.
>
> Sorry, clutching at straws here.

No that's okay, thanks for the input. Finding a platform with
broken msi could be an interesting test. I'll check it out.

> > > > +
> > > > +        pci_register_bar(dev, s->msix_bar_nr,
> > > > +                         PCI_BASE_ADDRESS_SPACE_MEMORY |
> > > > +                         PCI_BASE_ADDRESS_MEM_TYPE_64,
> > > > +                         msix_bar);
> > > >
> > >
> > > Is it safe to call pci_register_bar() again for the msix_bar_nr = 0 case?
> > > Even if it is safe, is it sensible? If we're calling it twice for the
> > same
> > > BAR, and the arguments of either of the calls changes in future, the
> > other
> > > needs to change too. Doesn't seem ideal.
> >
> > Good catch. It looks like it "works" so long as the bar wasn't mapped,
> > but I'm sure bad practice... Interesting there is no assertion in
> > there though. I'll fix it though.
> >
>
> I notice there's a msix_init_exclusive_bar()… I wonder if it'd be simpler
> to use that and modify it so it allows you to choose a size and layout for
> the BAR, rather than adding all that extra code to deal with the extra BAR
> in the XHCI?
> (It already calls pci_register_bar() and msix_init() internally, but seems
> to set the BAR's size to 4096 and places the PBA at halfway through the
> BAR. Perhaps rename it to something like
> msix_init_exclusive_bar_with_layout and pass the bar_size and
> bar_pba_offset in as parameters; then make msix_init_exclusive_bar() a
> wrapper for that function with the existing defaults for those variables?)
>
> Just kicking around some ideas here, I have no idea if that actually ends
> up making things simpler…

Yeah, I ended up beginning with that, but ended up running into some of
these issues and ended up being more code due to duplicating the non
exclusive case.

I'll stick with open-coding it for now, but it almost seems like there
could be an API call that could encompass exclusive and non-exclusive
cases in one. Would probably be good to have more than one caller before
trying to refactor it though.

Thanks,
Nick