target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Hardcoded 32 bytes is used for vbsrl emulation check, there is
problem when options lsx=on,lasx=off is used for vbsrl.v instruction
in TCG mode. It injects LASX exception rather LSX exception.
Here actual operand size is used.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
index 92b1d22e28..ba5ca98a33 100644
--- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
@@ -5126,7 +5126,7 @@ static bool do_vbsrl_v(DisasContext *ctx, arg_vv_i *a, uint32_t oprsz)
{
int i, ofs;
- if (!check_vec(ctx, 32)) {
+ if (!check_vec(ctx, oprsz)) {
return true;
}
base-commit: 1cf9bc6eba7506ab6d9de635f224259225f63466
--
2.39.3
On 12/12/24 09:22, Bibo Mao wrote: > Hardcoded 32 bytes is used for vbsrl emulation check, there is > problem when options lsx=on,lasx=off is used for vbsrl.v instruction > in TCG mode. It injects LASX exception rather LSX exception. > > Here actual operand size is used. > > Signed-off-by: Bibo Mao <maobibo@loongson.cn> > --- > target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Fixes: df97f338076 ("target/loongarch: Implement xvreplve xvinsve0 xvpickve") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
On 12/12/24 02:22, Bibo Mao wrote: > Hardcoded 32 bytes is used for vbsrl emulation check, there is > problem when options lsx=on,lasx=off is used for vbsrl.v instruction > in TCG mode. It injects LASX exception rather LSX exception. > > Here actual operand size is used. > > Signed-off-by: Bibo Mao <maobibo@loongson.cn> > --- > target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loongarch/tcg/insn_trans/trans_vec.c.inc > index 92b1d22e28..ba5ca98a33 100644 > --- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc > +++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc > @@ -5126,7 +5126,7 @@ static bool do_vbsrl_v(DisasContext *ctx, arg_vv_i *a, uint32_t oprsz) > { > int i, ofs; > > - if (!check_vec(ctx, 32)) { > + if (!check_vec(ctx, oprsz)) { > return true; > } > > > base-commit: 1cf9bc6eba7506ab6d9de635f224259225f63466 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
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