Hello,

Here is the aspeed series I plan to send as a PR this week.

- fix for the Aspeed I2C slave mode, an I2C echo device from Klaus

and its associated test in avocado.

- initial cleanups to allow the use of block devices instead of

drives on the command line.

- new facebook machines and eeprom fixes for the Fuji

- readline fix !

Thanks,

C.

Cédric Le Goater (4):

tests/avocado/machine_aspeed.py: Add an I2C slave test

aspeed: Introduce a spi_boot region under the SoC

aspeed: Add a boot_rom overlap region in the SoC spi_boot container

aspeed/smc: Replace SysBus IRQs with GPIO lines

Dongli Zhang (1):

readline: fix hmp completion issue

Karthikeyan Pasupathi (2):

hw/arm/aspeed: Adding new machine Yosemitev2 in QEMU

hw/arm/aspeed: Adding new machine Tiogapass in QEMU

Klaus Jensen (2):

hw/i2c: only schedule pending master when bus is idle

hw/misc: add a toy i2c echo device

Sittisak Sinprem (2):

hw/at24c : modify at24c to support 1 byte address mode

aspeed/fuji : correct the eeprom size

docs/system/arm/aspeed.rst | 2 +

hw/arm/aspeed_eeprom.h | 6 ++

include/hw/arm/aspeed_soc.h | 5 +

include/hw/i2c/i2c.h | 2 +

hw/arm/aspeed.c | 159 ++++++++++++++++++++++----------

hw/arm/aspeed_ast2600.c | 13 +++

hw/arm/aspeed_eeprom.c | 45 +++++++++

hw/arm/aspeed_soc.c | 14 +++

hw/arm/fby35.c | 8 +-

hw/i2c/aspeed_i2c.c | 2 +

hw/i2c/core.c | 37 +++++---

hw/misc/i2c-echo.c | 156 +++++++++++++++++++++++++++++++

hw/nvram/eeprom_at24c.c | 30 +++++-

hw/ssi/aspeed_smc.c | 5 +-

monitor/hmp.c | 8 +-

hw/misc/meson.build | 2 +

tests/avocado/machine_aspeed.py | 10 ++

17 files changed, 421 insertions(+), 83 deletions(-)

create mode 100644 hw/misc/i2c-echo.c

--

2.39.2

From: Dongli Zhang <dongli.zhang@oracle.com>

The auto completion does not work in some cases.

Case 1.

1. (qemu) info reg

2. Press 'Tab'.

3. It does not auto complete.

Case 2.

1. (qemu) block_resize flo

2. Press 'Tab'.

3. It does not auto complete 'floppy0'.

Since the readline_add_completion_of() may add any completion when

strlen(pfx) is zero, we remove the check with (name[0] == '\0') because

strlen() always returns zero in that case.

Fixes: 52f50b1e9f8f ("readline: Extract readline_add_completion_of() from monitor")

Cc: Joe Jin <joe.jin@oracle.com>

Signed-off-by: Dongli Zhang <dongli.zhang@oracle.com>

Tested-by: Thomas Huth <thuth@redhat.com>

Reviewed-by: Markus Armbruster <armbru@redhat.com>

Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

monitor/hmp.c | 8 ++------

1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/monitor/hmp.c b/monitor/hmp.c

--- a/monitor/hmp.c

+++ b/monitor/hmp.c

@@ -XXX,XX +XXX,XX @@ static void cmd_completion(MonitorHMP *mon, const char *name, const char *list)

}

memcpy(cmd, pstart, len);

cmd[len] = '\0';

- if (name[0] == '\0') {

- readline_add_completion_of(mon->rs, name, cmd);

- }

+ readline_add_completion_of(mon->rs, name, cmd);

if (*p == '\0') {

break;

}

@@ -XXX,XX +XXX,XX @@ static void monitor_find_completion_by_table(MonitorHMP *mon,

/* block device name completion */

readline_set_completion_index(mon->rs, strlen(str));

while ((blk = blk_next(blk)) != NULL) {

- if (str[0] == '\0') {

- readline_add_completion_of(mon->rs, str, blk_name(blk));

- }

+ readline_add_completion_of(mon->rs, str, blk_name(blk));

}

break;

case 's':

2.39.2

From: Klaus Jensen <k.jensen@samsung.com>

It is not given that the current master will release the bus after a

transfer ends. Only schedule a pending master if the bus is idle.

Fixes: 37fa5ca42623 ("hw/i2c: support multiple masters")

Signed-off-by: Klaus Jensen <k.jensen@samsung.com>

Acked-by: Corey Minyard <cminyard@mvista.com>

Message-Id: <20221116084312.35808-2-its@irrelevant.dk>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

include/hw/i2c/i2c.h | 2 ++

hw/i2c/aspeed_i2c.c | 2 ++

hw/i2c/core.c | 37 ++++++++++++++++++++++---------------

3 files changed, 26 insertions(+), 15 deletions(-)

diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h

--- a/include/hw/i2c/i2c.h

+++ b/include/hw/i2c/i2c.h

@@ -XXX,XX +XXX,XX @@ int i2c_start_send(I2CBus *bus, uint8_t address);

int i2c_start_send_async(I2CBus *bus, uint8_t address);

+void i2c_schedule_pending_master(I2CBus *bus);

+

void i2c_end_transfer(I2CBus *bus);

void i2c_nack(I2CBus *bus);

void i2c_ack(I2CBus *bus);

diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/i2c/aspeed_i2c.c

+++ b/hw/i2c/aspeed_i2c.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)

}

SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_STOP_CMD, 0);

aspeed_i2c_set_state(bus, I2CD_IDLE);

+

+ i2c_schedule_pending_master(bus->bus);

}

if (aspeed_i2c_bus_pkt_mode_en(bus)) {

diff --git a/hw/i2c/core.c b/hw/i2c/core.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/i2c/core.c

+++ b/hw/i2c/core.c

@@ -XXX,XX +XXX,XX @@ int i2c_start_transfer(I2CBus *bus, uint8_t address, bool is_recv)

void i2c_bus_master(I2CBus *bus, QEMUBH *bh)

- if (i2c_bus_busy(bus)) {

- I2CPendingMaster *node = g_new(struct I2CPendingMaster, 1);

- node->bh = bh;

+ I2CPendingMaster *node = g_new(struct I2CPendingMaster, 1);

+ node->bh = bh;

+

+ QSIMPLEQ_INSERT_TAIL(&bus->pending_masters, node, entry);

+}

+

+void i2c_schedule_pending_master(I2CBus *bus)

+{

+ I2CPendingMaster *node;

- QSIMPLEQ_INSERT_TAIL(&bus->pending_masters, node, entry);

+ if (i2c_bus_busy(bus)) {

+ /* someone is already controlling the bus; wait for it to release it */

+ return;

+ }

+ if (QSIMPLEQ_EMPTY(&bus->pending_masters)) {

return;

}

- bus->bh = bh;

+ node = QSIMPLEQ_FIRST(&bus->pending_masters);

+ bus->bh = node->bh;

+

+ QSIMPLEQ_REMOVE_HEAD(&bus->pending_masters, entry);

+ g_free(node);

+

qemu_bh_schedule(bus->bh);

void i2c_bus_release(I2CBus *bus)

bus->bh = NULL;

+

+ i2c_schedule_pending_master(bus);

int i2c_start_recv(I2CBus *bus, uint8_t address)

@@ -XXX,XX +XXX,XX @@ void i2c_end_transfer(I2CBus *bus)

g_free(node);

}

bus->broadcast = false;

-

- if (!QSIMPLEQ_EMPTY(&bus->pending_masters)) {

- I2CPendingMaster *node = QSIMPLEQ_FIRST(&bus->pending_masters);

- bus->bh = node->bh;

-

- QSIMPLEQ_REMOVE_HEAD(&bus->pending_masters, entry);

- g_free(node);

-

- qemu_bh_schedule(bus->bh);

- }

int i2c_send(I2CBus *bus, uint8_t data)

2.39.2

From: Klaus Jensen <k.jensen@samsung.com>

Add an example I2C device to demonstrate how a slave may master the bus

and send data asynchronously to another slave.

The device will echo whatever it is sent to the device identified by the

first byte received.

Signed-off-by: Klaus Jensen <k.jensen@samsung.com>

[ clg: integrated fixes :

https://lore.kernel.org/qemu-devel/Y3yMKAhOkYGtnkOp@cormorant.local/ ]

Message-Id: <20220601210831.67259-7-its@irrelevant.dk>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

hw/misc/i2c-echo.c | 156 ++++++++++++++++++++++++++++++++++++++++++++

hw/misc/meson.build | 2 +

2 files changed, 158 insertions(+)

create mode 100644 hw/misc/i2c-echo.c

diff --git a/hw/misc/i2c-echo.c b/hw/misc/i2c-echo.c

+++ b/hw/misc/i2c-echo.c

+#include "qemu/osdep.h"

+#include "qemu/timer.h"

+#include "qemu/main-loop.h"

+#include "block/aio.h"

+#include "hw/i2c/i2c.h"

+#define TYPE_I2C_ECHO "i2c-echo"

+OBJECT_DECLARE_SIMPLE_TYPE(I2CEchoState, I2C_ECHO)

+enum i2c_echo_state {

+ I2C_ECHO_STATE_IDLE,

+ I2C_ECHO_STATE_START_SEND,

+ I2C_ECHO_STATE_ACK,

+typedef struct I2CEchoState {

+ I2CSlave parent_obj;

+ I2CBus *bus;

+ enum i2c_echo_state state;

+ QEMUBH *bh;

+ unsigned int pos;

+ uint8_t data[3];

+} I2CEchoState;

+static void i2c_echo_bh(void *opaque)

+{

+ I2CEchoState *state = opaque;

+ switch (state->state) {

+ case I2C_ECHO_STATE_IDLE:

+ return;

+

+ case I2C_ECHO_STATE_START_SEND:

+ if (i2c_start_send_async(state->bus, state->data[0])) {

+ goto release_bus;

+ }

+

+ state->pos++;

+ state->state = I2C_ECHO_STATE_ACK;

+ return;

+

+ case I2C_ECHO_STATE_ACK:

+ if (state->pos > 2) {

+ break;

+ }

+

+ if (i2c_send_async(state->bus, state->data[state->pos++])) {

+ break;

+ }

+

+ return;

+ }

+

+

+ i2c_end_transfer(state->bus);

+release_bus:

+ i2c_bus_release(state->bus);

+

+ state->state = I2C_ECHO_STATE_IDLE;

+static int i2c_echo_event(I2CSlave *s, enum i2c_event event)

+ I2CEchoState *state = I2C_ECHO(s);

+

+ switch (event) {

+ case I2C_START_RECV:

+ state->pos = 0;

+

+ break;

+

+ case I2C_START_SEND:

+ state->pos = 0;

+

+ break;

+

+ case I2C_FINISH:

+ state->pos = 0;

+ state->state = I2C_ECHO_STATE_START_SEND;

+ i2c_bus_master(state->bus, state->bh);

+

+ break;

+

+ case I2C_NACK:

+ break;

+

+ default:

+ return -1;

+ }

+

+ return 0;

+static uint8_t i2c_echo_recv(I2CSlave *s)

+ I2CEchoState *state = I2C_ECHO(s);

+

+ if (state->pos > 2) {

+ return 0xff;

+ }

+

+ return state->data[state->pos++];

+static int i2c_echo_send(I2CSlave *s, uint8_t data)

+ I2CEchoState *state = I2C_ECHO(s);

+

+ if (state->pos > 2) {

+ return -1;

+ }

+

+ state->data[state->pos++] = data;

+

+ return 0;

+static void i2c_echo_realize(DeviceState *dev, Error **errp)

+ I2CEchoState *state = I2C_ECHO(dev);

+ BusState *bus = qdev_get_parent_bus(dev);

+

+ state->bus = I2C_BUS(bus);

+ state->bh = qemu_bh_new(i2c_echo_bh, state);

+

+ return;

+static void i2c_echo_class_init(ObjectClass *oc, void *data)

+ I2CSlaveClass *sc = I2C_SLAVE_CLASS(oc);

+ DeviceClass *dc = DEVICE_CLASS(oc);

+

+ dc->realize = i2c_echo_realize;

+

+ sc->event = i2c_echo_event;

+ sc->recv = i2c_echo_recv;

+ sc->send = i2c_echo_send;

+static const TypeInfo i2c_echo = {

+ .name = TYPE_I2C_ECHO,

+ .parent = TYPE_I2C_SLAVE,

+ .instance_size = sizeof(I2CEchoState),

+ .class_init = i2c_echo_class_init,

+};

+

+static void register_types(void)

+ type_register_static(&i2c_echo);

+type_init(register_types);

diff --git a/hw/misc/meson.build b/hw/misc/meson.build

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/meson.build

+++ b/hw/misc/meson.build

@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_rng.c'))

softmmu_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_ahb_apb_pnp.c'))

+softmmu_ss.add(when: 'CONFIG_I2C', if_true: files('i2c-echo.c'))

specific_ss.add(when: 'CONFIG_AVR_POWER', if_true: files('avr_power.c'))

specific_ss.add(when: 'CONFIG_MAC_VIA', if_true: files('mac_via.c'))