From: Glenn Miles <milesg@linux.ibm.com>
Added new test for pool interrupts. Removed all printfs from pnv-xive2-* qtests.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
tests/qtest/pnv-xive2-flush-sync.c | 6 +-
tests/qtest/pnv-xive2-nvpg_bar.c | 7 +--
tests/qtest/pnv-xive2-test.c | 98 +++++++++++++++++++++++++++---
3 files changed, 94 insertions(+), 17 deletions(-)
diff --git a/tests/qtest/pnv-xive2-flush-sync.c b/tests/qtest/pnv-xive2-flush-sync.c
index 3b32446adb..142826bad0 100644
--- a/tests/qtest/pnv-xive2-flush-sync.c
+++ b/tests/qtest/pnv-xive2-flush-sync.c
@@ -178,14 +178,14 @@ void test_flush_sync_inject(QTestState *qts)
int test_nr;
uint8_t byte;
- printf("# ============================================================\n");
- printf("# Starting cache flush/queue sync injection tests...\n");
+ g_test_message("=========================================================");
+ g_test_message("Starting cache flush/queue sync injection tests...");
for (test_nr = 0; test_nr < sizeof(xive_inject_tests);
test_nr++) {
int op_type = xive_inject_tests[test_nr];
- printf("# Running test %d\n", test_nr);
+ g_test_message("Running test %d", test_nr);
/* start with status byte set to 0 */
clr_sync(qts, src_pir, ic_topo_id, op_type);
diff --git a/tests/qtest/pnv-xive2-nvpg_bar.c b/tests/qtest/pnv-xive2-nvpg_bar.c
index 10d4962d1e..8481a70f22 100644
--- a/tests/qtest/pnv-xive2-nvpg_bar.c
+++ b/tests/qtest/pnv-xive2-nvpg_bar.c
@@ -4,8 +4,7 @@
*
* Copyright (c) 2024, IBM Corporation.
*
- * This work is licensed under the terms of the GNU GPL, version 2 or
- * later. See the COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "libqtest.h"
@@ -78,8 +77,8 @@ void test_nvpg_bar(QTestState *qts)
uint32_t count, delta;
uint8_t i;
- printf("# ============================================================\n");
- printf("# Testing NVPG BAR operations\n");
+ g_test_message("=========================================================");
+ g_test_message("Testing NVPG BAR operations");
set_nvg(qts, group_target, 0);
set_nvp(qts, nvp_target, 0x04);
diff --git a/tests/qtest/pnv-xive2-test.c b/tests/qtest/pnv-xive2-test.c
index a0e9f19313..5313d4ef18 100644
--- a/tests/qtest/pnv-xive2-test.c
+++ b/tests/qtest/pnv-xive2-test.c
@@ -4,6 +4,7 @@
* - Test 'Pull Thread Context to Odd Thread Reporting Line'
* - Test irq to hardware group
* - Test irq to hardware group going through backlog
+ * - Test irq to pool thread
*
* Copyright (c) 2024, IBM Corporation.
*
@@ -220,8 +221,8 @@ static void test_hw_irq(QTestState *qts)
uint16_t reg16;
uint8_t pq, nsr, cppr;
- printf("# ============================================================\n");
- printf("# Testing irq %d to hardware thread %d\n", irq, target_pir);
+ g_test_message("=========================================================");
+ g_test_message("Testing irq %d to hardware thread %d", irq, target_pir);
/* irq config */
set_eas(qts, irq, end_index, irq_data);
@@ -266,6 +267,79 @@ static void test_hw_irq(QTestState *qts)
g_assert_cmphex(cppr, ==, 0xFF);
}
+static void test_pool_irq(QTestState *qts)
+{
+ uint32_t irq = 2;
+ uint32_t irq_data = 0x600d0d06;
+ uint32_t end_index = 5;
+ uint32_t target_pir = 1;
+ uint32_t target_nvp = 0x100 + target_pir;
+ uint8_t priority = 5;
+ uint32_t reg32;
+ uint16_t reg16;
+ uint8_t pq, nsr, cppr, ipb;
+
+ g_test_message("=========================================================");
+ g_test_message("Testing irq %d to pool thread %d", irq, target_pir);
+
+ /* irq config */
+ set_eas(qts, irq, end_index, irq_data);
+ set_end(qts, end_index, target_nvp, priority, false /* group */);
+
+ /* enable and trigger irq */
+ get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00);
+ set_esb(qts, irq, XIVE_TRIGGER_PAGE, 0, 0);
+
+ /* check irq is raised on cpu */
+ pq = get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
+ g_assert_cmpuint(pq, ==, XIVE_ESB_PENDING);
+
+ /* check TIMA values in the PHYS ring (shared by POOL ring) */
+ reg32 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0);
+ nsr = reg32 >> 24;
+ cppr = (reg32 >> 16) & 0xFF;
+ g_assert_cmphex(nsr, ==, 0x40);
+ g_assert_cmphex(cppr, ==, 0xFF);
+
+ /* check TIMA values in the POOL ring */
+ reg32 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD0);
+ nsr = reg32 >> 24;
+ cppr = (reg32 >> 16) & 0xFF;
+ ipb = (reg32 >> 8) & 0xFF;
+ g_assert_cmphex(nsr, ==, 0);
+ g_assert_cmphex(cppr, ==, 0);
+ g_assert_cmphex(ipb, ==, 0x80 >> priority);
+
+ /* ack the irq */
+ reg16 = get_tima16(qts, target_pir, TM_SPC_ACK_HV_REG);
+ nsr = reg16 >> 8;
+ cppr = reg16 & 0xFF;
+ g_assert_cmphex(nsr, ==, 0x40);
+ g_assert_cmphex(cppr, ==, priority);
+
+ /* check irq data is what was configured */
+ reg32 = qtest_readl(qts, xive_get_queue_addr(end_index));
+ g_assert_cmphex((reg32 & 0x7fffffff), ==, (irq_data & 0x7fffffff));
+
+ /* check IPB is cleared in the POOL ring */
+ reg32 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD0);
+ ipb = (reg32 >> 8) & 0xFF;
+ g_assert_cmphex(ipb, ==, 0);
+
+ /* End Of Interrupt */
+ set_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_STORE_EOI, 0);
+ pq = get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
+ g_assert_cmpuint(pq, ==, XIVE_ESB_RESET);
+
+ /* reset CPPR */
+ set_tima8(qts, target_pir, TM_QW3_HV_PHYS + TM_CPPR, 0xFF);
+ reg32 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0);
+ nsr = reg32 >> 24;
+ cppr = (reg32 >> 16) & 0xFF;
+ g_assert_cmphex(nsr, ==, 0x00);
+ g_assert_cmphex(cppr, ==, 0xFF);
+}
+
#define XIVE_ODD_CL 0x80
static void test_pull_thread_ctx_to_odd_thread_cl(QTestState *qts)
{
@@ -278,8 +352,9 @@ static void test_pull_thread_ctx_to_odd_thread_cl(QTestState *qts)
uint32_t cl_word;
uint32_t word2;
- printf("# ============================================================\n");
- printf("# Testing 'Pull Thread Context to Odd Thread Reporting Line'\n");
+ g_test_message("=========================================================");
+ g_test_message("Testing 'Pull Thread Context to Odd Thread Reporting " \
+ "Line'");
/* clear odd cache line prior to pull operation */
memset(cl_pair, 0, sizeof(cl_pair));
@@ -330,8 +405,8 @@ static void test_hw_group_irq(QTestState *qts)
uint16_t reg16;
uint8_t pq, nsr, cppr;
- printf("# ============================================================\n");
- printf("# Testing irq %d to hardware group of size 4\n", irq);
+ g_test_message("=========================================================");
+ g_test_message("Testing irq %d to hardware group of size 4", irq);
/* irq config */
set_eas(qts, irq, end_index, irq_data);
@@ -395,10 +470,10 @@ static void test_hw_group_irq_backlog(QTestState *qts)
uint16_t reg16;
uint8_t pq, nsr, cppr, lsmfb, i;
- printf("# ============================================================\n");
- printf("# Testing irq %d to hardware group of size 4 going through " \
- "backlog\n",
- irq);
+ g_test_message("=========================================================");
+ g_test_message("Testing irq %d to hardware group of size 4 going " \
+ "through backlog",
+ irq);
/*
* set current priority of all threads in the group to something
@@ -484,6 +559,9 @@ static void test_xive(void)
/* omit reset_state here and use settings from test_hw_irq */
test_pull_thread_ctx_to_odd_thread_cl(qts);
+ reset_state(qts);
+ test_pool_irq(qts);
+
reset_state(qts);
test_hw_group_irq(qts);
--
2.43.0On Tue Dec 10, 2024 at 10:05 AM AEST, Michael Kowal wrote:
> From: Glenn Miles <milesg@linux.ibm.com>
>
> Added new test for pool interrupts. Removed all printfs from pnv-xive2-* qtests.
>
> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
> Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
This looks good. I split the remove-printfs into its own patch.
I would like to see the irq test code merged into one that can
just select CAM rings by argument because it's mostly duplicated.
Should then be able to add an OS ring test with the same code too.
But okay for now.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> tests/qtest/pnv-xive2-flush-sync.c | 6 +-
> tests/qtest/pnv-xive2-nvpg_bar.c | 7 +--
> tests/qtest/pnv-xive2-test.c | 98 +++++++++++++++++++++++++++---
> 3 files changed, 94 insertions(+), 17 deletions(-)
>
> diff --git a/tests/qtest/pnv-xive2-flush-sync.c b/tests/qtest/pnv-xive2-flush-sync.c
> index 3b32446adb..142826bad0 100644
> --- a/tests/qtest/pnv-xive2-flush-sync.c
> +++ b/tests/qtest/pnv-xive2-flush-sync.c
> @@ -178,14 +178,14 @@ void test_flush_sync_inject(QTestState *qts)
> int test_nr;
> uint8_t byte;
>
> - printf("# ============================================================\n");
> - printf("# Starting cache flush/queue sync injection tests...\n");
> + g_test_message("=========================================================");
> + g_test_message("Starting cache flush/queue sync injection tests...");
>
> for (test_nr = 0; test_nr < sizeof(xive_inject_tests);
> test_nr++) {
> int op_type = xive_inject_tests[test_nr];
>
> - printf("# Running test %d\n", test_nr);
> + g_test_message("Running test %d", test_nr);
>
> /* start with status byte set to 0 */
> clr_sync(qts, src_pir, ic_topo_id, op_type);
> diff --git a/tests/qtest/pnv-xive2-nvpg_bar.c b/tests/qtest/pnv-xive2-nvpg_bar.c
> index 10d4962d1e..8481a70f22 100644
> --- a/tests/qtest/pnv-xive2-nvpg_bar.c
> +++ b/tests/qtest/pnv-xive2-nvpg_bar.c
> @@ -4,8 +4,7 @@
> *
> * Copyright (c) 2024, IBM Corporation.
> *
> - * This work is licensed under the terms of the GNU GPL, version 2 or
> - * later. See the COPYING file in the top-level directory.
> + * SPDX-License-Identifier: GPL-2.0-or-later
> */
> #include "qemu/osdep.h"
> #include "libqtest.h"
> @@ -78,8 +77,8 @@ void test_nvpg_bar(QTestState *qts)
> uint32_t count, delta;
> uint8_t i;
>
> - printf("# ============================================================\n");
> - printf("# Testing NVPG BAR operations\n");
> + g_test_message("=========================================================");
> + g_test_message("Testing NVPG BAR operations");
>
> set_nvg(qts, group_target, 0);
> set_nvp(qts, nvp_target, 0x04);
> diff --git a/tests/qtest/pnv-xive2-test.c b/tests/qtest/pnv-xive2-test.c
> index a0e9f19313..5313d4ef18 100644
> --- a/tests/qtest/pnv-xive2-test.c
> +++ b/tests/qtest/pnv-xive2-test.c
> @@ -4,6 +4,7 @@
> * - Test 'Pull Thread Context to Odd Thread Reporting Line'
> * - Test irq to hardware group
> * - Test irq to hardware group going through backlog
> + * - Test irq to pool thread
> *
> * Copyright (c) 2024, IBM Corporation.
> *
> @@ -220,8 +221,8 @@ static void test_hw_irq(QTestState *qts)
> uint16_t reg16;
> uint8_t pq, nsr, cppr;
>
> - printf("# ============================================================\n");
> - printf("# Testing irq %d to hardware thread %d\n", irq, target_pir);
> + g_test_message("=========================================================");
> + g_test_message("Testing irq %d to hardware thread %d", irq, target_pir);
>
> /* irq config */
> set_eas(qts, irq, end_index, irq_data);
> @@ -266,6 +267,79 @@ static void test_hw_irq(QTestState *qts)
> g_assert_cmphex(cppr, ==, 0xFF);
> }
>
> +static void test_pool_irq(QTestState *qts)
> +{
> + uint32_t irq = 2;
> + uint32_t irq_data = 0x600d0d06;
> + uint32_t end_index = 5;
> + uint32_t target_pir = 1;
> + uint32_t target_nvp = 0x100 + target_pir;
> + uint8_t priority = 5;
> + uint32_t reg32;
> + uint16_t reg16;
> + uint8_t pq, nsr, cppr, ipb;
> +
> + g_test_message("=========================================================");
> + g_test_message("Testing irq %d to pool thread %d", irq, target_pir);
> +
> + /* irq config */
> + set_eas(qts, irq, end_index, irq_data);
> + set_end(qts, end_index, target_nvp, priority, false /* group */);
> +
> + /* enable and trigger irq */
> + get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00);
> + set_esb(qts, irq, XIVE_TRIGGER_PAGE, 0, 0);
> +
> + /* check irq is raised on cpu */
> + pq = get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
> + g_assert_cmpuint(pq, ==, XIVE_ESB_PENDING);
> +
> + /* check TIMA values in the PHYS ring (shared by POOL ring) */
> + reg32 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0);
> + nsr = reg32 >> 24;
> + cppr = (reg32 >> 16) & 0xFF;
> + g_assert_cmphex(nsr, ==, 0x40);
> + g_assert_cmphex(cppr, ==, 0xFF);
> +
> + /* check TIMA values in the POOL ring */
> + reg32 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD0);
> + nsr = reg32 >> 24;
> + cppr = (reg32 >> 16) & 0xFF;
> + ipb = (reg32 >> 8) & 0xFF;
> + g_assert_cmphex(nsr, ==, 0);
> + g_assert_cmphex(cppr, ==, 0);
> + g_assert_cmphex(ipb, ==, 0x80 >> priority);
> +
> + /* ack the irq */
> + reg16 = get_tima16(qts, target_pir, TM_SPC_ACK_HV_REG);
> + nsr = reg16 >> 8;
> + cppr = reg16 & 0xFF;
> + g_assert_cmphex(nsr, ==, 0x40);
> + g_assert_cmphex(cppr, ==, priority);
> +
> + /* check irq data is what was configured */
> + reg32 = qtest_readl(qts, xive_get_queue_addr(end_index));
> + g_assert_cmphex((reg32 & 0x7fffffff), ==, (irq_data & 0x7fffffff));
> +
> + /* check IPB is cleared in the POOL ring */
> + reg32 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD0);
> + ipb = (reg32 >> 8) & 0xFF;
> + g_assert_cmphex(ipb, ==, 0);
> +
> + /* End Of Interrupt */
> + set_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_STORE_EOI, 0);
> + pq = get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
> + g_assert_cmpuint(pq, ==, XIVE_ESB_RESET);
> +
> + /* reset CPPR */
> + set_tima8(qts, target_pir, TM_QW3_HV_PHYS + TM_CPPR, 0xFF);
> + reg32 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0);
> + nsr = reg32 >> 24;
> + cppr = (reg32 >> 16) & 0xFF;
> + g_assert_cmphex(nsr, ==, 0x00);
> + g_assert_cmphex(cppr, ==, 0xFF);
> +}
> +
> #define XIVE_ODD_CL 0x80
> static void test_pull_thread_ctx_to_odd_thread_cl(QTestState *qts)
> {
> @@ -278,8 +352,9 @@ static void test_pull_thread_ctx_to_odd_thread_cl(QTestState *qts)
> uint32_t cl_word;
> uint32_t word2;
>
> - printf("# ============================================================\n");
> - printf("# Testing 'Pull Thread Context to Odd Thread Reporting Line'\n");
> + g_test_message("=========================================================");
> + g_test_message("Testing 'Pull Thread Context to Odd Thread Reporting " \
> + "Line'");
>
> /* clear odd cache line prior to pull operation */
> memset(cl_pair, 0, sizeof(cl_pair));
> @@ -330,8 +405,8 @@ static void test_hw_group_irq(QTestState *qts)
> uint16_t reg16;
> uint8_t pq, nsr, cppr;
>
> - printf("# ============================================================\n");
> - printf("# Testing irq %d to hardware group of size 4\n", irq);
> + g_test_message("=========================================================");
> + g_test_message("Testing irq %d to hardware group of size 4", irq);
>
> /* irq config */
> set_eas(qts, irq, end_index, irq_data);
> @@ -395,10 +470,10 @@ static void test_hw_group_irq_backlog(QTestState *qts)
> uint16_t reg16;
> uint8_t pq, nsr, cppr, lsmfb, i;
>
> - printf("# ============================================================\n");
> - printf("# Testing irq %d to hardware group of size 4 going through " \
> - "backlog\n",
> - irq);
> + g_test_message("=========================================================");
> + g_test_message("Testing irq %d to hardware group of size 4 going " \
> + "through backlog",
> + irq);
>
> /*
> * set current priority of all threads in the group to something
> @@ -484,6 +559,9 @@ static void test_xive(void)
> /* omit reset_state here and use settings from test_hw_irq */
> test_pull_thread_ctx_to_odd_thread_cl(qts);
>
> + reset_state(qts);
> + test_pool_irq(qts);
> +
> reset_state(qts);
> test_hw_group_irq(qts);
>
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