On Thu, Dec 5, 2024 at 11:33 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> This is a re-submission of the original Hardware Performance Monitor
> IOMMU support sent by Tomasz back in July 2023 [1] in the first version
> of the IOMMU emulation. In the second version of that work [2] sent in
> February 2024 I said:
>
> ----
> - I'm not contributing the HPM support that was present in v1. It shaved
> off 600 lines of code from the series, which is already large enough
> as is. We'll introduce HPM in later versions or as a follow-up;
> -----
>
> So here I am keeping my end of the deal. The code is basically the same that
> Tomasz sent in v1 with some tweaks:
>
> - Code was split across several patches for easier review;
> - A separated file was created, riscv-iommu-hpm.c, to host all the HPM
> related code. The base emulation will use HPM via public helpers. The
> idea is to avoid clogging riscv-iommu.c;
> - There was a lock in use to read/write the HPM registers in the
> original posting. Based on the current design of the merged IOMMU
> support, a lock-less design, I also removed the locks from HPM;
> - Other minor tweaks such as not naming functions using "__name" and so
> on.
>
> Patch 1 is a header fix required to put the helpers in riscv-iommu-hpm.
> Patches 10 and 11 are new. The original HPM code is split in patches
> 2-9.
>
> Series based on alistair/riscv-to-apply.next.
Looks fine, I didn't check it that closely but any bugs will affect you :P
Do you mind rebasing though?
Alistair
>
> [1] https://lore.kernel.org/qemu-riscv/cover.1689819031.git.tjeznach@rivosinc.com/
> [2] https://lore.kernel.org/qemu-riscv/20240307160319.675044-1-dbarboza@ventanamicro.com/
>
> Cc: Tomasz Jeznach <tjeznach@rivosinc.com>
>
> Daniel Henrique Barboza (3):
> hw/riscv/riscv-iommu.h: add missing headers
> hw/riscv: add IOMMU HPM trace events
> docs/specs/riscv-iommu.rst: add HPM support info
>
> Tomasz Jeznach (8):
> hw/riscv/riscv-iommu-bits.h: HPM bits
> hw/riscv/riscv-iommu: add riscv-iommu-hpm file
> hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr()
> hw/riscv/riscv-iommu: instantiate hpm_timer
> hw/riscv/riscv-iommu: add IOCOUNTINH mmio writes
> hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write
> hw/riscv/riscv-iommu: add hpm events mmio write
> hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap
>
> docs/specs/riscv-iommu.rst | 2 +
> hw/riscv/meson.build | 3 +-
> hw/riscv/riscv-iommu-bits.h | 47 +++++
> hw/riscv/riscv-iommu-hpm.c | 381 ++++++++++++++++++++++++++++++++++++
> hw/riscv/riscv-iommu-hpm.h | 33 ++++
> hw/riscv/riscv-iommu.c | 131 +++++++++++--
> hw/riscv/riscv-iommu.h | 27 +++
> hw/riscv/trace-events | 5 +
> 8 files changed, 612 insertions(+), 17 deletions(-)
> create mode 100644 hw/riscv/riscv-iommu-hpm.c
> create mode 100644 hw/riscv/riscv-iommu-hpm.h
>
> --
> 2.47.1
>
>