On Tue, 3 Dec 2024 21:35:46 +0800
Tomita Moeko <tomitamoeko@gmail.com> wrote:
> The GGC register at 0x50 of pci config space is a mirror of the same
> register at 0x108040 of mmio bar0 [1]. i915 driver also reads that
> register from mmio bar0 instead of config space. As GGC is programmed
> and emulated by qemu, the mmio address should also be emulated, in the
> same way of BDSM register.
>
> [1] 4.1.28, 12th Generation Intel Core Processors Datasheet Volume 2
> https://www.intel.com/content/www/us/en/content-details/655259
>
> Signed-off-by: Tomita Moeko <tomitamoeko@gmail.com>
> ---
> hw/vfio/igd.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c
> index 522845c509..bc18fc8cc0 100644
> --- a/hw/vfio/igd.c
> +++ b/hw/vfio/igd.c
> @@ -483,8 +483,10 @@ static const MemoryRegionOps vfio_igd_quirk_mirror_##name = { \
> .endianness = DEVICE_LITTLE_ENDIAN, \
> };
>
> +VFIO_IGD_QUIRK_MIRROR_REG(IGD_GMCH, ggc)
> VFIO_IGD_QUIRK_MIRROR_REG(IGD_BDSM_GEN11, bdsm)
>
> +#define IGD_GGC_MMIO_OFFSET 0x108040
> #define IGD_BDSM_MMIO_OFFSET 0x1080C0
>
> void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr)
> @@ -513,9 +515,16 @@ void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr)
> return;
> }
>
> - quirk = vfio_quirk_alloc(1);
> + quirk = vfio_quirk_alloc(2);
> quirk->data = vdev;
>
> + memory_region_init_io(&quirk->mem[0], OBJECT(vdev),
> + &vfio_igd_quirk_mirror_ggc, vdev,
> + "vfio-igd-ggc-quirk", 2);
> + memory_region_add_subregion_overlap(vdev->bars[0].region.mem,
> + IGD_GGC_MMIO_OFFSET, &quirk->mem[0],
> + 1);
> +
> memory_region_init_io(&quirk->mem[1], OBJECT(vdev),
> &vfio_igd_quirk_mirror_bdsm, vdev,
> "vfio-igd-bdsm-quirk", 8);
Seems like trying to keep these ordered by offset is what introduced
the bug in the previous patch. Let's not care about that, use the next
index and setup in index order. Thanks,
Alex