[PULL 0/9] target-arm queue
[Qemu-devel] [PULL v2 00/25] target-arm queue
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This one's almost all docs fixes.
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Dropped the tmp421 patch and the following patch that
2
depended on it; no other changes.
2
3
3
thanks
4
thanks
4
-- PMM
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-- PMM
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The following changes since commit ba54a7e6b86884e43bed2d2f5a79c719059652a8:
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The following changes since commit 43771d5d92312504305c19abe29ec5bfabd55f01:
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8
8
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-11-26 14:06:40 +0000)
9
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-05-31' into staging (2017-06-01 16:39:16 +0100)
9
10
10
are available in the Git repository at:
11
are available in the git repository at:
11
12
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241126
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170602
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14
14
for you to fetch changes up to d8790ead55a2ef1e65332ebec63ae3c5db598942:
15
for you to fetch changes up to c7637c04be257968e6df30de961a6a23a0ac3dd8:
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16
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docs/system/arm/aspeed: add missing model supermicrox11spi-bmc (2024-11-26 16:22:38 +0000)
17
hw/arm/virt: fdt: generate distance-map when needed (2017-06-02 11:51:49 +0100)
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18
18
----------------------------------------------------------------
19
----------------------------------------------------------------
19
target-arm queue:
20
target-arm queue:
20
* target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
21
* virt: numa: provide ACPI distance info when needed
21
* docs/system/arm: Fix broken links and missing feature names
22
* aspeed: fix i2c controller bugs
23
* M profile: support MPU
24
* gicv3: fix mishandling of BPR1, VBPR1
25
* load_uboot_image: don't assume a full header read
26
* libvixl: Correct build failures on NetBSD
22
27
23
----------------------------------------------------------------
28
----------------------------------------------------------------
24
Michael Tokarev (1):
29
Andrew Jones (3):
25
target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
30
load_uboot_image: don't assume a full header read
31
hw/arm/virt-acpi-build: build SLIT when needed
32
hw/arm/virt: fdt: generate distance-map when needed
26
33
27
Pierrick Bouvier (8):
34
Cédric Le Goater (4):
28
docs/system/arm/emulation: mention armv9
35
aspeed/i2c: improve command handling
29
docs/system/arm/emulation: fix typo in feature name
36
aspeed/i2c: handle LAST command under the RX command
30
docs/system/arm/emulation: add FEAT_SSBS2
37
aspeed/i2c: introduce a state machine
31
target/arm/tcg/: fix typo in FEAT name
38
aspeed: add some I2C devices to the Aspeed machines
32
docs/system/arm/: add FEAT_MTE_ASYNC
33
docs/system/arm/: add FEAT_DoubleLock
34
docs/system/arm/fby35: update link to product page
35
docs/system/arm/aspeed: add missing model supermicrox11spi-bmc
36
39
37
docs/system/arm/aspeed.rst | 7 ++++---
40
Kamil Rytarowski (1):
38
docs/system/arm/emulation.rst | 11 +++++++----
41
libvixl: Correct build failures on NetBSD
39
docs/system/arm/fby35.rst | 2 +-
42
40
target/arm/tcg/cpu32.c | 6 +++---
43
Michael Davidsaver (4):
41
4 files changed, 15 insertions(+), 11 deletions(-)
44
armv7m: Improve "-d mmu" tracing for PMSAv7 MPU
45
armv7m: Implement M profile default memory map
46
armv7m: Classify faults as MemManage or BusFault
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arm: add MPU support to M profile CPUs
48
49
Peter Maydell (12):
50
hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1
51
hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum
52
hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1
53
arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access()
54
arm: Add support for M profile CPUs having different MMU index semantics
55
arm: Use different ARMMMUIdx values for M profile
56
arm: Clean up handling of no-MPU PMSA CPUs
57
arm: Don't clear ARM_FEATURE_PMSA for no-mpu configs
58
arm: Don't let no-MPU PMSA cores write to SCTLR.M
59
arm: Remove unnecessary check on cpu->pmsav7_dregion
60
arm: All M profile cores are PMSA
61
arm: Implement HFNMIENA support for M profile MPU
62
63
Wei Huang (1):
64
target/arm: clear PMUVER field of AA64DFR0 when vPMU=off
65
66
disas/libvixl/Makefile.objs | 3 +
67
target/arm/cpu.h | 118 ++++++++++++++--
68
target/arm/translate.h | 2 +-
69
hw/arm/aspeed.c | 27 ++++
70
hw/arm/virt-acpi-build.c | 4 +
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hw/arm/virt.c | 21 +++
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hw/core/loader.c | 3 +-
73
hw/i2c/aspeed_i2c.c | 65 +++++++--
74
hw/intc/arm_gicv3_cpuif.c | 50 ++++++-
75
hw/intc/armv7m_nvic.c | 104 ++++++++++++++
76
target/arm/cpu.c | 28 +++-
77
target/arm/helper.c | 338 ++++++++++++++++++++++++++++++--------------
78
target/arm/machine.c | 7 +-
79
target/arm/op_helper.c | 3 +-
80
target/arm/translate-a64.c | 18 ++-
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target/arm/translate.c | 14 +-
82
16 files changed, 648 insertions(+), 157 deletions(-)
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diff view generated by jsdifflib
[PULL 1/9] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
Deleted patch
1
From: Michael Tokarev <mjt@tls.msk.ru>
2
1
3
According to Cortex-R5 r1p2 manual, register with opcode2=0 is
4
BTCM and with opcode2=1 is ATCM, - exactly the opposite from how
5
qemu labels them. Just swap the labels to avoid confusion, -
6
both registers are implemented as always-zero.
7
8
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20241121171602.3273252-1-mjt@tls.msk.ru
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/tcg/cpu32.c | 4 ++--
14
1 file changed, 2 insertions(+), 2 deletions(-)
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16
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/tcg/cpu32.c
19
+++ b/target/arm/tcg/cpu32.c
20
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
21
22
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
23
/* Dummy the TCM region regs for the moment */
24
- { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
25
+ { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
26
.access = PL1_RW, .type = ARM_CP_CONST },
27
- { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
28
+ { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
29
.access = PL1_RW, .type = ARM_CP_CONST },
30
{ .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
31
.opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
32
--
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2.34.1
diff view generated by jsdifflib
[PULL 2/9] docs/system/arm/emulation: mention armv9
Deleted patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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1
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20241122225049.1617774-2-pierrick.bouvier@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
8
docs/system/arm/emulation.rst | 6 +++---
9
1 file changed, 3 insertions(+), 3 deletions(-)
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diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
12
index XXXXXXX..XXXXXXX 100644
13
--- a/docs/system/arm/emulation.rst
14
+++ b/docs/system/arm/emulation.rst
15
@@ -XXX,XX +XXX,XX @@
16
A-profile CPU architecture support
17
==================================
18
19
-QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and
20
-Armv8 versions of the A-profile architecture. It also has support for
21
+QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7,
22
+Armv8 and Armv9 versions of the A-profile architecture. It also has support for
23
the following architecture extensions:
24
25
- FEAT_AA32BF16 (AArch32 BFloat16 instructions)
26
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
27
- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
28
29
For information on the specifics of these extensions, please refer
30
-to the `Armv8-A Arm Architecture Reference Manual
31
+to the `Arm Architecture Reference Manual for A-profile architecture
32
<https://developer.arm.com/documentation/ddi0487/latest>`_.
33
34
When a specific named CPU is being emulated, only those features which
35
--
36
2.34.1
diff view generated by jsdifflib
[PULL 3/9] docs/system/arm/emulation: fix typo in feature name
Deleted patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
1
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20241122225049.1617774-3-pierrick.bouvier@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
docs/system/arm/emulation.rst | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
12
index XXXXXXX..XXXXXXX 100644
13
--- a/docs/system/arm/emulation.rst
14
+++ b/docs/system/arm/emulation.rst
15
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
16
- FEAT_LSE2 (Large System Extensions v2)
17
- FEAT_LVA (Large Virtual Address space)
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- FEAT_MixedEnd (Mixed-endian support)
19
-- FEAT_MixdEndEL0 (Mixed-endian support at EL0)
20
+- FEAT_MixedEndEL0 (Mixed-endian support at EL0)
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- FEAT_MOPS (Standardization of memory operations)
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- FEAT_MTE (Memory Tagging Extension)
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- FEAT_MTE2 (Memory Tagging Extension)
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--
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2.34.1
diff view generated by jsdifflib
[PULL 4/9] docs/system/arm/emulation: add FEAT_SSBS2
Deleted patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
1
3
We implemented this at the same times as FEAT_SSBS, but forgot
4
to list it in the documentation.
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Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20241122225049.1617774-4-pierrick.bouvier@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
[PMM: improve commit message]
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
docs/system/arm/emulation.rst | 1 +
14
1 file changed, 1 insertion(+)
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diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
17
index XXXXXXX..XXXXXXX 100644
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--- a/docs/system/arm/emulation.rst
19
+++ b/docs/system/arm/emulation.rst
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@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
21
- FEAT_SVE2 (Scalable Vector Extension version 2)
22
- FEAT_SPECRES (Speculation restriction instructions)
23
- FEAT_SSBS (Speculative Store Bypass Safe)
24
+- FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2)
25
- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1)
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- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1)
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- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1)
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--
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2.34.1
diff view generated by jsdifflib
[PULL 5/9] target/arm/tcg/: fix typo in FEAT name
Deleted patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
1
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241122225049.1617774-5-pierrick.bouvier@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/tcg/cpu32.c | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
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12
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/tcg/cpu32.c
15
+++ b/target/arm/tcg/cpu32.c
16
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
17
cpu->isar.id_mmfr5 = t;
18
19
t = cpu->isar.id_pfr0;
20
- t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
21
+ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
22
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
23
t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
24
cpu->isar.id_pfr0 = t;
25
--
26
2.34.1
27
28
diff view generated by jsdifflib
[PULL 6/9] docs/system/arm/: add FEAT_MTE_ASYNC
Deleted patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
1
3
We already implement FEAT_MTE_ASYNC; we just forgot to list it
4
in the documentation.
5
6
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241122225049.1617774-6-pierrick.bouvier@linaro.org
9
[PMM: expand commit message]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
docs/system/arm/emulation.rst | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
16
index XXXXXXX..XXXXXXX 100644
17
--- a/docs/system/arm/emulation.rst
18
+++ b/docs/system/arm/emulation.rst
19
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
20
- FEAT_MTE2 (Memory Tagging Extension)
21
- FEAT_MTE3 (MTE Asymmetric Fault Handling)
22
- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults)
23
+- FEAT_MTE_ASYNC (Asynchronous reporting of Tag Check Fault)
24
- FEAT_NMI (Non-maskable Interrupt)
25
- FEAT_NV (Nested Virtualization)
26
- FEAT_NV2 (Enhanced nested virtualization support)
27
--
28
2.34.1
diff view generated by jsdifflib
[PULL 7/9] docs/system/arm/: add FEAT_DoubleLock
Deleted patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
1
3
We already implement FEAT_DoubleLock (see commit f94a6df5dd6a7) when
4
the ID registers call for it. This feature is actually one that must
5
*not* be implemented in v9.0, but since our documentation lists
6
everything we can emulate, we should include FEAT_DoubleLock in the
7
list.
8
9
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
10
Message-id: 20241122225049.1617774-7-pierrick.bouvier@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
[PMM: expand commit message]
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
docs/system/arm/emulation.rst | 1 +
16
1 file changed, 1 insertion(+)
17
18
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
19
index XXXXXXX..XXXXXXX 100644
20
--- a/docs/system/arm/emulation.rst
21
+++ b/docs/system/arm/emulation.rst
22
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
23
- FEAT_CSV3 (Cache speculation variant 3)
24
- FEAT_DGH (Data gathering hint)
25
- FEAT_DIT (Data Independent Timing instructions)
26
+- FEAT_DoubleLock (Double Lock)
27
- FEAT_DPB (DC CVAP instruction)
28
- FEAT_DPB2 (DC CVADP instruction)
29
- FEAT_Debugv8p1 (Debug with VHE)
30
--
31
2.34.1
diff view generated by jsdifflib
[PULL 8/9] docs/system/arm/fby35: update link to product page
Deleted patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
1
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20241122225049.1617774-8-pierrick.bouvier@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
docs/system/arm/fby35.rst | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
12
13
diff --git a/docs/system/arm/fby35.rst b/docs/system/arm/fby35.rst
14
index XXXXXXX..XXXXXXX 100644
15
--- a/docs/system/arm/fby35.rst
16
+++ b/docs/system/arm/fby35.rst
17
@@ -XXX,XX +XXX,XX @@ include various compute accelerators (video, inferencing, etc). At the moment,
18
only the first server slot's BIC is included.
19
20
Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds
21
-can be fit into a chassis. See `here <https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server>`__
22
+can be fit into a chassis. See `here <https://www.opencompute.org/products-chiplets/237/wiwynn-yosemite-v3-server>`__
23
for an example.
24
25
In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC
26
--
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2.34.1
28
29
diff view generated by jsdifflib
[PULL 9/9] docs/system/arm/aspeed: add missing model supermicrox11spi-bmc
Deleted patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
1
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
5
Message-id: 20241122225049.1617774-13-pierrick.bouvier@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
docs/system/arm/aspeed.rst | 7 ++++---
9
1 file changed, 4 insertions(+), 3 deletions(-)
10
11
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
12
index XXXXXXX..XXXXXXX 100644
13
--- a/docs/system/arm/aspeed.rst
14
+++ b/docs/system/arm/aspeed.rst
15
@@ -XXX,XX +XXX,XX @@
16
-Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
17
-========================================================================================================================================================================================================================================================================================================================================================================================================
18
+Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
19
+==================================================================================================================================================================================================================================================================================================================================================================================================================================
20
21
The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
22
Aspeed evaluation boards. They are based on different releases of the
23
@@ -XXX,XX +XXX,XX @@ AST2400 SoC based machines :
24
25
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
26
- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
27
-- ``supermicrox11-bmc`` Supermicro X11 BMC
28
+- ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
29
+- ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
30
31
AST2500 SoC based machines :
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33
--
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2.34.1
diff view generated by jsdifflib

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