On 11/14/24 08:01, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/cpu.h | 8 +++++---
> target/riscv/cpu_helper.c | 22 +++++++++++++++++-----
> target/riscv/tcg/tcg-cpu.c | 2 +-
> 3 files changed, 23 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 284b112821..f97c4f3410 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -25,6 +25,7 @@
> #include "hw/qdev-properties.h"
> #include "exec/cpu-defs.h"
> #include "exec/gdbstub.h"
> +#include "exec/memop.h"
> #include "qemu/cpu-float.h"
> #include "qom/object.h"
> #include "qemu/int128.h"
> @@ -563,9 +564,10 @@ bool cpu_get_bcfien(CPURISCVState *env);
> G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> MMUAccessType access_type,
> int mmu_idx, uintptr_t retaddr);
> -bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> - MMUAccessType access_type, int mmu_idx,
> - bool probe, uintptr_t retaddr);
> +bool riscv_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out,
> + vaddr addr, MMUAccessType access_type,
> + int mmu_idx, MemOp memop, int size,
> + bool probe, uintptr_t ra);
> char *riscv_isa_string(RISCVCPU *cpu);
> int riscv_cpu_max_xlen(RISCVCPUClass *mcc);
> bool riscv_cpu_option_set(const char *optname);
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 0a3ead69ea..edb2edfc55 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1429,9 +1429,10 @@ static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)
> riscv_pmu_incr_ctr(cpu, pmu_event_type);
> }
>
> -bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> - MMUAccessType access_type, int mmu_idx,
> - bool probe, uintptr_t retaddr)
> +bool riscv_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out,
> + vaddr address, MMUAccessType access_type,
> + int mmu_idx, MemOp memop, int size,
> + bool probe, uintptr_t retaddr)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> @@ -1452,6 +1453,14 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
> __func__, address, access_type, mmu_idx);
>
> + if (address & ((1 << memop_alignment_bits(memop)) - 1)) {
> + if (probe) {
> + return false;
> + }
> + riscv_cpu_do_unaligned_access(cs, address, access_type,
> + mmu_idx, retaddr);
> + }
> +
> pmu_tlb_fill_incr_ctr(cpu, access_type);
> if (two_stage_lookup) {
> /* Two stage lookup */
> @@ -1544,8 +1553,11 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> }
>
> if (ret == TRANSLATE_SUCCESS) {
> - tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
> - prot, mmu_idx, tlb_size);
> + memset(out, 0, sizeof(*out));
> + out->phys_addr = pa;
> + out->prot = prot;
> + out->lg_page_size = ctz64(tlb_size);
> + out->attrs = MEMTXATTRS_UNSPECIFIED;
> return true;
> } else if (probe) {
> return false;
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index c62c221696..f3b436bb86 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -138,7 +138,7 @@ static const TCGCPUOps riscv_tcg_ops = {
> .restore_state_to_opc = riscv_restore_state_to_opc,
>
> #ifndef CONFIG_USER_ONLY
> - .tlb_fill = riscv_cpu_tlb_fill,
> + .tlb_fill_align = riscv_cpu_tlb_fill_align,
> .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
> .cpu_exec_halt = riscv_cpu_has_work,
> .do_interrupt = riscv_cpu_do_interrupt,
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>