[PATCH for-10.0 0/9] target/riscv: add 'sha' support

Daniel Henrique Barboza posted 9 patches 1 year, 2 months ago
Failed in applying to current master (apply log)
There is a newer version of this series
target/riscv/cpu.c         | 10 ++++++++++
target/riscv/cpu_cfg.h     |  2 ++
target/riscv/tcg/tcg-cpu.c | 30 ++++++++++++++++++++++++++----
3 files changed, 38 insertions(+), 4 deletions(-)
[PATCH for-10.0 0/9] target/riscv: add 'sha' support
Posted by Daniel Henrique Barboza 1 year, 2 months ago
Hi,

'sha' is defined in RVA22 as "augmented hypervisor extension" and
consists of a set of named features that must be enabled.

RVA23 makes 'sha' mandatory, so let's add official support for it in
preparation to support RVA23 later. 

Most of the named features added here are always implemented by TCG.
Only 'ssstateen' has a runtime dependency. 


Daniel Henrique Barboza (9):
  target/riscv/tcg: hide warn for named feats when disabling via
    priv_ver
  target/riscv: add ssstateen
  target/riscv: add shcounterenw
  target/riscv: add shvstvala
  target/riscv: add shtvala
  target/riscv: add shvstvecd
  target/riscv: add shvsatpa
  target/riscv: add shgatpa
  target/riscv/tcg: add sha

 target/riscv/cpu.c         | 10 ++++++++++
 target/riscv/cpu_cfg.h     |  2 ++
 target/riscv/tcg/tcg-cpu.c | 30 ++++++++++++++++++++++++++----
 3 files changed, 38 insertions(+), 4 deletions(-)

-- 
2.47.0
Re: [PATCH for-10.0 0/9] target/riscv: add 'sha' support
Posted by Alistair Francis 1 year, 2 months ago
On Thu, Nov 14, 2024 at 2:19 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> 'sha' is defined in RVA22 as "augmented hypervisor extension" and
> consists of a set of named features that must be enabled.
>
> RVA23 makes 'sha' mandatory, so let's add official support for it in
> preparation to support RVA23 later.
>
> Most of the named features added here are always implemented by TCG.
> Only 'ssstateen' has a runtime dependency.
>
>
> Daniel Henrique Barboza (9):
>   target/riscv/tcg: hide warn for named feats when disabling via
>     priv_ver
>   target/riscv: add ssstateen
>   target/riscv: add shcounterenw
>   target/riscv: add shvstvala
>   target/riscv: add shtvala
>   target/riscv: add shvstvecd
>   target/riscv: add shvsatpa
>   target/riscv: add shgatpa
>   target/riscv/tcg: add sha

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c         | 10 ++++++++++
>  target/riscv/cpu_cfg.h     |  2 ++
>  target/riscv/tcg/tcg-cpu.c | 30 ++++++++++++++++++++++++++----
>  3 files changed, 38 insertions(+), 4 deletions(-)
>
> --
> 2.47.0
>
>