On Tue, Nov 12, 2024 at 07:10:35PM +0100, Philippe Mathieu-Daudé wrote:
> Rather than accessing the registers within the mixed RAM/MMIO
> region as indexed register, declare a per-port RX_CTRL. This
> will help to map the RAM as RAM (keeping MMIO as MMIO) in few
> commits.
>
> Previous s->regs[R_RX_CTRL0] and s->regs[R_RX_CTRL1] are now
> unused. Not a concern, this array will soon disappear.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/net/xilinx_ethlite.c | 31 +++++++++++++++++++++----------
> 1 file changed, 21 insertions(+), 10 deletions(-)
>
> diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
> index fdbf25fd91..605451a522 100644
> --- a/hw/net/xilinx_ethlite.c
> +++ b/hw/net/xilinx_ethlite.c
> @@ -59,6 +59,13 @@
> #define CTRL_P 0x2
> #define CTRL_S 0x1
>
> +typedef struct XlnxXpsEthLitePort
> +{
> + struct {
> + uint32_t rx_ctrl;
> + } reg;
> +} XlnxXpsEthLitePort;
> +
> #define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite"
> OBJECT_DECLARE_SIMPLE_TYPE(XlnxXpsEthLite, XILINX_ETHLITE)
>
> @@ -76,6 +83,7 @@ struct XlnxXpsEthLite
> unsigned int port_index;
>
> UnimplementedDeviceState mdio;
> + XlnxXpsEthLitePort port[2];
> uint32_t regs[R_MAX];
> };
>
> @@ -110,6 +118,7 @@ static uint64_t
> eth_read(void *opaque, hwaddr addr, unsigned int size)
> {
> XlnxXpsEthLite *s = opaque;
> + unsigned port_index = addr_to_port_index(addr);
> uint32_t r = 0;
>
> addr >>= 2;
> @@ -121,11 +130,13 @@ eth_read(void *opaque, hwaddr addr, unsigned int size)
> case R_TX_LEN1:
> case R_TX_CTRL1:
> case R_TX_CTRL0:
> - case R_RX_CTRL1:
> - case R_RX_CTRL0:
> r = s->regs[addr];
> break;
>
> + case R_RX_CTRL1:
> + case R_RX_CTRL0:
> + r = s->port[port_index].reg.rx_ctrl;
> +
> default:
> r = tswap32(s->regs[addr]);
> break;
> @@ -173,7 +184,9 @@ eth_write(void *opaque, hwaddr addr,
> if (!(value & CTRL_S)) {
> qemu_flush_queued_packets(qemu_get_queue(s->nic));
> }
> - /* fall through */
> + s->port[port_index].reg.rx_ctrl = value;
> + break;
> +
> case R_TX_LEN0:
> case R_TX_LEN1:
> case R_TX_GIE0:
> @@ -203,23 +216,21 @@ static const MemoryRegionOps eth_ops = {
> static bool eth_can_rx(NetClientState *nc)
> {
> XlnxXpsEthLite *s = qemu_get_nic_opaque(nc);
> - unsigned int rxbase = s->port_index * (0x800 / 4);
>
> - return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S);
> + return !(s->port[s->port_index].reg.rx_ctrl & CTRL_S);
> }
>
> static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
> {
> XlnxXpsEthLite *s = qemu_get_nic_opaque(nc);
> unsigned int port_index = s->port_index;
> - unsigned int rxbase = port_index * (0x800 / 4);
>
> /* DA filter. */
> if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
> return size;
>
> - if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
> - trace_ethlite_pkt_lost(s->regs[R_RX_CTRL0]);
> + if (s->port[port_index].reg.rx_ctrl & CTRL_S) {
> + trace_ethlite_pkt_lost(s->port[port_index].reg.rx_ctrl);
> return -1;
> }
>
> @@ -229,8 +240,8 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
> }
> memcpy(rxbuf_ptr(s, port_index), buf, size);
>
> - s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
> - if (s->regs[R_RX_CTRL0] & CTRL_I) {
> + s->port[port_index].reg.rx_ctrl |= CTRL_S;
> + if (s->port[port_index].reg.rx_ctrl & CTRL_I) {
> eth_pulse_irq(s);
> }
>
> --
> 2.45.2
>