Series comparison

-[PATCH v2 00/16] hw/microblaze: Allow running cross-endian vCPUs
+[PATCH v6 00/11] hw/microblaze: Allow running cross-endian vCPUs
+Since v5:
+- Introduce QAPI EndianMode
+- Update RISCV machine while rebasing
+- Fixed INTC use on PPC (Thomas)
+- Dropped patch adding more machines (Daniel)
+Since v4 & v3:
+- Addressed Thomas review comments
+Since v2:
+- Addressed Richard's review comments
 Since v1:
 - Make device endianness configurable (Edgar)
 - Convert more Xilinx devices
 - Avoid preprocessor #if (Richard)
 - Add R-b tags
-Make machines endianness-agnostic, allowing to run a big-endian vCPU
+Philippe Mathieu-Daudé (11):
-on the little-endian 'qemu-system-microblazeel' binary, and a little
+  hw/qdev-properties-system: Introduce EndianMode QAPI enum
 endian one on the big-endian 'qemu-system-microblaze' binary.
 Tests added, following combinations covered:
 - little-endian vCPU using little-endian binary (in-tree)
 - little-endian vCPU using big-endian binary (new)
 - big-endian vCPU using little-endian binary (new)
 - big-endian vCPU using big-endian binary (in-tree)
 To make a target endian-agnostic we need to remove the MO_TE uses.
 In order to do that, we propagate the MemOp from earlier in the
 call stack, or we extract it from the vCPU env (on MicroBlaze the
 CPU endianness is exposed by the 'ENDI' bit).
 Next step: Look at unifying binaries.
 Please review,
 Phil.
 Philippe Mathieu-Daudé (16):
   hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit
   hw/microblaze: Propagate CPU endianness to microblaze_load_kernel()
   hw/intc/xilinx_intc: Make device endianness configurable
-  RFC hw/net/xilinx_ethlite: Simplify by having configurable endianness
+  hw/net/xilinx_ethlite: Make device endianness configurable
   RFC hw/timer/xilinx_timer: Allow down to 8-bit memory access
   hw/timer/xilinx_timer: Make device endianness configurable
   hw/char/xilinx_uartlite: Make device endianness configurable
   hw/ssi/xilinx_spi: Make device endianness configurable
-  hw/ssi/xilinx_spips: Make device endianness configurable
+  tests/functional: Avoid using www.qemu-advent-calendar.org URL
   target/microblaze: Explode MO_TExx -> MO_TE | MO_xx
   target/microblaze: Set MO_TE once in do_load() / do_store()
   target/microblaze: Introduce mo_endian() helper
   target/microblaze: Consider endianness while translating code
   hw/microblaze: Support various endianness for s3adsp1800 machines
   tests/functional: Explicit endianness of microblaze assets
-  tests/functional: Add microblaze cross-endianness tests
+  tests/functional: Allow microblaze tests to take a machine name
     argument
   tests/functional: Remove sleep() kludges from microblaze tests
   tests/functional: Have microblaze tests inherit common parent class
- hw/microblaze/boot.h                          |  4 +-
+ qapi/common.json                              | 16 +++++
- include/hw/ssi/xilinx_spips.h                 |  1 +
+ include/hw/qdev-properties-system.h           |  7 +++
- target/microblaze/cpu.h                       |  7 +++
+ hw/char/xilinx_uartlite.c                     | 34 +++++++----
- hw/arm/xilinx_zynq.c                          |  1 +
+ hw/core/qdev-properties-system.c              | 11 ++++
- hw/arm/xlnx-zynqmp.c                          |  4 ++
+ hw/intc/xilinx_intc.c                         | 60 ++++++++++++++-----
- hw/char/xilinx_uartlite.c                     | 40 +++++++++----
+ hw/microblaze/petalogix_ml605_mmu.c           |  3 +
- hw/intc/xilinx_intc.c                         | 59 +++++++++++++++----
+ hw/microblaze/petalogix_s3adsp1800_mmu.c      |  6 ++
- hw/microblaze/boot.c                          |  8 +--
+ hw/net/xilinx_ethlite.c                       | 27 +++++++--
- hw/microblaze/petalogix_ml605_mmu.c           |  4 +-
+ hw/ppc/virtex_ml507.c                         |  2 +
- hw/microblaze/petalogix_s3adsp1800_mmu.c      | 59 ++++++++++++++++---
+ hw/riscv/microblaze-v-generic.c               |  5 ++
- hw/microblaze/xlnx-zynqmp-pmu.c               |  2 +-
+ hw/ssi/xilinx_spi.c                           | 32 +++++++---
- hw/net/xilinx_ethlite.c                       | 52 ++++++++++++----
+ hw/timer/xilinx_timer.c                       | 43 +++++++++----
- hw/ppc/virtex_ml507.c                         |  1 +
+ .../functional/test_microblaze_s3adsp1800.py  | 35 +++++++++--
- hw/ssi/xilinx_spi.c                           | 29 ++++++---
+ .../test_microblazeel_s3adsp1800.py           | 32 ++--------
- hw/ssi/xilinx_spips.c                         | 46 +++++++++++----
+files changed, 229 insertions(+), 84 deletions(-)
  hw/timer/xilinx_timer.c                       | 42 ++++++++++---
  target/microblaze/translate.c                 | 49 +++++++++------
  .../functional/test_microblaze_s3adsp1800.py  | 27 ++++++++-
  .../test_microblazeel_s3adsp1800.py           | 25 +++++++-
 files changed, 358 insertions(+), 102 deletions(-)
 --
-.45.2
+.47.1

-[PATCH v2 01/16] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit
+Deleted patch
-All these MemoryRegionOps read() and write() handlers are
-implemented expecting 32-bit accesses. Clarify that setting
-.impl.min/max_access_size fields.
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Anton Johansson <anjo@rev.ng>
-Message-Id: <20241105130431.22564-8-philmd@linaro.org>
----
- hw/char/xilinx_uartlite.c | 4 ++++
- hw/intc/xilinx_intc.c     | 4 ++++
- hw/net/xilinx_ethlite.c   | 4 ++++
- hw/timer/xilinx_timer.c   | 4 ++++
-files changed, 16 insertions(+)
-diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/char/xilinx_uartlite.c
-+++ b/hw/char/xilinx_uartlite.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps uart_ops = {
-     .read = uart_read,
-     .write = uart_write,
-     .endianness = DEVICE_NATIVE_ENDIAN,
-+    .impl = {
-+        .min_access_size = 4,
-+        .max_access_size = 4,
-+    },
-     .valid = {
-         .min_access_size = 1,
-         .max_access_size = 4
-diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/xilinx_intc.c
-+++ b/hw/intc/xilinx_intc.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps pic_ops = {
-     .read = pic_read,
-     .write = pic_write,
-     .endianness = DEVICE_NATIVE_ENDIAN,
-+    .impl = {
-+        .min_access_size = 4,
-+        .max_access_size = 4,
-+    },
-     .valid = {
-         .min_access_size = 4,
-         .max_access_size = 4
-diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/net/xilinx_ethlite.c
-+++ b/hw/net/xilinx_ethlite.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps eth_ops = {
-     .read = eth_read,
-     .write = eth_write,
-     .endianness = DEVICE_NATIVE_ENDIAN,
-+    .impl = {
-+        .min_access_size = 4,
-+        .max_access_size = 4,
-+    },
-     .valid = {
-         .min_access_size = 4,
-         .max_access_size = 4
-diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/xilinx_timer.c
-+++ b/hw/timer/xilinx_timer.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps timer_ops = {
-     .read = timer_read,
-     .write = timer_write,
-     .endianness = DEVICE_NATIVE_ENDIAN,
-+    .impl = {
-+        .min_access_size = 4,
-+        .max_access_size = 4,
-+    },
-     .valid = {
-         .min_access_size = 4,
-         .max_access_size = 4
---
-.45.2

-[PATCH v2 02/16] hw/microblaze: Propagate CPU endianness to microblaze_load_kernel()
+Deleted patch
-Pass vCPU endianness as argument so we can load kernels
-with different endianness (different from the qemu-system-binary
-builtin one).
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Anton Johansson <anjo@rev.ng>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
-Message-Id: <20241105130431.22564-9-philmd@linaro.org>
----
- hw/microblaze/boot.h                     | 4 ++--
- hw/microblaze/boot.c                     | 8 ++++----
- hw/microblaze/petalogix_ml605_mmu.c      | 2 +-
- hw/microblaze/petalogix_s3adsp1800_mmu.c | 2 +-
- hw/microblaze/xlnx-zynqmp-pmu.c          | 2 +-
-files changed, 9 insertions(+), 9 deletions(-)
-diff --git a/hw/microblaze/boot.h b/hw/microblaze/boot.h
-index XXXXXXX..XXXXXXX 100644
---- a/hw/microblaze/boot.h
-+++ b/hw/microblaze/boot.h
-@@ -XXX,XX +XXX,XX @@
- #define MICROBLAZE_BOOT_H
--void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
--                            uint32_t ramsize,
-+void microblaze_load_kernel(MicroBlazeCPU *cpu, bool is_little_endian,
-+                            hwaddr ddr_base, uint32_t ramsize,
-                             const char *initrd_filename,
-                             const char *dtb_filename,
-                             void (*machine_cpu_reset)(MicroBlazeCPU *));
-diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/microblaze/boot.c
-+++ b/hw/microblaze/boot.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
-     return addr - 0x30000000LL;
- }
--void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
--                            uint32_t ramsize,
-+void microblaze_load_kernel(MicroBlazeCPU *cpu, bool is_little_endian,
-+                            hwaddr ddr_base, uint32_t ramsize,
-                             const char *initrd_filename,
-                             const char *dtb_filename,
-                             void (*machine_cpu_reset)(MicroBlazeCPU *))
-@@ -XXX,XX +XXX,XX @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
-         /* Boots a kernel elf binary.  */
-         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
-                                &entry, NULL, &high, NULL,
--                               TARGET_BIG_ENDIAN, EM_MICROBLAZE, 0, 0);
-+                               !is_little_endian, EM_MICROBLAZE, 0, 0);
-         base32 = entry;
-         if (base32 == 0xc0000000) {
-             kernel_size = load_elf(kernel_filename, NULL,
-                                    translate_kernel_address, NULL,
-                                    &entry, NULL, NULL, NULL,
--                                   TARGET_BIG_ENDIAN, EM_MICROBLAZE, 0, 0);
-+                                   !is_little_endian, EM_MICROBLAZE, 0, 0);
-         }
-         /* Always boot into physical ram.  */
-         boot_info.bootstrap_pc = (uint32_t)entry;
-diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/microblaze/petalogix_ml605_mmu.c
-+++ b/hw/microblaze/petalogix_ml605_mmu.c
-@@ -XXX,XX +XXX,XX @@ petalogix_ml605_init(MachineState *machine)
-     cpu->cfg.pvr_regs[5] = 0xc56be000;
-     cpu->cfg.pvr_regs[10] = 0x0e000000; /* virtex 6 */
--    microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
-+    microblaze_load_kernel(cpu, true, MEMORY_BASEADDR, ram_size,
-                            machine->initrd_filename,
-                            BINARY_DEVICE_TREE_FILE,
-                            NULL);
-diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
-+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
-@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
-     create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000);
--    microblaze_load_kernel(cpu, ddr_base, ram_size,
-+    microblaze_load_kernel(cpu, !TARGET_BIG_ENDIAN, ddr_base, ram_size,
-                            machine->initrd_filename,
-                            BINARY_DEVICE_TREE_FILE,
-                            NULL);
-diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/microblaze/xlnx-zynqmp-pmu.c
-+++ b/hw/microblaze/xlnx-zynqmp-pmu.c
-@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
-     qdev_realize(DEVICE(pmu), NULL, &error_fatal);
-     /* Load the kernel */
--    microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
-+    microblaze_load_kernel(&pmu->cpu, true, XLNX_ZYNQMP_PMU_RAM_ADDR,
-                            machine->ram_size,
-                            machine->initrd_filename,
-                            machine->dtb,
---
-.45.2

-[PATCH v2 09/16] hw/ssi/xilinx_spips: Make device endianness configurable
+[PATCH v6 01/11] hw/qdev-properties-system: Introduce EndianMode QAPI enum
-Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
+Introduce the EndianMode type and the DEFINE_PROP_ENDIAN() macros.
-of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
+Endianness can be BIG, LITTLE or unspecified (default).
 Add the "little-endian" property to select the device
 endianness, defaulting to little endian.
 Set the proper endianness on the single machine using the
 device.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 ---
- include/hw/ssi/xilinx_spips.h |  1 +
+ qapi/common.json                    | 16 ++++++++++++++++
- hw/arm/xilinx_zynq.c          |  1 +
+ include/hw/qdev-properties-system.h |  7 +++++++
- hw/ssi/xilinx_spips.c         | 46 ++++++++++++++++++++++++++---------
+ hw/core/qdev-properties-system.c    | 11 +++++++++++
-files changed, 36 insertions(+), 12 deletions(-)
+files changed, 34 insertions(+)
-diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h
+diff --git a/qapi/common.json b/qapi/common.json
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/ssi/xilinx_spips.h
+--- a/qapi/common.json
-+++ b/include/hw/ssi/xilinx_spips.h
++++ b/qapi/common.json
-@@ -XXX,XX +XXX,XX @@ typedef struct XilinxQSPIPS XilinxQSPIPS;
+@@ -XXX,XX +XXX,XX @@
- struct XlnxZynqMPQSPIPS {
+ ##
-     XilinxQSPIPS parent_obj;
+ { 'struct': 'HumanReadableText',
+   'data': { 'human-readable-text': 'str' } }
-+    bool little_endian_model;
++
-     StreamSink *dma;
++##
-     int gqspi_irqline;
++# @EndianMode:
++#
-diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
++# An enumeration of three options: little, big, and unspecified
 +#
 +# @little: Little endianness
 +#
 +# @big: Big endianness
 +#
 +# @unspecified: Endianness not specified
 +#
 +# Since: 10.0
 +##
 +{ 'enum': 'EndianMode',
 +  'data': [ 'little', 'big', 'unspecified' ] }
 diff --git a/include/hw/qdev-properties-system.h b/include/hw/qdev-properties-system.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xilinx_zynq.c
+--- a/include/hw/qdev-properties-system.h
-+++ b/hw/arm/xilinx_zynq.c
++++ b/include/hw/qdev-properties-system.h
-@@ -XXX,XX +XXX,XX @@ static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
+@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_pcie_link_speed;
-     int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
+ extern const PropertyInfo qdev_prop_pcie_link_width;
+ extern const PropertyInfo qdev_prop_cpus390entitlement;
-     dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
+ extern const PropertyInfo qdev_prop_iothread_vq_mapping_list;
-+    qdev_prop_set_bit(dev, "little-endian", true);
++extern const PropertyInfo qdev_prop_endian_mode;
-     qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
-     qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
+ #define DEFINE_PROP_PCI_DEVFN(_n, _s, _f, _d)                   \
-     qdev_prop_set_uint8(dev, "num-busses", num_busses);
+     DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_pci_devfn, int32_t)
-diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
+@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_iothread_vq_mapping_list;
      DEFINE_PROP(_name, _state, _field, qdev_prop_iothread_vq_mapping_list, \
                  IOThreadVirtQueueMappingList *)
 +#define DEFINE_PROP_ENDIAN(_name, _state, _field, _default) \
 +    DEFINE_PROP_UNSIGNED(_name, _state, _field, _default, \
 +                         qdev_prop_endian_mode, EndianMode)
 +#define DEFINE_PROP_ENDIAN_NODEFAULT(_name, _state, _field) \
 +    DEFINE_PROP_ENDIAN(_name, _state, _field, ENDIAN_MODE_UNSPECIFIED)
 +
  #endif
 diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/xilinx_spips.c
+--- a/hw/core/qdev-properties-system.c
-+++ b/hw/ssi/xilinx_spips.c
++++ b/hw/core/qdev-properties-system.c
-@@ -XXX,XX +XXX,XX @@ static MemTxResult lqspi_write(void *opaque, hwaddr offset, uint64_t value,
+@@ -XXX,XX +XXX,XX @@ const PropertyInfo qdev_prop_iothread_vq_mapping_list = {
-     return MEMTX_ERROR;
+     .set = set_iothread_vq_mapping_list,
- }
+     .release = release_iothread_vq_mapping_list,
 -static const MemoryRegionOps lqspi_ops = {
 -    .read_with_attrs = lqspi_read,
 -    .write_with_attrs = lqspi_write,
 -    .endianness = DEVICE_NATIVE_ENDIAN,
 -    .impl = {
 -        .min_access_size = 4,
 -        .max_access_size = 4,
 +static const MemoryRegionOps lqspi_ops[2] = {
 +    {
 +        .read_with_attrs = lqspi_read,
 +        .write_with_attrs = lqspi_write,
 +        .endianness = DEVICE_BIG_ENDIAN,
 +        .impl = {
 +            .min_access_size = 4,
 +            .max_access_size = 4,
 +        },
 +        .valid = {
 +            .min_access_size = 1,
 +            .max_access_size = 4
 +        },
      },
 -    .valid = {
 -        .min_access_size = 1,
 -        .max_access_size = 4
 +    {
 +        .read_with_attrs = lqspi_read,
 +        .write_with_attrs = lqspi_write,
 +        .endianness = DEVICE_LITTLE_ENDIAN,
 +        .impl = {
 +            .min_access_size = 4,
 +            .max_access_size = 4,
 +        },
 +        .valid = {
 +            .min_access_size = 1,
 +            .max_access_size = 4,
 +        },
      }
  };
++
-@@ -XXX,XX +XXX,XX @@ static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
++/* --- Endian modes */
-     s->num_txrx_bytes = 4;
++
++const PropertyInfo qdev_prop_endian_mode = {
-     xilinx_spips_realize(dev, errp);
++    .name = "EndianMode",
--    memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi",
++    .description = "Endian mode, big/little/unspecified",
--                          (1 << LQSPI_ADDRESS_BITS) * 2);
++    .enum_table = &EndianMode_lookup,
-+    memory_region_init_io(&s->mmlqspi, OBJECT(s),
++    .get = qdev_propinfo_get_enum,
-+                          &lqspi_ops[s->little_endian_model],
++    .set = qdev_propinfo_set_enum,
-+                          s, "lqspi", (1 << LQSPI_ADDRESS_BITS) * 2);
++    .set_default_value = qdev_propinfo_set_default_value_enum,
      sysbus_init_mmio(sbd, &s->mmlqspi);
      q->lqspi_cached_addr = ~0ULL;
@@ -XXX,XX +XXX,XX @@ static Property xilinx_spips_properties[] = {
      DEFINE_PROP_END_OF_LIST(),
  };
 +static Property xilinx_qspips_properties[] = {
 +    DEFINE_PROP_BOOL("little-endian", XilinxQSPIPS, little_endian_model, true),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
-+
- static void xilinx_qspips_class_init(ObjectClass *klass, void * data)
- {
-     DeviceClass *dc = DEVICE_CLASS(klass);
-     XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
-     dc->realize = xilinx_qspips_realize;
-+    device_class_set_props(dc, xilinx_qspips_properties);
-     xsc->reg_ops = &qspips_ops;
-     xsc->reg_size = XLNX_SPIPS_R_MAX * 4;
-     xsc->rx_fifo_size = RXFF_A_Q;
 --
-.45.2
+.47.1

-[PATCH v2 03/16] hw/intc/xilinx_intc: Make device endianness configurable
+[PATCH v6 02/11] hw/intc/xilinx_intc: Make device endianness configurable
 ...
 endianness, defaulting to little endian.
 Set the proper endianness for each machine using the device.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 ---
- hw/intc/xilinx_intc.c                    | 61 +++++++++++++++++++-----
+ hw/intc/xilinx_intc.c                    | 60 ++++++++++++++++++------
  hw/microblaze/petalogix_ml605_mmu.c      |  1 +
- hw/microblaze/petalogix_s3adsp1800_mmu.c |  1 +
+ hw/microblaze/petalogix_s3adsp1800_mmu.c |  3 ++
-files changed, 50 insertions(+), 13 deletions(-)
+ hw/ppc/virtex_ml507.c                    |  1 +
  hw/riscv/microblaze-v-generic.c          |  1 +
 files changed, 52 insertions(+), 14 deletions(-)
 diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/xilinx_intc.c
 +++ b/hw/intc/xilinx_intc.c
 ...
 + * DS572: LogiCORE IP XPS Interrupt Controller (v2.01a)
 + *
   * Permission is hereby granted, free of charge, to any person obtaining a copy
   * of this software and associated documentation files (the "Software"), to deal
   * in the Software without restriction, including without limitation the rights
+@@ -XXX,XX +XXX,XX @@
+  */
+ #include "qemu/osdep.h"
++#include "qapi/error.h"
+ #include "hw/sysbus.h"
+ #include "qemu/module.h"
+ #include "hw/irq.h"
+ #include "hw/qdev-properties.h"
++#include "hw/qdev-properties-system.h"
+ #include "qom/object.h"
+ #define D(x)
 @@ -XXX,XX +XXX,XX @@ struct XpsIntc
  {
      SysBusDevice parent_obj;
-+    bool little_endian_model;
++    EndianMode model_endianness;
      MemoryRegion mmio;
      qemu_irq parent_irq;
 @@ -XXX,XX +XXX,XX @@ static void pic_write(void *opaque, hwaddr addr,
      update_irq(p);
 ...
 -    .endianness = DEVICE_NATIVE_ENDIAN,
 -    .impl = {
 -        .min_access_size = 4,
 -        .max_access_size = 4,
 +static const MemoryRegionOps pic_ops[2] = {
-+    {
++    [0 ... 1] = {
 +        .read = pic_read,
 +        .write = pic_write,
 +        .endianness = DEVICE_BIG_ENDIAN,
 +        .impl = {
 +            .min_access_size = 4,
 ...
 +        },
      },
 -    .valid = {
 -        .min_access_size = 4,
 -        .max_access_size = 4
-+    {
+-    }
-+        .read = pic_read,
++    [ENDIAN_MODE_BIG].endianness = DEVICE_BIG_ENDIAN,
-+        .write = pic_write,
++    [ENDIAN_MODE_LITTLE].endianness = DEVICE_LITTLE_ENDIAN,
 +        .endianness = DEVICE_LITTLE_ENDIAN,
 +        .impl = {
 +            .min_access_size = 4,
 +            .max_access_size = 4,
 +        },
 +        .valid = {
 +            .min_access_size = 4,
 +            .max_access_size = 4,
 +        },
      }
  };
+ static void irq_handler(void *opaque, int irq, int level)
 @@ -XXX,XX +XXX,XX @@ static void xilinx_intc_init(Object *obj)
      qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
      sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq);
 -
 ...
 +static void xilinx_intc_realize(DeviceState *dev, Error **errp)
 +{
 +    XpsIntc *p = XILINX_INTC(dev);
 +
++    if (p->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
++        error_setg(errp, TYPE_XILINX_INTC " property 'endianness'"
++                         " must be set to 'big' or 'little'");
++        return;
++    }
++
 +    memory_region_init_io(&p->mmio, OBJECT(dev),
-+                          &pic_ops[p->little_endian_model],
++                          &pic_ops[p->model_endianness],
 +                          p, "xlnx.xps-intc",
 +                          R_MAX * 4);
 +}
 +
- static Property xilinx_intc_properties[] = {
+ static const Property xilinx_intc_properties[] = {
-+    DEFINE_PROP_BOOL("little-endian", XpsIntc, little_endian_model, true),
++    DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XpsIntc, model_endianness),
      DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0),
-     DEFINE_PROP_END_OF_LIST(),
  };
 @@ -XXX,XX +XXX,XX @@ static void xilinx_intc_class_init(ObjectClass *klass, void *data)
  {
      DeviceClass *dc = DEVICE_CLASS(klass);
 +    dc->realize = xilinx_intc_realize;
 ...
 +++ b/hw/microblaze/petalogix_ml605_mmu.c
 @@ -XXX,XX +XXX,XX @@ petalogix_ml605_init(MachineState *machine)
      dev = qdev_new("xlnx.xps-intc");
-+    qdev_prop_set_bit(dev, "little-endian", true);
++    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
      qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ);
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
      sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
 diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
 +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
 @@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
+     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
+     qemu_irq irq[32];
+     MemoryRegion *sysmem = get_system_memory();
++    EndianMode endianness = TARGET_BIG_ENDIAN ? ENDIAN_MODE_BIG
++                                              : ENDIAN_MODE_LITTLE;
+     cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
+     object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort);
+@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
      dev = qdev_new("xlnx.xps-intc");
-+    qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN);
++    qdev_prop_set_enum(dev, "endianness", endianness);
      qdev_prop_set_uint32(dev, "kind-of-intr",
 << ETHLITE_IRQ | 1 << UARTLITE_IRQ);
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/ppc/virtex_ml507.c
++++ b/hw/ppc/virtex_ml507.c
+@@ -XXX,XX +XXX,XX @@ static void virtex_init(MachineState *machine)
+     cpu_irq = qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT);
+     dev = qdev_new("xlnx.xps-intc");
++    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_BIG);
+     qdev_prop_set_uint32(dev, "kind-of-intr", 0);
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
+diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/microblaze-v-generic.c
++++ b/hw/riscv/microblaze-v-generic.c
+@@ -XXX,XX +XXX,XX @@ static void mb_v_generic_init(MachineState *machine)
+     memory_region_add_subregion(sysmem, ddr_base, phys_ram);
+     dev = qdev_new("xlnx.xps-intc");
++    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
+     qdev_prop_set_uint32(dev, "kind-of-intr",
+<< UARTLITE_IRQ);
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 --
-.45.2
+.47.1

-[RFC PATCH v2 04/16] hw/net/xilinx_ethlite: Simplify by having configurable endianness
+[PATCH v6 03/11] hw/net/xilinx_ethlite: Make device endianness configurable
-The Xilinx 'ethlite' device was added in commit b43848a100
+Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
-("xilinx: Add ethlite emulation"), being only built back
+of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
-then for a big-endian MicroBlaze target (see commit 72b675caac
+Add the "little-endian" property to select the device
-"microblaze: Hook into the build-system").
+endianness, defaulting to little endian.
+Set the proper endianness on the single machine using the
-I/O endianness access was then clarified in commit d48751ed4f
+device.
 ("xilinx-ethlite: Simplify byteswapping to/from brams"). Here
 the 'fix' was to use tswap32(). Since the machine was built as
 big-endian target, tswap32() use means the fix was for a little
 endian host. While the datasheet (reference added in file header)
 is not precise about it, we interpret such change as the device
 expects accesses in big-endian order.
 Instead of having a double swapping, one in the core memory layer
 due to DEVICE_NATIVE_ENDIAN and a second one with the tswap calls,
 allow the machine code to select the proper endianness desired,
 removing the need of tswap().
 Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of
 DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
 Add the "little-endian" property to select the device endianness,
 defaulting to little endian.
 Set the proper endianness on the single machine using the device.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 ---
-RFC until I digest Paolo's review from v1:
+ hw/microblaze/petalogix_s3adsp1800_mmu.c |  1 +
-https://lore.kernel.org/qemu-devel/34f6fe2f-06e0-4e2a-a361-2d662f6814b5@redhat.com/
+ hw/net/xilinx_ethlite.c                  | 27 ++++++++++++++++++------
----
+ hw/riscv/microblaze-v-generic.c          |  1 +
- hw/microblaze/petalogix_s3adsp1800_mmu.c |  2 +
+files changed, 23 insertions(+), 6 deletions(-)
  hw/net/xilinx_ethlite.c                  | 54 +++++++++++++++++-------
 files changed, 40 insertions(+), 16 deletions(-)
 diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
 +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
 @@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
      sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
      dev = qdev_new("xlnx.xps-ethernetlite");
-+    qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN);
++    qdev_prop_set_enum(dev, "endianness", endianness);
      qemu_configure_nic_device(dev, true, NULL);
      qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
      qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
-+    qdev_prop_set_bit(dev, "little-endian-model", !TARGET_BIG_ENDIAN);
-     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
-     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
 diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/net/xilinx_ethlite.c
 +++ b/hw/net/xilinx_ethlite.c
 @@ -XXX,XX +XXX,XX @@
-  *
-  * Copyright (c) 2009 Edgar E. Iglesias.
-  *
-+ * DS580: https://docs.amd.com/v/u/en-US/xps_ethernetlite
-+ * LogiCORE IP XPS Ethernet Lite Media Access Controller
-+ *
-  * Permission is hereby granted, free of charge, to any person obtaining a copy
-  * of this software and associated documentation files (the "Software"), to deal
-  * in the Software without restriction, including without limitation the rights
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/osdep.h"
- #include "qemu/module.h"
- #include "qom/object.h"
--#include "exec/tswap.h"
  #include "hw/sysbus.h"
  #include "hw/irq.h"
  #include "hw/qdev-properties.h"
-@@ -XXX,XX +XXX,XX @@ struct xlx_ethlite
++#include "hw/qdev-properties-system.h"
  #include "hw/misc/unimp.h"
  #include "net/net.h"
  #include "trace.h"
@@ -XXX,XX +XXX,XX @@ struct XlnxXpsEthLite
  {
      SysBusDevice parent_obj;
-+    bool little_endian_model;
++    EndianMode model_endianness;
-     MemoryRegion mmio;
+     MemoryRegion container;
      qemu_irq irq;
      NICState *nic;
-@@ -XXX,XX +XXX,XX @@ eth_read(void *opaque, hwaddr addr, unsigned int size)
+@@ -XXX,XX +XXX,XX @@ static void port_tx_write(void *opaque, hwaddr addr, uint64_t value,
              break;
          default:
 -            r = tswap32(s->regs[addr]);
 +            r = s->regs[addr];
              break;
      }
 +
      return r;
  }
@@ -XXX,XX +XXX,XX @@ eth_write(void *opaque, hwaddr addr,
              break;
          default:
 -            s->regs[addr] = tswap32(value);
 +            s->regs[addr] = value;
              break;
      }
  }
--static const MemoryRegionOps eth_ops = {
+-static const MemoryRegionOps eth_porttx_ops = {
--    .read = eth_read,
++static const MemoryRegionOps eth_porttx_ops[2] = {
--    .write = eth_write,
++    [0 ... 1] = {
--    .endianness = DEVICE_NATIVE_ENDIAN,
+         .read = port_tx_read,
--    .impl = {
+         .write = port_tx_write,
--        .min_access_size = 4,
+-        .endianness = DEVICE_NATIVE_ENDIAN,
--        .max_access_size = 4,
+         .impl = {
-+static const MemoryRegionOps eth_ops[2] = {
+             .min_access_size = 4,
-+    {
+             .max_access_size = 4,
-+        .read = eth_read,
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps eth_porttx_ops = {
-+        .write = eth_write,
+             .min_access_size = 4,
-+        .endianness = DEVICE_BIG_ENDIAN,
+             .max_access_size = 4,
-+        .impl = {
+         },
-+            .min_access_size = 4,
++    },
-+            .max_access_size = 4,
++    [ENDIAN_MODE_BIG].endianness = DEVICE_BIG_ENDIAN,
-+        },
++    [ENDIAN_MODE_LITTLE].endianness = DEVICE_LITTLE_ENDIAN,
-+        .valid = {
+ };
-+            .min_access_size = 4,
-+            .max_access_size = 4,
+ static uint64_t port_rx_read(void *opaque, hwaddr addr, unsigned int size)
-+        },
+@@ -XXX,XX +XXX,XX @@ static void port_rx_write(void *opaque, hwaddr addr, uint64_t value,
      },
 -    .valid = {
 -        .min_access_size = 4,
 -        .max_access_size = 4
 +    {
 +        .read = eth_read,
 +        .write = eth_write,
 +        .endianness = DEVICE_LITTLE_ENDIAN,
 +        .impl = {
 +            .min_access_size = 4,
 +            .max_access_size = 4,
 +        },
 +        .valid = {
 +            .min_access_size = 4,
 +            .max_access_size = 4,
 +        },
      }
+ }
+-static const MemoryRegionOps eth_portrx_ops = {
++static const MemoryRegionOps eth_portrx_ops[2] = {
++    [0 ... 1] = {
+         .read = port_rx_read,
+         .write = port_rx_write,
+-        .endianness = DEVICE_NATIVE_ENDIAN,
+         .impl = {
+             .min_access_size = 4,
+             .max_access_size = 4,
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps eth_portrx_ops = {
+             .min_access_size = 4,
+             .max_access_size = 4,
+         },
++    },
++    [ENDIAN_MODE_BIG].endianness = DEVICE_BIG_ENDIAN,
++    [ENDIAN_MODE_LITTLE].endianness = DEVICE_LITTLE_ENDIAN,
  };
+ static bool eth_can_rx(NetClientState *nc)
 @@ -XXX,XX +XXX,XX @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
  {
-     struct xlx_ethlite *s = XILINX_ETHLITE(dev);
+     XlnxXpsEthLite *s = XILINX_ETHLITE(dev);
-+    memory_region_init_io(&s->mmio, OBJECT(dev),
++    if (s->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
-+                          &eth_ops[s->little_endian_model], s,
++        error_setg(errp, TYPE_XILINX_ETHLITE " property 'endianness'"
-+                          "xlnx.xps-ethernetlite", R_MAX * 4);
++                         " must be set to 'big' or 'little'");
 +        return;
 +    }
 +
-     qemu_macaddr_default_if_unset(&s->conf.macaddr);
+     memory_region_init(&s->container, OBJECT(dev),
-     s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
+                        "xlnx.xps-ethernetlite", 0x2000);
-                           object_get_typename(OBJECT(dev)), dev->id,
@@ -XXX,XX +XXX,XX @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
                                 BUFSZ_MAX, &error_abort);
          memory_region_add_subregion(&s->container, 0x0800 * i, &s->port[i].txbuf);
          memory_region_init_io(&s->port[i].txio, OBJECT(dev),
 -                              &eth_porttx_ops, s,
 +                              &eth_porttx_ops[s->model_endianness], s,
                                i ? "ethlite.tx[1]io" : "ethlite.tx[0]io",
 * TX_MAX);
          memory_region_add_subregion(&s->container, i ? A_TX_BASE1 : A_TX_BASE0,
@@ -XXX,XX +XXX,XX @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
          memory_region_add_subregion(&s->container, 0x1000 + 0x0800 * i,
                                      &s->port[i].rxbuf);
          memory_region_init_io(&s->port[i].rxio, OBJECT(dev),
 -                              &eth_portrx_ops, s,
 +                              &eth_portrx_ops[s->model_endianness], s,
                                i ? "ethlite.rx[1]io" : "ethlite.rx[0]io",
 * RX_MAX);
          memory_region_add_subregion(&s->container, i ? A_RX_BASE1 : A_RX_BASE0,
 @@ -XXX,XX +XXX,XX @@ static void xilinx_ethlite_init(Object *obj)
-     struct xlx_ethlite *s = XILINX_ETHLITE(obj);
-     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
--
--    memory_region_init_io(&s->mmio, obj, &eth_ops, s,
--                          "xlnx.xps-ethernetlite", R_MAX * 4);
-     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
  }
- static Property xilinx_ethlite_properties[] = {
+ static const Property xilinx_ethlite_properties[] = {
-+    DEFINE_PROP_BOOL("little-endian", struct xlx_ethlite,
++    DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XlnxXpsEthLite, model_endianness),
-+                     little_endian_model, true),
+     DEFINE_PROP_UINT32("tx-ping-pong", XlnxXpsEthLite, c_tx_pingpong, 1),
-     DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1),
+     DEFINE_PROP_UINT32("rx-ping-pong", XlnxXpsEthLite, c_rx_pingpong, 1),
-     DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1),
+     DEFINE_NIC_PROPERTIES(XlnxXpsEthLite, conf),
-     DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
+diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microblaze-v-generic.c
 +++ b/hw/riscv/microblaze-v-generic.c
@@ -XXX,XX +XXX,XX @@ static void mb_v_generic_init(MachineState *machine)
      /* Emaclite */
      dev = qdev_new("xlnx.xps-ethernetlite");
 +    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
      qemu_configure_nic_device(dev, true, NULL);
      qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
      qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
 --
-.45.2
+.47.1

-[RFC PATCH v2 05/16] hw/timer/xilinx_timer: Allow down to 8-bit memory access
+Deleted patch
-Allow down to 8-bit access, per the datasheet (reference added
-in previous commit):
- "Timer Counter registers are accessed as one of the following types:
-  • Byte (8 bits)
-  • Half word (2 bytes)
-  • Word (4 bytes)"
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Anton Johansson <anjo@rev.ng>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
----
-RFC: This breaks the UART qtest, instead of having TX register
-receiving 'T' = 0x54, it receives 0x54000000, converted to '\0'
-char. It works if we use SWI instead of SBI (storing 32-bit).
----
- hw/timer/xilinx_timer.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/xilinx_timer.c
-+++ b/hw/timer/xilinx_timer.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps timer_ops = {
-         .max_access_size = 4,
-     },
-     .valid = {
--        .min_access_size = 4,
-+        .min_access_size = 1,
-         .max_access_size = 4
-     }
- };
---
-.45.2

-[PATCH v2 06/16] hw/timer/xilinx_timer: Make device endianness configurable
+[PATCH v6 04/11] hw/timer/xilinx_timer: Make device endianness configurable
 ...
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 ---
  hw/microblaze/petalogix_ml605_mmu.c      |  1 +
  hw/microblaze/petalogix_s3adsp1800_mmu.c |  1 +
  hw/ppc/virtex_ml507.c                    |  1 +
- hw/timer/xilinx_timer.c                  | 46 +++++++++++++++++-------
+ hw/riscv/microblaze-v-generic.c          |  2 ++
-files changed, 36 insertions(+), 13 deletions(-)
+ hw/timer/xilinx_timer.c                  | 43 +++++++++++++++++-------
 files changed, 35 insertions(+), 13 deletions(-)
 diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/microblaze/petalogix_ml605_mmu.c
 +++ b/hw/microblaze/petalogix_ml605_mmu.c
 @@ -XXX,XX +XXX,XX @@ petalogix_ml605_init(MachineState *machine)
      /* 2 timers at irq 2 @ 100 Mhz.  */
      dev = qdev_new("xlnx.xps-timer");
-+    qdev_prop_set_bit(dev, "little-endian", true);
++    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
      qdev_prop_set_uint32(dev, "one-timer-only", 0);
      qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000);
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
 +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
 @@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
      /* 2 timers at irq 2 @ 62 Mhz.  */
      dev = qdev_new("xlnx.xps-timer");
-+    qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN);
++    qdev_prop_set_enum(dev, "endianness", endianness);
      qdev_prop_set_uint32(dev, "one-timer-only", 0);
      qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/ppc/virtex_ml507.c
 +++ b/hw/ppc/virtex_ml507.c
 @@ -XXX,XX +XXX,XX @@ static void virtex_init(MachineState *machine)
      /* 2 timers at irq 2 @ 62 Mhz.  */
      dev = qdev_new("xlnx.xps-timer");
-+    qdev_prop_set_bit(dev, "little-endian", false);
++    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_BIG);
      qdev_prop_set_uint32(dev, "one-timer-only", 0);
      qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/microblaze-v-generic.c
++++ b/hw/riscv/microblaze-v-generic.c
+@@ -XXX,XX +XXX,XX @@ static void mb_v_generic_init(MachineState *machine)
+     /* 2 timers at irq 0 @ 100 Mhz.  */
+     dev = qdev_new("xlnx.xps-timer");
++    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
+     qdev_prop_set_uint32(dev, "one-timer-only", 0);
+     qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+@@ -XXX,XX +XXX,XX @@ static void mb_v_generic_init(MachineState *machine)
+     /* 2 timers at irq 3 @ 100 Mhz.  */
+     dev = qdev_new("xlnx.xps-timer");
++    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
+     qdev_prop_set_uint32(dev, "one-timer-only", 0);
+     qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/timer/xilinx_timer.c
 +++ b/hw/timer/xilinx_timer.c
 ...
 + * LogiCORE IP XPS Timer/Counter (v1.02a)
 + *
   * Permission is hereby granted, free of charge, to any person obtaining a copy
   * of this software and associated documentation files (the "Software"), to deal
   * in the Software without restriction, including without limitation the rights
+@@ -XXX,XX +XXX,XX @@
+  */
+ #include "qemu/osdep.h"
++#include "qapi/error.h"
+ #include "hw/sysbus.h"
+ #include "hw/irq.h"
+ #include "hw/ptimer.h"
+ #include "hw/qdev-properties.h"
++#include "hw/qdev-properties-system.h"
+ #include "qemu/log.h"
+ #include "qemu/module.h"
+ #include "qom/object.h"
 @@ -XXX,XX +XXX,XX @@ struct XpsTimerState
  {
      SysBusDevice parent_obj;
-+    bool little_endian_model;
++    EndianMode model_endianness;
      MemoryRegion mmio;
      qemu_irq irq;
      uint8_t one_timer_only;
 @@ -XXX,XX +XXX,XX @@ timer_write(void *opaque, hwaddr addr,
      timer_update_irq(t);
 ...
 -    .write = timer_write,
 -    .endianness = DEVICE_NATIVE_ENDIAN,
 -    .impl = {
 -        .min_access_size = 4,
 -        .max_access_size = 4,
--    },
--    .valid = {
--        .min_access_size = 1,
--        .max_access_size = 4
 +static const MemoryRegionOps timer_ops[2] = {
-+    {
++    [0 ... 1] = {
 +        .read = timer_read,
 +        .write = timer_write,
-+        .endianness = DEVICE_LITTLE_ENDIAN,
 +        .impl = {
 +            .min_access_size = 4,
 +            .max_access_size = 4,
 +        },
 +        .valid = {
-+            .min_access_size = 1,
-+            .max_access_size = 4,
-+        },
-+    }, {
-+        .read = timer_read,
-+        .write = timer_write,
-+        .endianness = DEVICE_BIG_ENDIAN,
-+        .impl = {
 +            .min_access_size = 4,
 +            .max_access_size = 4,
 +        },
-+        .valid = {
+     },
-+            .min_access_size = 1,
+-    .valid = {
-+            .max_access_size = 4,
+-        .min_access_size = 4,
-+        },
+-        .max_access_size = 4
-     }
+-    }
 +    [ENDIAN_MODE_BIG].endianness = DEVICE_BIG_ENDIAN,
 +    [ENDIAN_MODE_LITTLE].endianness = DEVICE_LITTLE_ENDIAN,
  };
+ static void timer_hit(void *opaque)
+@@ -XXX,XX +XXX,XX @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp)
+     XpsTimerState *t = XILINX_TIMER(dev);
+     unsigned int i;
++    if (t->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
++        error_setg(errp, TYPE_XILINX_TIMER " property 'endianness'"
++                         " must be set to 'big' or 'little'");
++        return;
++    }
++
+     /* Init all the ptimers.  */
+     t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
+     for (i = 0; i < num_timers(t); i++) {
 @@ -XXX,XX +XXX,XX @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp)
          ptimer_transaction_commit(xt->ptimer);
      }
 -    memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer",
 -                          R_MAX * 4 * num_timers(t));
 +    memory_region_init_io(&t->mmio, OBJECT(t),
-+                          &timer_ops[t->little_endian_model], t,
++                          &timer_ops[t->model_endianness], t,
 +                          "xlnx.xps-timer", R_MAX * 4 * num_timers(t));
      sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio);
  }
 @@ -XXX,XX +XXX,XX @@ static void xilinx_timer_init(Object *obj)
  }
- static Property xilinx_timer_properties[] = {
+ static const Property xilinx_timer_properties[] = {
-+    DEFINE_PROP_BOOL("little-endian", XpsTimerState, little_endian_model, true),
++    DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XpsTimerState, model_endianness),
      DEFINE_PROP_UINT32("clock-frequency", XpsTimerState, freq_hz, 62 * 1000000),
      DEFINE_PROP_UINT8("one-timer-only", XpsTimerState, one_timer_only, 0),
-     DEFINE_PROP_END_OF_LIST(),
+ };
 --
-.45.2
+.47.1

-[PATCH v2 07/16] hw/char/xilinx_uartlite: Make device endianness configurable
+[PATCH v6 05/11] hw/char/xilinx_uartlite: Make device endianness configurable
 ...
 Set the proper endianness on the single machine using the
 device.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 ---
- hw/char/xilinx_uartlite.c                | 44 ++++++++++++++++--------
+ hw/char/xilinx_uartlite.c                | 34 ++++++++++++++++--------
  hw/microblaze/petalogix_s3adsp1800_mmu.c |  1 +
-files changed, 31 insertions(+), 14 deletions(-)
+ hw/riscv/microblaze-v-generic.c          |  1 +
 files changed, 25 insertions(+), 11 deletions(-)
 diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/xilinx_uartlite.c
 +++ b/hw/char/xilinx_uartlite.c
 @@ -XXX,XX +XXX,XX @@
+ #include "qemu/osdep.h"
+ #include "qemu/log.h"
++#include "qapi/error.h"
+ #include "hw/char/xilinx_uartlite.h"
+ #include "hw/irq.h"
+ #include "hw/qdev-properties.h"
+@@ -XXX,XX +XXX,XX @@
  struct XilinxUARTLite {
      SysBusDevice parent_obj;
-+    bool little_endian_model;
++    EndianMode model_endianness;
      MemoryRegion mmio;
      CharBackend chr;
      qemu_irq irq;
 @@ -XXX,XX +XXX,XX @@ uart_write(void *opaque, hwaddr addr,
      uart_update_irq(s);
  }
 -static const MemoryRegionOps uart_ops = {
 -    .read = uart_read,
 -    .write = uart_write,
 -    .endianness = DEVICE_NATIVE_ENDIAN,
--    .impl = {
--        .min_access_size = 4,
--        .max_access_size = 4,
--    },
 -    .valid = {
 -        .min_access_size = 1,
 -        .max_access_size = 4
+-    }
 +static const MemoryRegionOps uart_ops[2] = {
-+    {
++    [0 ... 1] = {
 +        .read = uart_read,
 +        .write = uart_write,
-+        .endianness = DEVICE_BIG_ENDIAN,
-+        .impl = {
-+            .min_access_size = 4,
-+            .max_access_size = 4,
-+        },
 +        .valid = {
 +            .min_access_size = 1,
 +            .max_access_size = 4,
 +        },
-+    }, {
++    },
-+        .read = uart_read,
++    [ENDIAN_MODE_BIG].endianness = DEVICE_BIG_ENDIAN,
-+        .write = uart_write,
++    [ENDIAN_MODE_LITTLE].endianness = DEVICE_LITTLE_ENDIAN,
 +        .endianness = DEVICE_LITTLE_ENDIAN,
 +        .impl = {
 +            .min_access_size = 4,
 +            .max_access_size = 4,
 +        },
 +        .valid = {
 +            .min_access_size = 1,
 +            .max_access_size = 4,
 +        },
      }
  };
- static Property xilinx_uartlite_properties[] = {
+ static const Property xilinx_uartlite_properties[] = {
-+    DEFINE_PROP_BOOL("little-endian", XilinxUARTLite, little_endian_model, true),
++    DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XilinxUARTLite, model_endianness),
      DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr),
-     DEFINE_PROP_END_OF_LIST(),
  };
 @@ -XXX,XX +XXX,XX @@ static void xilinx_uartlite_realize(DeviceState *dev, Error **errp)
  {
      XilinxUARTLite *s = XILINX_UARTLITE(dev);
++    if (s->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
++        error_setg(errp, TYPE_XILINX_UARTLITE " property 'endianness'"
++                         " must be set to 'big' or 'little'");
++        return;
++    }
++
 +    memory_region_init_io(&s->mmio, OBJECT(dev),
-+                          &uart_ops[s->little_endian_model],
++                          &uart_ops[s->model_endianness],
 +                          s, "xlnx.xps-uartlite", R_MAX * 4);
      qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
                               uart_event, NULL, s, NULL, true);
  }
 @@ -XXX,XX +XXX,XX @@ static void xilinx_uartlite_init(Object *obj)
 ...
 +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
 @@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
      }
      dev = qdev_new(TYPE_XILINX_UARTLITE);
-+    qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN);
++    qdev_prop_set_enum(dev, "endianness", endianness);
      qdev_prop_set_chr(dev, "chardev", serial_hd(0));
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
      sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
 diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microblaze-v-generic.c
 +++ b/hw/riscv/microblaze-v-generic.c
@@ -XXX,XX +XXX,XX @@ static void mb_v_generic_init(MachineState *machine)
      /* Uartlite */
      dev = qdev_new(TYPE_XILINX_UARTLITE);
 +    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
      qdev_prop_set_chr(dev, "chardev", serial_hd(0));
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
      sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
 --
-.45.2
+.47.1

-[PATCH v2 08/16] hw/ssi/xilinx_spi: Make device endianness configurable
+[PATCH v6 06/11] hw/ssi/xilinx_spi: Make device endianness configurable
 ...
 Set the proper endianness on the single machine using the
 device.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 ---
- hw/arm/xlnx-zynqmp.c |  4 ++++
+ hw/microblaze/petalogix_ml605_mmu.c |  1 +
- hw/ssi/xilinx_spi.c  | 29 +++++++++++++++++++++--------
+ hw/ssi/xilinx_spi.c                 | 32 +++++++++++++++++++++--------
-files changed, 25 insertions(+), 8 deletions(-)
+files changed, 24 insertions(+), 9 deletions(-)
-diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
+diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-zynqmp.c
+--- a/hw/microblaze/petalogix_ml605_mmu.c
-+++ b/hw/arm/xlnx-zynqmp.c
++++ b/hw/microblaze/petalogix_ml605_mmu.c
-@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ petalogix_ml605_init(MachineState *machine)
-     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
+         SSIBus *spi;
-         gchar *bus_name;
+         dev = qdev_new("xlnx.xps-spi");
-+        if (!object_property_set_bool(OBJECT(&s->spi[i])), "little-endian",
++        qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
-+                                      true, errp)) {
+         qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
-+            return;
+         busdev = SYS_BUS_DEVICE(dev);
-+        }
+         sysbus_realize_and_unref(busdev, &error_fatal);
          if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
              return;
          }
 diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/ssi/xilinx_spi.c
 +++ b/hw/ssi/xilinx_spi.c
+@@ -XXX,XX +XXX,XX @@
+  */
+ #include "qemu/osdep.h"
++#include "qapi/error.h"
+ #include "hw/sysbus.h"
+ #include "migration/vmstate.h"
+ #include "qemu/module.h"
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/irq.h"
+ #include "hw/qdev-properties.h"
++#include "hw/qdev-properties-system.h"
+ #include "hw/ssi/ssi.h"
+ #include "qom/object.h"
 @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XilinxSPI, XILINX_SPI)
  struct XilinxSPI {
      SysBusDevice parent_obj;
-+    bool little_endian_model;
++    EndianMode model_endianness;
      MemoryRegion mmio;
      qemu_irq irq;
 @@ -XXX,XX +XXX,XX @@ done:
      xlx_spi_update_irq(s);
 ...
 -    .write = spi_write,
 -    .endianness = DEVICE_NATIVE_ENDIAN,
 -    .valid = {
 -        .min_access_size = 4,
 -        .max_access_size = 4
+-    }
 +static const MemoryRegionOps spi_ops[2] = {
-+    {
++    [0 ... 1] = {
 +        .read = spi_read,
 +        .write = spi_write,
-+        .endianness = DEVICE_BIG_ENDIAN,
 +        .valid = {
 +            .min_access_size = 4,
 +            .max_access_size = 4,
 +        },
-+    }, {
++    },
-+        .read = spi_read,
++    [ENDIAN_MODE_BIG].endianness = DEVICE_BIG_ENDIAN,
-+        .write = spi_write,
++    [ENDIAN_MODE_LITTLE].endianness = DEVICE_LITTLE_ENDIAN,
 +        .endianness = DEVICE_LITTLE_ENDIAN,
 +        .valid = {
 +            .min_access_size = 4,
 +            .max_access_size = 4,
 +        },
      }
  };
+ static void xilinx_spi_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void xilinx_spi_realize(DeviceState *dev, Error **errp)
+     XilinxSPI *s = XILINX_SPI(dev);
+     int i;
++    if (s->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
++        error_setg(errp, TYPE_XILINX_SPI " property 'endianness'"
++                         " must be set to 'big' or 'little'");
++        return;
++    }
++
+     DB_PRINT("\n");
+     s->spi = ssi_create_bus(dev, "spi");
 @@ -XXX,XX +XXX,XX @@ static void xilinx_spi_realize(DeviceState *dev, Error **errp)
          sysbus_init_irq(sbd, &s->cs_lines[i]);
      }
 -    memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
 +    memory_region_init_io(&s->mmio, OBJECT(s),
-+                          &spi_ops[s->little_endian_model], s,
++                          &spi_ops[s->model_endianness], s,
                            "xilinx-spi", R_MAX * 4);
      sysbus_init_mmio(sbd, &s->mmio);
 @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_xilinx_spi = {
  };
- static Property xilinx_spi_properties[] = {
+ static const Property xilinx_spi_properties[] = {
-+    DEFINE_PROP_BOOL("little-endian", XilinxSPI, little_endian_model, true),
++    DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XilinxSPI, model_endianness),
      DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1),
-     DEFINE_PROP_END_OF_LIST(),
  };
 --
-.45.2
+.47.1

-[PATCH v2 10/16] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx
+Deleted patch
-Extract the implicit MO_TE definition in order to replace
-it by runtime variable in the next commit.
-Mechanical change using:
-  $ for n in UW UL UQ UO SW SL SQ; do \
-      sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
-           $(git grep -l MO_TE$n target/microblaze); \
-    done
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/microblaze/translate.c | 36 +++++++++++++++++------------------
-file changed, 18 insertions(+), 18 deletions(-)
-diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/microblaze/translate.c
-+++ b/target/microblaze/translate.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg)
- static bool trans_lhu(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
-+    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
- }
- static bool trans_lhur(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true);
-+    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
- }
- static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
-@@ -XXX,XX +XXX,XX @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
-     return true;
- #else
-     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
--    return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false);
-+    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
- #endif
- }
- static bool trans_lhui(DisasContext *dc, arg_typeb *arg)
- {
-     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
--    return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
-+    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
- }
- static bool trans_lw(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
-+    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
- }
- static bool trans_lwr(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true);
-+    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
- }
- static bool trans_lwea(DisasContext *dc, arg_typea *arg)
-@@ -XXX,XX +XXX,XX @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
-     return true;
- #else
-     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
--    return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false);
-+    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
- #endif
- }
- static bool trans_lwi(DisasContext *dc, arg_typeb *arg)
- {
-     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
--    return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
-+    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
- }
- static bool trans_lwx(DisasContext *dc, arg_typea *arg)
-@@ -XXX,XX +XXX,XX @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
-     /* lwx does not throw unaligned access errors, so force alignment */
-     tcg_gen_andi_tl(addr, addr, ~3);
--    tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL);
-+    tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL);
-     tcg_gen_mov_tl(cpu_res_addr, addr);
-     if (arg->rd) {
-@@ -XXX,XX +XXX,XX @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg)
- static bool trans_sh(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
-+    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
- }
- static bool trans_shr(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true);
-+    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
- }
- static bool trans_shea(DisasContext *dc, arg_typea *arg)
-@@ -XXX,XX +XXX,XX @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
-     return true;
- #else
-     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
--    return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false);
-+    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
- #endif
- }
- static bool trans_shi(DisasContext *dc, arg_typeb *arg)
- {
-     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
--    return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
-+    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
- }
- static bool trans_sw(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
-+    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
- }
- static bool trans_swr(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true);
-+    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
- }
- static bool trans_swea(DisasContext *dc, arg_typea *arg)
-@@ -XXX,XX +XXX,XX @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
-     return true;
- #else
-     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
--    return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false);
-+    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
- #endif
- }
- static bool trans_swi(DisasContext *dc, arg_typeb *arg)
- {
-     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
--    return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
-+    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
- }
- static bool trans_swx(DisasContext *dc, arg_typea *arg)
-@@ -XXX,XX +XXX,XX @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
-     tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val,
-                                reg_for_write(dc, arg->rd),
--                               dc->mem_index, MO_TEUL);
-+                               dc->mem_index, MO_TE | MO_UL);
-     tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail);
---
-.45.2

-[PATCH v2 11/16] target/microblaze: Set MO_TE once in do_load() / do_store()
+Deleted patch
-All callers of do_load() / do_store() set MO_TE flag.
-Set it once in the callees.
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
----
- target/microblaze/translate.c | 36 +++++++++++++++++++----------------
-file changed, 20 insertions(+), 16 deletions(-)
-diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/microblaze/translate.c
-+++ b/target/microblaze/translate.c
-@@ -XXX,XX +XXX,XX @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
- {
-     MemOp size = mop & MO_SIZE;
-+    mop |= MO_TE;
-+
-     /*
-      * When doing reverse accesses we need to do two things.
-      *
-@@ -XXX,XX +XXX,XX @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg)
- static bool trans_lhu(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
-+    return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
- }
- static bool trans_lhur(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
-+    return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, true);
- }
- static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
-@@ -XXX,XX +XXX,XX @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
-     return true;
- #else
-     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
--    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
-+    return do_load(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false);
- #endif
- }
- static bool trans_lhui(DisasContext *dc, arg_typeb *arg)
- {
-     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
--    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
-+    return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
- }
- static bool trans_lw(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
-+    return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
- }
- static bool trans_lwr(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
-+    return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, true);
- }
- static bool trans_lwea(DisasContext *dc, arg_typea *arg)
-@@ -XXX,XX +XXX,XX @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
-     return true;
- #else
-     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
--    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
-+    return do_load(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false);
- #endif
- }
- static bool trans_lwi(DisasContext *dc, arg_typeb *arg)
- {
-     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
--    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
-+    return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
- }
- static bool trans_lwx(DisasContext *dc, arg_typea *arg)
-@@ -XXX,XX +XXX,XX @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,
- {
-     MemOp size = mop & MO_SIZE;
-+    mop |= MO_TE;
-+
-     /*
-      * When doing reverse accesses we need to do two things.
-      *
-@@ -XXX,XX +XXX,XX @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg)
- static bool trans_sh(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
-+    return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
- }
- static bool trans_shr(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
-+    return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, true);
- }
- static bool trans_shea(DisasContext *dc, arg_typea *arg)
-@@ -XXX,XX +XXX,XX @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
-     return true;
- #else
-     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
--    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
-+    return do_store(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false);
- #endif
- }
- static bool trans_shi(DisasContext *dc, arg_typeb *arg)
- {
-     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
--    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
-+    return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
- }
- static bool trans_sw(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
-+    return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
- }
- static bool trans_swr(DisasContext *dc, arg_typea *arg)
- {
-     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
--    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
-+    return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, true);
- }
- static bool trans_swea(DisasContext *dc, arg_typea *arg)
-@@ -XXX,XX +XXX,XX @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
-     return true;
- #else
-     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
--    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
-+    return do_store(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false);
- #endif
- }
- static bool trans_swi(DisasContext *dc, arg_typeb *arg)
- {
-     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
--    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
-+    return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
- }
- static bool trans_swx(DisasContext *dc, arg_typea *arg)
---
-.45.2

-[PATCH v2 14/16] hw/microblaze: Support various endianness for s3adsp1800 machines
+[PATCH v6 07/11] tests/functional: Avoid using www.qemu-advent-calendar.org URL
-Introduce an abstract machine parent class which defines
+Avoid fetching assets from www.qemu-advent-calendar.org
-the 'little_endian' property. Duplicate the current machine,
+website, prefer fetching microblaze assets from GitLab servers.
 which endian is tied to the binary endianness, to one big
 endian and a little endian machine; updating the machine
 description. Keep the current default machine for each binary.
-'petalogix-s3adsp1800' machine is aliased as:
+Suggested-by: Thomas Huth <thuth@redhat.com>
 - 'petalogix-s3adsp1800-be' on big-endian binary,
 - 'petalogix-s3adsp1800-le' on little-endian one.
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 ---
- hw/microblaze/petalogix_s3adsp1800_mmu.c | 62 +++++++++++++++++++-----
+ tests/functional/test_microblazeel_s3adsp1800.py | 3 ++-
-file changed, 51 insertions(+), 11 deletions(-)
+file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
+diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py
-index XXXXXXX..XXXXXXX 100644
+index XXXXXXX..XXXXXXX 100755
---- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+--- a/tests/functional/test_microblazeel_s3adsp1800.py
-+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
++++ b/tests/functional/test_microblazeel_s3adsp1800.py
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ class MicroblazeelMachine(QemuSystemTest):
- #define ETHLITE_IRQ         1
+     timeout = 90
- #define UARTLITE_IRQ        3
+     ASSET_IMAGE = Asset(
-+typedef struct PetalogixS3adsp1800MachineClass {
+-        ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'),
-+    MachineClass parent_obj;
++        ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/'
-+
++         'day05.tar.xz'),
-+    bool little_endian;
+         'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22')
-+} PetalogixS3adsp1800MachineClass;
-+
+     def test_microblazeel_s3adsp1800(self):
  #define TYPE_PETALOGIX_S3ADSP1800_MACHINE \
 -            MACHINE_TYPE_NAME("petalogix-s3adsp1800")
 +            MACHINE_TYPE_NAME("petalogix-s3adsp1800-common")
 +DECLARE_CLASS_CHECKERS(PetalogixS3adsp1800MachineClass,
 +                       PETALOGIX_S3ADSP1800_MACHINE,
 +                       TYPE_PETALOGIX_S3ADSP1800_MACHINE)
  static void
  petalogix_s3adsp1800_init(MachineState *machine)
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
      MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
      qemu_irq irq[32];
      MemoryRegion *sysmem = get_system_memory();
 +    PetalogixS3adsp1800MachineClass *pmc;
 +    pmc = PETALOGIX_S3ADSP1800_MACHINE_GET_CLASS(machine);
      cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
      object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort);
      object_property_set_bool(OBJECT(cpu), "little-endian",
 -                             !TARGET_BIG_ENDIAN, &error_abort);
 +                             pmc->little_endian, &error_abort);
      qdev_realize(DEVICE(cpu), NULL, &error_abort);
      /* Attach emulated BRAM through the LMB.  */
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
      dev = qdev_new("xlnx.xps-intc");
 -    qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN);
 +    qdev_prop_set_bit(dev, "little-endian", pmc->little_endian);
      qdev_prop_set_uint32(dev, "kind-of-intr",
 << ETHLITE_IRQ | 1 << UARTLITE_IRQ);
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
      }
      dev = qdev_new(TYPE_XILINX_UARTLITE);
 -    qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN);
 +    qdev_prop_set_bit(dev, "little-endian", pmc->little_endian);
      qdev_prop_set_chr(dev, "chardev", serial_hd(0));
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
      sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
      /* 2 timers at irq 2 @ 62 Mhz.  */
      dev = qdev_new("xlnx.xps-timer");
 -    qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN);
 +    qdev_prop_set_bit(dev, "little-endian", pmc->little_endian);
      qdev_prop_set_uint32(dev, "one-timer-only", 0);
      qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
      qemu_configure_nic_device(dev, true, NULL);
      qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
      qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
 -    qdev_prop_set_bit(dev, "little-endian-model", !TARGET_BIG_ENDIAN);
 +    qdev_prop_set_bit(dev, "little-endian", pmc->little_endian);
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
      sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
      sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
      create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000);
 -    microblaze_load_kernel(cpu, !TARGET_BIG_ENDIAN, ddr_base, ram_size,
 +    microblaze_load_kernel(cpu, pmc->little_endian, ddr_base, ram_size,
                             machine->initrd_filename,
                             BINARY_DEVICE_TREE_FILE,
                             NULL);
  }
 -static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, void *data)
 +static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc,
 +                                                    bool little_endian)
  {
      MachineClass *mc = MACHINE_CLASS(oc);
 +    PetalogixS3adsp1800MachineClass *pmc = PETALOGIX_S3ADSP1800_MACHINE_CLASS(oc);
 -    mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800";
      mc->init = petalogix_s3adsp1800_init;
 -    mc->is_default = true;
 +    pmc->little_endian = little_endian;
 +    mc->desc = little_endian
 +        ? "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800 (little endian)"
 +        : "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800 (big endian)";
 +    if (little_endian == !TARGET_BIG_ENDIAN) {
 +        mc->is_default = true;
 +        mc->alias = "petalogix-s3adsp1800";
 +    }
 +}
 +
 +static void petalogix_s3adsp1800_machine_class_init_be(ObjectClass *oc, void *data)
 +{
 +    petalogix_s3adsp1800_machine_class_init(oc, false);
 +}
 +
 +static void petalogix_s3adsp1800_machine_class_init_le(ObjectClass *oc, void *data)
 +{
 +    petalogix_s3adsp1800_machine_class_init(oc, true);
  }
  static const TypeInfo petalogix_s3adsp1800_machine_types[] = {
      {
          .name           = TYPE_PETALOGIX_S3ADSP1800_MACHINE,
          .parent         = TYPE_MACHINE,
 -        .class_init     = petalogix_s3adsp1800_machine_class_init,
 +        .abstract       = true,
 +        .class_size     = sizeof(PetalogixS3adsp1800MachineClass),
 +    },
 +    {
 +        .name           = MACHINE_TYPE_NAME("petalogix-s3adsp1800-be"),
 +        .parent         = TYPE_PETALOGIX_S3ADSP1800_MACHINE,
 +        .class_init     = petalogix_s3adsp1800_machine_class_init_be,
 +    },
 +    {
 +        .name           = MACHINE_TYPE_NAME("petalogix-s3adsp1800-le"),
 +        .parent         = TYPE_PETALOGIX_S3ADSP1800_MACHINE,
 +        .class_init     = petalogix_s3adsp1800_machine_class_init_le,
      },
  };
 --
-.45.2
+.47.1

-[PATCH v2 15/16] tests/functional: Explicit endianness of microblaze assets
+[PATCH v6 08/11] tests/functional: Explicit endianness of microblaze assets
 ...
 These changes will help when adding cross-endian kernel tests.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
+Message-Id: <20250206131052.30207-13-philmd@linaro.org>
 ---
  tests/functional/test_microblaze_s3adsp1800.py   | 6 +++---
  tests/functional/test_microblazeel_s3adsp1800.py | 6 +++---
 files changed, 6 insertions(+), 6 deletions(-)
 ...
          '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057')
 -    def test_microblaze_s3adsp1800(self):
 +    def test_microblaze_s3adsp1800_be(self):
          self.set_machine('petalogix-s3adsp1800')
--        file_path = self.ASSET_IMAGE.fetch()
+-        self.archive_extract(self.ASSET_IMAGE)
-+        file_path = self.ASSET_IMAGE_BE.fetch()
++        self.archive_extract(self.ASSET_IMAGE_BE)
          archive_extract(file_path, self.workdir)
          self.vm.set_console()
-         self.vm.add_args('-kernel', self.workdir + '/day17/ballerina.bin')
+         self.vm.add_args('-kernel',
                           self.scratch_file('day17', 'ballerina.bin'))
 diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py
 index XXXXXXX..XXXXXXX 100755
 --- a/tests/functional/test_microblazeel_s3adsp1800.py
 +++ b/tests/functional/test_microblazeel_s3adsp1800.py
 @@ -XXX,XX +XXX,XX @@ class MicroblazeelMachine(QemuSystemTest):
      timeout = 90
 -    ASSET_IMAGE = Asset(
 +    ASSET_IMAGE_LE = Asset(
-         ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'),
+         ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/'
           'day05.tar.xz'),
          'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22')
 -    def test_microblazeel_s3adsp1800(self):
 +    def test_microblazeel_s3adsp1800_le(self):
          self.require_netdev('user')
          self.set_machine('petalogix-s3adsp1800')
--        file_path = self.ASSET_IMAGE.fetch()
+-        self.archive_extract(self.ASSET_IMAGE)
-+        file_path = self.ASSET_IMAGE_LE.fetch()
++        self.archive_extract(self.ASSET_IMAGE_LE)
          archive_extract(file_path, self.workdir)
          self.vm.set_console()
-         self.vm.add_args('-kernel', self.workdir + '/day13/xmaton.bin')
+         self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin'))
          tftproot = self.scratch_file('day13')
 --
-.45.2
+.47.1

-[PATCH v2 16/16] tests/functional: Add microblaze cross-endianness tests
+[PATCH v6 09/11] tests/functional: Allow microblaze tests to take a machine name argument
-Copy/paste the current tests, but call the opposite endianness
+Make microblaze tests a bit more generic.
 machines, testing:
 - petalogix-s3adsp1800-le machine (little-endian CPU) on the
   qemu-system-microblaze binary (big-endian)
 - petalogix-s3adsp1800-be machine (big-endian CPU) on the
   qemu-system-microblazeel binary (little-endian).
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
 Message-Id: <20250206131052.30207-14-philmd@linaro.org>
 ---
- .../functional/test_microblaze_s3adsp1800.py  | 21 +++++++++++++++++++
+ tests/functional/test_microblaze_s3adsp1800.py   | 7 +++++--
- .../test_microblazeel_s3adsp1800.py           | 19 +++++++++++++++++
+ tests/functional/test_microblazeel_s3adsp1800.py | 7 +++++--
-files changed, 40 insertions(+)
+files changed, 10 insertions(+), 4 deletions(-)
 diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py
 index XXXXXXX..XXXXXXX 100755
 --- a/tests/functional/test_microblaze_s3adsp1800.py
 +++ b/tests/functional/test_microblaze_s3adsp1800.py
+@@ -XXX,XX +XXX,XX @@ class MicroblazeMachine(QemuSystemTest):
+          'day17.tar.xz'),
+         '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057')
+-    def test_microblaze_s3adsp1800_be(self):
+-        self.set_machine('petalogix-s3adsp1800')
++    def do_ballerina_be_test(self, machine):
++        self.set_machine(machine)
+         self.archive_extract(self.ASSET_IMAGE_BE)
+         self.vm.set_console()
+         self.vm.add_args('-kernel',
 @@ -XXX,XX +XXX,XX @@ def test_microblaze_s3adsp1800_be(self):
          # message, that's why we don't test for a later string here. This
          # needs some investigation by a microblaze wizard one day...
-+    ASSET_IMAGE_LE = Asset(
++    def test_microblaze_s3adsp1800_legacy_be(self):
-+        ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'),
++        self.do_ballerina_be_test('petalogix-s3adsp1800')
 +        'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22')
 +
 +    def test_microblaze_s3adsp1800_le(self):
 +        self.require_netdev('user')
 +        self.set_machine('petalogix-s3adsp1800-le')
 +        file_path = self.ASSET_IMAGE_LE.fetch()
 +        archive_extract(file_path, self.workdir)
 +        self.vm.set_console()
 +        self.vm.add_args('-kernel', self.workdir + '/day13/xmaton.bin')
 +        self.vm.add_args('-nic', 'user,tftp=' + self.workdir + '/day13/')
 +        self.vm.launch()
 +        wait_for_console_pattern(self, 'QEMU Advent Calendar 2023')
 +        time.sleep(0.1)
 +        exec_command(self, 'root')
 +        time.sleep(0.1)
 +        exec_command_and_wait_for_pattern(self,
 +                'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png',
 +                '821cd3cab8efd16ad6ee5acc3642a8ea')
 +
  if __name__ == '__main__':
      QemuSystemTest.main()
 diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py
 index XXXXXXX..XXXXXXX 100755
 --- a/tests/functional/test_microblazeel_s3adsp1800.py
 +++ b/tests/functional/test_microblazeel_s3adsp1800.py
+@@ -XXX,XX +XXX,XX @@ class MicroblazeelMachine(QemuSystemTest):
+          'day05.tar.xz'),
+         'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22')
+-    def test_microblazeel_s3adsp1800_le(self):
++    def do_xmaton_le_test(self, machine):
+         self.require_netdev('user')
+-        self.set_machine('petalogix-s3adsp1800')
++        self.set_machine(machine)
+         self.archive_extract(self.ASSET_IMAGE_LE)
+         self.vm.set_console()
+         self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin'))
 @@ -XXX,XX +XXX,XX @@ def test_microblazeel_s3adsp1800_le(self):
                  'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png',
                  '821cd3cab8efd16ad6ee5acc3642a8ea')
-+    ASSET_IMAGE_BE = Asset(
++    def test_microblaze_s3adsp1800_legacy_le(self):
-+        ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/'
++        self.do_xmaton_le_test('petalogix-s3adsp1800')
 +         'day17.tar.xz'),
 +        '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057')
 +
 +    def test_microblazeel_s3adsp1800_be(self):
 +        self.set_machine('petalogix-s3adsp1800-be')
 +        file_path = self.ASSET_IMAGE_BE.fetch()
 +        archive_extract(file_path, self.workdir)
 +        self.vm.set_console()
 +        self.vm.add_args('-kernel', self.workdir + '/day17/ballerina.bin')
 +        self.vm.launch()
 +        wait_for_console_pattern(self, 'This architecture does not have '
 +                                       'kernel memory protection')
 +        # Note:
 +        # The kernel sometimes gets stuck after the "This architecture ..."
 +        # message, that's why we don't test for a later string here. This
 +        # needs some investigation by a microblaze wizard one day...
 +
  if __name__ == '__main__':
      QemuSystemTest.main()
 --
-.45.2
+.47.1

-[PATCH v2 13/16] target/microblaze: Consider endianness while translating code
+[PATCH v6 10/11] tests/functional: Remove sleep() kludges from microblaze tests
-Consider the CPU ENDI bit, swap instructions when the CPU
+Commit f0ec14c78c4 ("tests/avocado: Fix console data loss") fixed
-endianness doesn't match the binary one.
+QEMUMachine's problem with console, we don't need to use the sleep()
 kludges.
+Suggested-by: Thomas Huth <thuth@redhat.com>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-Id: <20250206131052.30207-15-philmd@linaro.org>
 ---
- target/microblaze/cpu.h       | 7 +++++++
+ tests/functional/test_microblazeel_s3adsp1800.py | 8 +++-----
- target/microblaze/translate.c | 5 +++--
+file changed, 3 insertions(+), 5 deletions(-)
 files changed, 10 insertions(+), 2 deletions(-)
-diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
+diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py
-index XXXXXXX..XXXXXXX 100644
+index XXXXXXX..XXXXXXX 100755
---- a/target/microblaze/cpu.h
+--- a/tests/functional/test_microblazeel_s3adsp1800.py
-+++ b/target/microblaze/cpu.h
++++ b/tests/functional/test_microblazeel_s3adsp1800.py
-@@ -XXX,XX +XXX,XX @@ void mb_tcg_init(void);
+@@ -XXX,XX +XXX,XX @@
- /* Ensure there is no overlap between the two masks. */
+ # This work is licensed under the terms of the GNU GPL, version 2 or
- QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK);
+ # later. See the COPYING file in the top-level directory.
-+static inline bool mb_cpu_is_big_endian(CPUState *cs)
+-import time
-+{
+-from qemu_test import exec_command, exec_command_and_wait_for_pattern
-+    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
++from qemu_test import exec_command_and_wait_for_pattern
-+
+ from qemu_test import QemuSystemTest, Asset
-+    return !cpu->cfg.endi;
+ from qemu_test import wait_for_console_pattern
-+}
-+
+@@ -XXX,XX +XXX,XX @@ def do_xmaton_le_test(self, machine):
- static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc,
+         self.vm.add_args('-nic', f'user,tftp={tftproot}')
-                                         uint64_t *cs_base, uint32_t *flags)
+         self.vm.launch()
- {
+         wait_for_console_pattern(self, 'QEMU Advent Calendar 2023')
-diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
+-        time.sleep(0.1)
-index XXXXXXX..XXXXXXX 100644
+-        exec_command(self, 'root')
---- a/target/microblaze/translate.c
+-        time.sleep(0.1)
-+++ b/target/microblaze/translate.c
++        wait_for_console_pattern(self, 'buildroot login:')
-@@ -XXX,XX +XXX,XX @@ static void record_unaligned_ess(DisasContext *dc, int rd,
++        exec_command_and_wait_for_pattern(self, 'root', '#')
+         exec_command_and_wait_for_pattern(self,
- static inline MemOp mo_endian(DisasContext *dc)
+                 'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png',
- {
+                 '821cd3cab8efd16ad6ee5acc3642a8ea')
 -    return MO_TE;
 +    return dc->cfg->endi ? MO_LE : MO_BE;
  }
  static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
@@ -XXX,XX +XXX,XX @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
      dc->tb_flags_to_set = 0;
 -    ir = translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next);
 +    ir = translator_ldl_swap(cpu_env(cs), &dc->base, dc->base.pc_next,
 +                             mb_cpu_is_big_endian(cs) != TARGET_BIG_ENDIAN);
      if (!decode(dc, ir)) {
          trap_illegal(dc, true);
      }
 --
-.45.2
+.47.1

-[PATCH v2 12/16] target/microblaze: Introduce mo_endian() helper
+[PATCH v6 11/11] tests/functional: Have microblaze tests inherit common parent class
-mo_endian() returns the target endianness, currently static.
+Have the MicroblazeMachine class being common to both
 MicroblazeBigEndianMachine and MicroblazeLittleEndianMachine
 classes. Move the xmaton and ballerina tests to the parent class.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
 Message-Id: <20250206131052.30207-16-philmd@linaro.org>
 ---
- target/microblaze/translate.c | 14 ++++++++++----
+ .../functional/test_microblaze_s3adsp1800.py  | 24 +++++++++++++++
-file changed, 10 insertions(+), 4 deletions(-)
+ .../test_microblazeel_s3adsp1800.py           | 30 ++-----------------
 files changed, 27 insertions(+), 27 deletions(-)
-diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
+diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py
-index XXXXXXX..XXXXXXX 100644
+index XXXXXXX..XXXXXXX 100755
---- a/target/microblaze/translate.c
+--- a/tests/functional/test_microblaze_s3adsp1800.py
-+++ b/target/microblaze/translate.c
++++ b/tests/functional/test_microblaze_s3adsp1800.py
-@@ -XXX,XX +XXX,XX @@ static void record_unaligned_ess(DisasContext *dc, int rd,
+@@ -XXX,XX +XXX,XX @@
- }
+ # This work is licensed under the terms of the GNU GPL, version 2 or
- #endif
+ # later. See the COPYING file in the top-level directory.
-+static inline MemOp mo_endian(DisasContext *dc)
++from qemu_test import exec_command_and_wait_for_pattern
-+{
+ from qemu_test import QemuSystemTest, Asset
-+    return MO_TE;
+ from qemu_test import wait_for_console_pattern
-+}
@@ -XXX,XX +XXX,XX @@ class MicroblazeMachine(QemuSystemTest):
           'day17.tar.xz'),
          '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057')
 +    ASSET_IMAGE_LE = Asset(
 +        ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/'
 +         'day05.tar.xz'),
 +        'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22')
 +
- static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
+     def do_ballerina_be_test(self, machine):
-                     int mem_index, bool rev)
+         self.set_machine(machine)
- {
+         self.archive_extract(self.ASSET_IMAGE_BE)
-     MemOp size = mop & MO_SIZE;
+@@ -XXX,XX +XXX,XX @@ def do_ballerina_be_test(self, machine):
+         # message, that's why we don't test for a later string here. This
--    mop |= MO_TE;
+         # needs some investigation by a microblaze wizard one day...
-+    mop |= mo_endian(dc);
++    def do_xmaton_le_test(self, machine):
-     /*
++        self.require_netdev('user')
-      * When doing reverse accesses we need to do two things.
++        self.set_machine(machine)
-@@ -XXX,XX +XXX,XX @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
++        self.archive_extract(self.ASSET_IMAGE_LE)
-     /* lwx does not throw unaligned access errors, so force alignment */
++        self.vm.set_console()
-     tcg_gen_andi_tl(addr, addr, ~3);
++        self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin'))
++        tftproot = self.scratch_file('day13')
--    tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL);
++        self.vm.add_args('-nic', f'user,tftp={tftproot}')
-+    tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index,
++        self.vm.launch()
-+                        mo_endian(dc) | MO_UL);
++        wait_for_console_pattern(self, 'QEMU Advent Calendar 2023')
-     tcg_gen_mov_tl(cpu_res_addr, addr);
++        wait_for_console_pattern(self, 'buildroot login:')
++        exec_command_and_wait_for_pattern(self, 'root', '#')
-     if (arg->rd) {
++        exec_command_and_wait_for_pattern(self,
-@@ -XXX,XX +XXX,XX @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,
++                'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png',
- {
++                '821cd3cab8efd16ad6ee5acc3642a8ea')
-     MemOp size = mop & MO_SIZE;
++
++class MicroblazeBigEndianMachine(MicroblazeMachine):
--    mop |= MO_TE;
++
-+    mop |= mo_endian(dc);
+     def test_microblaze_s3adsp1800_legacy_be(self):
+         self.do_ballerina_be_test('petalogix-s3adsp1800')
-     /*
-      * When doing reverse accesses we need to do two things.
+diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py
-@@ -XXX,XX +XXX,XX @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
+index XXXXXXX..XXXXXXX 100755
+--- a/tests/functional/test_microblazeel_s3adsp1800.py
-     tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val,
++++ b/tests/functional/test_microblazeel_s3adsp1800.py
-                                reg_for_write(dc, arg->rd),
+@@ -XXX,XX +XXX,XX @@
--                               dc->mem_index, MO_TE | MO_UL);
+ # This work is licensed under the terms of the GNU GPL, version 2 or
-+                               dc->mem_index, mo_endian(dc) | MO_UL);
+ # later. See the COPYING file in the top-level directory.
-     tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail);
+-from qemu_test import exec_command_and_wait_for_pattern
+-from qemu_test import QemuSystemTest, Asset
 -from qemu_test import wait_for_console_pattern
 +from qemu_test import QemuSystemTest
 +from test_microblaze_s3adsp1800 import MicroblazeMachine
 -class MicroblazeelMachine(QemuSystemTest):
 -
 -    timeout = 90
 -
 -    ASSET_IMAGE_LE = Asset(
 -        ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/'
 -         'day05.tar.xz'),
 -        'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22')
 -
 -    def do_xmaton_le_test(self, machine):
 -        self.require_netdev('user')
 -        self.set_machine(machine)
 -        self.archive_extract(self.ASSET_IMAGE_LE)
 -        self.vm.set_console()
 -        self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin'))
 -        tftproot = self.scratch_file('day13')
 -        self.vm.add_args('-nic', f'user,tftp={tftproot}')
 -        self.vm.launch()
 -        wait_for_console_pattern(self, 'QEMU Advent Calendar 2023')
 -        wait_for_console_pattern(self, 'buildroot login:')
 -        exec_command_and_wait_for_pattern(self, 'root', '#')
 -        exec_command_and_wait_for_pattern(self,
 -                'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png',
 -                '821cd3cab8efd16ad6ee5acc3642a8ea')
 +class MicroblazeLittleEndianMachine(MicroblazeMachine):
      def test_microblaze_s3adsp1800_legacy_le(self):
          self.do_xmaton_le_test('petalogix-s3adsp1800')
 --
-.45.2
+.47.1

Since v1:
- Make device endianness configurable (Edgar)
- Convert more Xilinx devices
- Avoid preprocessor #if (Richard)
- Add R-b tags

Make machines endianness-agnostic, allowing to run a big-endian vCPU
on the little-endian 'qemu-system-microblazeel' binary, and a little
endian one on the big-endian 'qemu-system-microblaze' binary.

Tests added, following combinations covered:
- little-endian vCPU using little-endian binary (in-tree)
- little-endian vCPU using big-endian binary (new)
- big-endian vCPU using little-endian binary (new)
- big-endian vCPU using big-endian binary (in-tree)

To make a target endian-agnostic we need to remove the MO_TE uses.
In order to do that, we propagate the MemOp from earlier in the
call stack, or we extract it from the vCPU env (on MicroBlaze the
CPU endianness is exposed by the 'ENDI' bit).

Next step: Look at unifying binaries.

Please review,

Phil.

Philippe Mathieu-Daudé (16):
  hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit
  hw/microblaze: Propagate CPU endianness to microblaze_load_kernel()
  hw/intc/xilinx_intc: Make device endianness configurable
  RFC hw/net/xilinx_ethlite: Simplify by having configurable endianness
  RFC hw/timer/xilinx_timer: Allow down to 8-bit memory access
  hw/timer/xilinx_timer: Make device endianness configurable
  hw/char/xilinx_uartlite: Make device endianness configurable
  hw/ssi/xilinx_spi: Make device endianness configurable
  hw/ssi/xilinx_spips: Make device endianness configurable
  target/microblaze: Explode MO_TExx -> MO_TE | MO_xx
  target/microblaze: Set MO_TE once in do_load() / do_store()
  target/microblaze: Introduce mo_endian() helper
  target/microblaze: Consider endianness while translating code
  hw/microblaze: Support various endianness for s3adsp1800 machines
  tests/functional: Explicit endianness of microblaze assets
  tests/functional: Add microblaze cross-endianness tests

-- 
2.45.2

All these MemoryRegionOps read() and write() handlers are
implemented expecting 32-bit accesses. Clarify that setting
.impl.min/max_access_size fields.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20241105130431.22564-8-philmd@linaro.org>
---
 hw/char/xilinx_uartlite.c | 4 ++++
 hw/intc/xilinx_intc.c     | 4 ++++
 hw/net/xilinx_ethlite.c   | 4 ++++
 hw/timer/xilinx_timer.c   | 4 ++++
 4 files changed, 16 insertions(+)

diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/xilinx_uartlite.c
+++ b/hw/char/xilinx_uartlite.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps uart_ops = {
     .read = uart_read,
     .write = uart_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
     .valid = {
         .min_access_size = 1,
         .max_access_size = 4
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps pic_ops = {
     .read = pic_read,
     .write = pic_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
     .valid = {
         .min_access_size = 4,
         .max_access_size = 4
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps eth_ops = {
     .read = eth_read,
     .write = eth_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
     .valid = {
         .min_access_size = 4,
         .max_access_size = 4
diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/xilinx_timer.c
+++ b/hw/timer/xilinx_timer.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps timer_ops = {
     .read = timer_read,
     .write = timer_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
     .valid = {
         .min_access_size = 4,
         .max_access_size = 4
-- 
2.45.2

Pass vCPU endianness as argument so we can load kernels
with different endianness (different from the qemu-system-binary
builtin one).

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20241105130431.22564-9-philmd@linaro.org>
---
 hw/microblaze/boot.h                     | 4 ++--
 hw/microblaze/boot.c                     | 8 ++++----
 hw/microblaze/petalogix_ml605_mmu.c      | 2 +-
 hw/microblaze/petalogix_s3adsp1800_mmu.c | 2 +-
 hw/microblaze/xlnx-zynqmp-pmu.c          | 2 +-
 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/microblaze/boot.h b/hw/microblaze/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/boot.h
+++ b/hw/microblaze/boot.h
@@ -XXX,XX +XXX,XX @@
 #define MICROBLAZE_BOOT_H
 
 
-void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
-                            uint32_t ramsize,
+void microblaze_load_kernel(MicroBlazeCPU *cpu, bool is_little_endian,
+                            hwaddr ddr_base, uint32_t ramsize,
                             const char *initrd_filename,
                             const char *dtb_filename,
                             void (*machine_cpu_reset)(MicroBlazeCPU *));
diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/boot.c
+++ b/hw/microblaze/boot.c
@@ -XXX,XX +XXX,XX @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
     return addr - 0x30000000LL;
 }
 
-void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
-                            uint32_t ramsize,
+void microblaze_load_kernel(MicroBlazeCPU *cpu, bool is_little_endian,
+                            hwaddr ddr_base, uint32_t ramsize,
                             const char *initrd_filename,
                             const char *dtb_filename,
                             void (*machine_cpu_reset)(MicroBlazeCPU *))
@@ -XXX,XX +XXX,XX @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
         /* Boots a kernel elf binary.  */
         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
                                &entry, NULL, &high, NULL,
-                               TARGET_BIG_ENDIAN, EM_MICROBLAZE, 0, 0);
+                               !is_little_endian, EM_MICROBLAZE, 0, 0);
         base32 = entry;
         if (base32 == 0xc0000000) {
             kernel_size = load_elf(kernel_filename, NULL,
                                    translate_kernel_address, NULL,
                                    &entry, NULL, NULL, NULL,
-                                   TARGET_BIG_ENDIAN, EM_MICROBLAZE, 0, 0);
+                                   !is_little_endian, EM_MICROBLAZE, 0, 0);
         }
         /* Always boot into physical ram.  */
         boot_info.bootstrap_pc = (uint32_t)entry;
diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -XXX,XX +XXX,XX @@ petalogix_ml605_init(MachineState *machine)
     cpu->cfg.pvr_regs[5] = 0xc56be000;
     cpu->cfg.pvr_regs[10] = 0x0e000000; /* virtex 6 */
 
-    microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
+    microblaze_load_kernel(cpu, true, MEMORY_BASEADDR, ram_size,
                            machine->initrd_filename,
                            BINARY_DEVICE_TREE_FILE,
                            NULL);
diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
 
     create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000);
 
-    microblaze_load_kernel(cpu, ddr_base, ram_size,
+    microblaze_load_kernel(cpu, !TARGET_BIG_ENDIAN, ddr_base, ram_size,
                            machine->initrd_filename,
                            BINARY_DEVICE_TREE_FILE,
                            NULL);
diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/xlnx-zynqmp-pmu.c
+++ b/hw/microblaze/xlnx-zynqmp-pmu.c
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
     qdev_realize(DEVICE(pmu), NULL, &error_fatal);
 
     /* Load the kernel */
-    microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
+    microblaze_load_kernel(&pmu->cpu, true, XLNX_ZYNQMP_PMU_RAM_ADDR,
                            machine->ram_size,
                            machine->initrd_filename,
                            machine->dtb,
-- 
2.45.2

Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness for each machine using the device.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/intc/xilinx_intc.c                    | 61 +++++++++++++++++++-----
 hw/microblaze/petalogix_ml605_mmu.c      |  1 +
 hw/microblaze/petalogix_s3adsp1800_mmu.c |  1 +
 3 files changed, 50 insertions(+), 13 deletions(-)

The Xilinx 'ethlite' device was added in commit b43848a100
("xilinx: Add ethlite emulation"), being only built back
then for a big-endian MicroBlaze target (see commit 72b675caac
"microblaze: Hook into the build-system").

I/O endianness access was then clarified in commit d48751ed4f
("xilinx-ethlite: Simplify byteswapping to/from brams"). Here
the 'fix' was to use tswap32(). Since the machine was built as
big-endian target, tswap32() use means the fix was for a little
endian host. While the datasheet (reference added in file header)
is not precise about it, we interpret such change as the device
expects accesses in big-endian order.

Instead of having a double swapping, one in the core memory layer
due to DEVICE_NATIVE_ENDIAN and a second one with the tswap calls,
allow the machine code to select the proper endianness desired,
removing the need of tswap().

Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of
DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device endianness,
defaulting to little endian.
Set the proper endianness on the single machine using the device.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
RFC until I digest Paolo's review from v1:
https://lore.kernel.org/qemu-devel/34f6fe2f-06e0-4e2a-a361-2d662f6814b5@redhat.com/
---
 hw/microblaze/petalogix_s3adsp1800_mmu.c |  2 +
 hw/net/xilinx_ethlite.c                  | 54 +++++++++++++++++-------
 2 files changed, 40 insertions(+), 16 deletions(-)

diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
 
     dev = qdev_new("xlnx.xps-ethernetlite");
+    qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN);
     qemu_configure_nic_device(dev, true, NULL);
     qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
     qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
+    qdev_prop_set_bit(dev, "little-endian-model", !TARGET_BIG_ENDIAN);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -XXX,XX +XXX,XX @@
  *
  * Copyright (c) 2009 Edgar E. Iglesias.
  *
+ * DS580: https://docs.amd.com/v/u/en-US/xps_ethernetlite
+ * LogiCORE IP XPS Ethernet Lite Media Access Controller
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qemu/module.h"
 #include "qom/object.h"
-#include "exec/tswap.h"
 #include "hw/sysbus.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
@@ -XXX,XX +XXX,XX @@ struct xlx_ethlite
 {
     SysBusDevice parent_obj;
 
+    bool little_endian_model;
     MemoryRegion mmio;
     qemu_irq irq;
     NICState *nic;
@@ -XXX,XX +XXX,XX @@ eth_read(void *opaque, hwaddr addr, unsigned int size)
             break;
 
         default:
-            r = tswap32(s->regs[addr]);
+            r = s->regs[addr];
             break;
     }
+
     return r;
 }
 
@@ -XXX,XX +XXX,XX @@ eth_write(void *opaque, hwaddr addr,
             break;
 
         default:
-            s->regs[addr] = tswap32(value);
+            s->regs[addr] = value;
             break;
     }
 }
 
-static const MemoryRegionOps eth_ops = {
-    .read = eth_read,
-    .write = eth_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
-    .impl = {
-        .min_access_size = 4,
-        .max_access_size = 4,
+static const MemoryRegionOps eth_ops[2] = {
+    {
+        .read = eth_read,
+        .write = eth_write,
+        .endianness = DEVICE_BIG_ENDIAN,
+        .impl = {
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
+        .valid = {
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
     },
-    .valid = {
-        .min_access_size = 4,
-        .max_access_size = 4
+    {
+        .read = eth_read,
+        .write = eth_write,
+        .endianness = DEVICE_LITTLE_ENDIAN,
+        .impl = {
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
+        .valid = {
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
     }
 };
 
@@ -XXX,XX +XXX,XX @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
 {
     struct xlx_ethlite *s = XILINX_ETHLITE(dev);
 
+    memory_region_init_io(&s->mmio, OBJECT(dev),
+                          &eth_ops[s->little_endian_model], s,
+                          "xlnx.xps-ethernetlite", R_MAX * 4);
+
     qemu_macaddr_default_if_unset(&s->conf.macaddr);
     s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
                           object_get_typename(OBJECT(dev)), dev->id,
@@ -XXX,XX +XXX,XX @@ static void xilinx_ethlite_init(Object *obj)
     struct xlx_ethlite *s = XILINX_ETHLITE(obj);
 
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
-
-    memory_region_init_io(&s->mmio, obj, &eth_ops, s,
-                          "xlnx.xps-ethernetlite", R_MAX * 4);
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 }
 
 static Property xilinx_ethlite_properties[] = {
+    DEFINE_PROP_BOOL("little-endian", struct xlx_ethlite,
+                     little_endian_model, true),
     DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1),
     DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1),
     DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
-- 
2.45.2

Allow down to 8-bit access, per the datasheet (reference added
in previous commit):

"Timer Counter registers are accessed as one of the following types:
  • Byte (8 bits)
  • Half word (2 bytes)
  • Word (4 bytes)"

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
---
RFC: This breaks the UART qtest, instead of having TX register
receiving 'T' = 0x54, it receives 0x54000000, converted to '\0'
char. It works if we use SWI instead of SBI (storing 32-bit).
---
 hw/timer/xilinx_timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/xilinx_timer.c
+++ b/hw/timer/xilinx_timer.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps timer_ops = {
         .max_access_size = 4,
     },
     .valid = {
-        .min_access_size = 4,
+        .min_access_size = 1,
         .max_access_size = 4
     }
 };
-- 
2.45.2

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/microblaze/petalogix_ml605_mmu.c      |  1 +
 hw/microblaze/petalogix_s3adsp1800_mmu.c |  1 +
 hw/ppc/virtex_ml507.c                    |  1 +
 hw/timer/xilinx_timer.c                  | 46 +++++++++++++++++-------
 4 files changed, 36 insertions(+), 13 deletions(-)

diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -XXX,XX +XXX,XX @@ petalogix_ml605_init(MachineState *machine)
 
     /* 2 timers at irq 2 @ 100 Mhz.  */
     dev = qdev_new("xlnx.xps-timer");
+    qdev_prop_set_bit(dev, "little-endian", true);
     qdev_prop_set_uint32(dev, "one-timer-only", 0);
     qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
 
     /* 2 timers at irq 2 @ 62 Mhz.  */
     dev = qdev_new("xlnx.xps-timer");
+    qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN);
     qdev_prop_set_uint32(dev, "one-timer-only", 0);
     qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ppc/virtex_ml507.c
+++ b/hw/ppc/virtex_ml507.c
@@ -XXX,XX +XXX,XX @@ static void virtex_init(MachineState *machine)
 
     /* 2 timers at irq 2 @ 62 Mhz.  */
     dev = qdev_new("xlnx.xps-timer");
+    qdev_prop_set_bit(dev, "little-endian", false);
     qdev_prop_set_uint32(dev, "one-timer-only", 0);
     qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/xilinx_timer.c
+++ b/hw/timer/xilinx_timer.c
@@ -XXX,XX +XXX,XX @@
  *
  * Copyright (c) 2009 Edgar E. Iglesias.
  *
+ * DS573: https://docs.amd.com/v/u/en-US/xps_timer
+ * LogiCORE IP XPS Timer/Counter (v1.02a)
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
@@ -XXX,XX +XXX,XX @@ struct XpsTimerState
 {
     SysBusDevice parent_obj;
 
+    bool little_endian_model;
     MemoryRegion mmio;
     qemu_irq irq;
     uint8_t one_timer_only;
@@ -XXX,XX +XXX,XX @@ timer_write(void *opaque, hwaddr addr,
     timer_update_irq(t);
 }
 
-static const MemoryRegionOps timer_ops = {
-    .read = timer_read,
-    .write = timer_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
-    .impl = {
-        .min_access_size = 4,
-        .max_access_size = 4,
-    },
-    .valid = {
-        .min_access_size = 1,
-        .max_access_size = 4
+static const MemoryRegionOps timer_ops[2] = {
+    {
+        .read = timer_read,
+        .write = timer_write,
+        .endianness = DEVICE_LITTLE_ENDIAN,
+        .impl = {
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
+        .valid = {
+            .min_access_size = 1,
+            .max_access_size = 4,
+        },
+    }, {
+        .read = timer_read,
+        .write = timer_write,
+        .endianness = DEVICE_BIG_ENDIAN,
+        .impl = {
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
+        .valid = {
+            .min_access_size = 1,
+            .max_access_size = 4,
+        },
     }
 };
 
@@ -XXX,XX +XXX,XX @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp)
         ptimer_transaction_commit(xt->ptimer);
     }
 
-    memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer",
-                          R_MAX * 4 * num_timers(t));
+    memory_region_init_io(&t->mmio, OBJECT(t),
+                          &timer_ops[t->little_endian_model], t,
+                          "xlnx.xps-timer", R_MAX * 4 * num_timers(t));
     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio);
 }
 
@@ -XXX,XX +XXX,XX @@ static void xilinx_timer_init(Object *obj)
 }
 
 static Property xilinx_timer_properties[] = {
+    DEFINE_PROP_BOOL("little-endian", XpsTimerState, little_endian_model, true),
     DEFINE_PROP_UINT32("clock-frequency", XpsTimerState, freq_hz, 62 * 1000000),
     DEFINE_PROP_UINT8("one-timer-only", XpsTimerState, one_timer_only, 0),
     DEFINE_PROP_END_OF_LIST(),
-- 
2.45.2

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/char/xilinx_uartlite.c                | 44 ++++++++++++++++--------
 hw/microblaze/petalogix_s3adsp1800_mmu.c |  1 +
 2 files changed, 31 insertions(+), 14 deletions(-)

diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/xilinx_uartlite.c
+++ b/hw/char/xilinx_uartlite.c
@@ -XXX,XX +XXX,XX @@
 struct XilinxUARTLite {
     SysBusDevice parent_obj;
 
+    bool little_endian_model;
     MemoryRegion mmio;
     CharBackend chr;
     qemu_irq irq;
@@ -XXX,XX +XXX,XX @@ uart_write(void *opaque, hwaddr addr,
     uart_update_irq(s);
 }
 
-static const MemoryRegionOps uart_ops = {
-    .read = uart_read,
-    .write = uart_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
-    .impl = {
-        .min_access_size = 4,
-        .max_access_size = 4,
-    },
-    .valid = {
-        .min_access_size = 1,
-        .max_access_size = 4
+static const MemoryRegionOps uart_ops[2] = {
+    {
+        .read = uart_read,
+        .write = uart_write,
+        .endianness = DEVICE_BIG_ENDIAN,
+        .impl = {
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
+        .valid = {
+            .min_access_size = 1,
+            .max_access_size = 4,
+        },
+    }, {
+        .read = uart_read,
+        .write = uart_write,
+        .endianness = DEVICE_LITTLE_ENDIAN,
+        .impl = {
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
+        .valid = {
+            .min_access_size = 1,
+            .max_access_size = 4,
+        },
     }
 };
 
 static Property xilinx_uartlite_properties[] = {
+    DEFINE_PROP_BOOL("little-endian", XilinxUARTLite, little_endian_model, true),
     DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr),
     DEFINE_PROP_END_OF_LIST(),
 };
@@ -XXX,XX +XXX,XX @@ static void xilinx_uartlite_realize(DeviceState *dev, Error **errp)
 {
     XilinxUARTLite *s = XILINX_UARTLITE(dev);
 
+    memory_region_init_io(&s->mmio, OBJECT(dev),
+                          &uart_ops[s->little_endian_model],
+                          s, "xlnx.xps-uartlite", R_MAX * 4);
     qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
                              uart_event, NULL, s, NULL, true);
 }
@@ -XXX,XX +XXX,XX @@ static void xilinx_uartlite_init(Object *obj)
     XilinxUARTLite *s = XILINX_UARTLITE(obj);
 
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
-
-    memory_region_init_io(&s->mmio, obj, &uart_ops, s,
-                          "xlnx.xps-uartlite", R_MAX * 4);
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 }
 
diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
     }
 
     dev = qdev_new(TYPE_XILINX_UARTLITE);
+    qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN);
     qdev_prop_set_chr(dev, "chardev", serial_hd(0));
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
-- 
2.45.2

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/xlnx-zynqmp.c |  4 ++++
 hw/ssi/xilinx_spi.c  | 29 +++++++++++++++++++++--------
 2 files changed, 25 insertions(+), 8 deletions(-)

diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
         gchar *bus_name;
 
+        if (!object_property_set_bool(OBJECT(&s->spi[i])), "little-endian",
+                                      true, errp)) {
+            return;
+        }
         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
             return;
         }
diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/xilinx_spi.c
+++ b/hw/ssi/xilinx_spi.c
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XilinxSPI, XILINX_SPI)
 struct XilinxSPI {
     SysBusDevice parent_obj;
 
+    bool little_endian_model;
     MemoryRegion mmio;
 
     qemu_irq irq;
@@ -XXX,XX +XXX,XX @@ done:
     xlx_spi_update_irq(s);
 }
 
-static const MemoryRegionOps spi_ops = {
-    .read = spi_read,
-    .write = spi_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
-    .valid = {
-        .min_access_size = 4,
-        .max_access_size = 4
+static const MemoryRegionOps spi_ops[2] = {
+    {
+        .read = spi_read,
+        .write = spi_write,
+        .endianness = DEVICE_BIG_ENDIAN,
+        .valid = {
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
+    }, {
+        .read = spi_read,
+        .write = spi_write,
+        .endianness = DEVICE_LITTLE_ENDIAN,
+        .valid = {
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
     }
 };
 
@@ -XXX,XX +XXX,XX @@ static void xilinx_spi_realize(DeviceState *dev, Error **errp)
         sysbus_init_irq(sbd, &s->cs_lines[i]);
     }
 
-    memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
+    memory_region_init_io(&s->mmio, OBJECT(s),
+                          &spi_ops[s->little_endian_model], s,
                           "xilinx-spi", R_MAX * 4);
     sysbus_init_mmio(sbd, &s->mmio);
 
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_xilinx_spi = {
 };
 
 static Property xilinx_spi_properties[] = {
+    DEFINE_PROP_BOOL("little-endian", XilinxSPI, little_endian_model, true),
     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1),
     DEFINE_PROP_END_OF_LIST(),
 };
-- 
2.45.2

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/ssi/xilinx_spips.h |  1 +
 hw/arm/xilinx_zynq.c          |  1 +
 hw/ssi/xilinx_spips.c         | 46 ++++++++++++++++++++++++++---------
 3 files changed, 36 insertions(+), 12 deletions(-)

diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/ssi/xilinx_spips.h
+++ b/include/hw/ssi/xilinx_spips.h
@@ -XXX,XX +XXX,XX @@ typedef struct XilinxQSPIPS XilinxQSPIPS;
 struct XlnxZynqMPQSPIPS {
     XilinxQSPIPS parent_obj;
 
+    bool little_endian_model;
     StreamSink *dma;
     int gqspi_irqline;
 
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -XXX,XX +XXX,XX @@ static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
     int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
 
     dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
+    qdev_prop_set_bit(dev, "little-endian", true);
     qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
     qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
     qdev_prop_set_uint8(dev, "num-busses", num_busses);
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -XXX,XX +XXX,XX @@ static MemTxResult lqspi_write(void *opaque, hwaddr offset, uint64_t value,
     return MEMTX_ERROR;
 }
 
-static const MemoryRegionOps lqspi_ops = {
-    .read_with_attrs = lqspi_read,
-    .write_with_attrs = lqspi_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
-    .impl = {
-        .min_access_size = 4,
-        .max_access_size = 4,
+static const MemoryRegionOps lqspi_ops[2] = {
+    {
+        .read_with_attrs = lqspi_read,
+        .write_with_attrs = lqspi_write,
+        .endianness = DEVICE_BIG_ENDIAN,
+        .impl = {
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
+        .valid = {
+            .min_access_size = 1,
+            .max_access_size = 4
+        },
     },
-    .valid = {
-        .min_access_size = 1,
-        .max_access_size = 4
+    {
+        .read_with_attrs = lqspi_read,
+        .write_with_attrs = lqspi_write,
+        .endianness = DEVICE_LITTLE_ENDIAN,
+        .impl = {
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
+        .valid = {
+            .min_access_size = 1,
+            .max_access_size = 4,
+        },
     }
 };
 
@@ -XXX,XX +XXX,XX @@ static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
     s->num_txrx_bytes = 4;
 
     xilinx_spips_realize(dev, errp);
-    memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi",
-                          (1 << LQSPI_ADDRESS_BITS) * 2);
+    memory_region_init_io(&s->mmlqspi, OBJECT(s),
+                          &lqspi_ops[s->little_endian_model],
+                          s, "lqspi", (1 << LQSPI_ADDRESS_BITS) * 2);
     sysbus_init_mmio(sbd, &s->mmlqspi);
 
     q->lqspi_cached_addr = ~0ULL;
@@ -XXX,XX +XXX,XX @@ static Property xilinx_spips_properties[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+static Property xilinx_qspips_properties[] = {
+    DEFINE_PROP_BOOL("little-endian", XilinxQSPIPS, little_endian_model, true),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
 static void xilinx_qspips_class_init(ObjectClass *klass, void * data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
     XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
 
     dc->realize = xilinx_qspips_realize;
+    device_class_set_props(dc, xilinx_qspips_properties);
     xsc->reg_ops = &qspips_ops;
     xsc->reg_size = XLNX_SPIPS_R_MAX * 4;
     xsc->rx_fifo_size = RXFF_A_Q;
-- 
2.45.2

Extract the implicit MO_TE definition in order to replace
it by runtime variable in the next commit.

Mechanical change using:

$ for n in UW UL UQ UO SW SL SQ; do \
      sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
           $(git grep -l MO_TE$n target/microblaze); \
    done

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/microblaze/translate.c | 36 +++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg)
 static bool trans_lhu(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
 }
 
 static bool trans_lhur(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true);
+    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
 }
 
 static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
@@ -XXX,XX +XXX,XX @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
     return true;
 #else
     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
-    return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false);
+    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
 #endif
 }
 
 static bool trans_lhui(DisasContext *dc, arg_typeb *arg)
 {
     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
-    return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
 }
 
 static bool trans_lw(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
 }
 
 static bool trans_lwr(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true);
+    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
 }
 
 static bool trans_lwea(DisasContext *dc, arg_typea *arg)
@@ -XXX,XX +XXX,XX @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
     return true;
 #else
     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
-    return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false);
+    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
 #endif
 }
 
 static bool trans_lwi(DisasContext *dc, arg_typeb *arg)
 {
     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
-    return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
 }
 
 static bool trans_lwx(DisasContext *dc, arg_typea *arg)
@@ -XXX,XX +XXX,XX @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
     /* lwx does not throw unaligned access errors, so force alignment */
     tcg_gen_andi_tl(addr, addr, ~3);
 
-    tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL);
+    tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL);
     tcg_gen_mov_tl(cpu_res_addr, addr);
 
     if (arg->rd) {
@@ -XXX,XX +XXX,XX @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg)
 static bool trans_sh(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
 }
 
 static bool trans_shr(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true);
+    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
 }
 
 static bool trans_shea(DisasContext *dc, arg_typea *arg)
@@ -XXX,XX +XXX,XX @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
     return true;
 #else
     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
-    return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false);
+    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
 #endif
 }
 
 static bool trans_shi(DisasContext *dc, arg_typeb *arg)
 {
     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
-    return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
 }
 
 static bool trans_sw(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
 }
 
 static bool trans_swr(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true);
+    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
 }
 
 static bool trans_swea(DisasContext *dc, arg_typea *arg)
@@ -XXX,XX +XXX,XX @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
     return true;
 #else
     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
-    return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false);
+    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
 #endif
 }
 
 static bool trans_swi(DisasContext *dc, arg_typeb *arg)
 {
     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
-    return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
 }
 
 static bool trans_swx(DisasContext *dc, arg_typea *arg)
@@ -XXX,XX +XXX,XX @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
 
     tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val,
                                reg_for_write(dc, arg->rd),
-                               dc->mem_index, MO_TEUL);
+                               dc->mem_index, MO_TE | MO_UL);
 
     tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail);
 
-- 
2.45.2

All callers of do_load() / do_store() set MO_TE flag.
Set it once in the callees.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/translate.c | 36 +++++++++++++++++++----------------
 1 file changed, 20 insertions(+), 16 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -XXX,XX +XXX,XX @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
 {
     MemOp size = mop & MO_SIZE;
 
+    mop |= MO_TE;
+
     /*
      * When doing reverse accesses we need to do two things.
      *
@@ -XXX,XX +XXX,XX @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg)
 static bool trans_lhu(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
+    return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
 }
 
 static bool trans_lhur(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
+    return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, true);
 }
 
 static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
@@ -XXX,XX +XXX,XX @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
     return true;
 #else
     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
-    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
+    return do_load(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false);
 #endif
 }
 
 static bool trans_lhui(DisasContext *dc, arg_typeb *arg)
 {
     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
-    return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
+    return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
 }
 
 static bool trans_lw(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
+    return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
 }
 
 static bool trans_lwr(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
+    return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, true);
 }
 
 static bool trans_lwea(DisasContext *dc, arg_typea *arg)
@@ -XXX,XX +XXX,XX @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
     return true;
 #else
     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
-    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
+    return do_load(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false);
 #endif
 }
 
 static bool trans_lwi(DisasContext *dc, arg_typeb *arg)
 {
     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
-    return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
+    return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
 }
 
 static bool trans_lwx(DisasContext *dc, arg_typea *arg)
@@ -XXX,XX +XXX,XX @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,
 {
     MemOp size = mop & MO_SIZE;
 
+    mop |= MO_TE;
+
     /*
      * When doing reverse accesses we need to do two things.
      *
@@ -XXX,XX +XXX,XX @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg)
 static bool trans_sh(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
+    return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
 }
 
 static bool trans_shr(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
+    return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, true);
 }
 
 static bool trans_shea(DisasContext *dc, arg_typea *arg)
@@ -XXX,XX +XXX,XX @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
     return true;
 #else
     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
-    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
+    return do_store(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false);
 #endif
 }
 
 static bool trans_shi(DisasContext *dc, arg_typeb *arg)
 {
     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
-    return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
+    return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
 }
 
 static bool trans_sw(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
+    return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
 }
 
 static bool trans_swr(DisasContext *dc, arg_typea *arg)
 {
     TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
-    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
+    return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, true);
 }
 
 static bool trans_swea(DisasContext *dc, arg_typea *arg)
@@ -XXX,XX +XXX,XX @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
     return true;
 #else
     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
-    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
+    return do_store(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false);
 #endif
 }
 
 static bool trans_swi(DisasContext *dc, arg_typeb *arg)
 {
     TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
-    return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
+    return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
 }
 
 static bool trans_swx(DisasContext *dc, arg_typea *arg)
-- 
2.45.2

mo_endian() returns the target endianness, currently static.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/translate.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -XXX,XX +XXX,XX @@ static void record_unaligned_ess(DisasContext *dc, int rd,
 }
 #endif
 
+static inline MemOp mo_endian(DisasContext *dc)
+{
+    return MO_TE;
+}
+
 static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
                     int mem_index, bool rev)
 {
     MemOp size = mop & MO_SIZE;
 
-    mop |= MO_TE;
+    mop |= mo_endian(dc);
 
     /*
      * When doing reverse accesses we need to do two things.
@@ -XXX,XX +XXX,XX @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
     /* lwx does not throw unaligned access errors, so force alignment */
     tcg_gen_andi_tl(addr, addr, ~3);
 
-    tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL);
+    tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index,
+                        mo_endian(dc) | MO_UL);
     tcg_gen_mov_tl(cpu_res_addr, addr);
 
     if (arg->rd) {
@@ -XXX,XX +XXX,XX @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,
 {
     MemOp size = mop & MO_SIZE;
 
-    mop |= MO_TE;
+    mop |= mo_endian(dc);
 
     /*
      * When doing reverse accesses we need to do two things.
@@ -XXX,XX +XXX,XX @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
 
     tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val,
                                reg_for_write(dc, arg->rd),
-                               dc->mem_index, MO_TE | MO_UL);
+                               dc->mem_index, mo_endian(dc) | MO_UL);
 
     tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail);
 
-- 
2.45.2

Consider the CPU ENDI bit, swap instructions when the CPU
endianness doesn't match the binary one.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/cpu.h       | 7 +++++++
 target/microblaze/translate.c | 5 +++--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -XXX,XX +XXX,XX @@ void mb_tcg_init(void);
 /* Ensure there is no overlap between the two masks. */
 QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK);
 
+static inline bool mb_cpu_is_big_endian(CPUState *cs)
+{
+    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+
+    return !cpu->cfg.endi;
+}
+
 static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *flags)
 {
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -XXX,XX +XXX,XX @@ static void record_unaligned_ess(DisasContext *dc, int rd,
 
 static inline MemOp mo_endian(DisasContext *dc)
 {
-    return MO_TE;
+    return dc->cfg->endi ? MO_LE : MO_BE;
 }
 
 static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
@@ -XXX,XX +XXX,XX @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
 
     dc->tb_flags_to_set = 0;
 
-    ir = translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next);
+    ir = translator_ldl_swap(cpu_env(cs), &dc->base, dc->base.pc_next,
+                             mb_cpu_is_big_endian(cs) != TARGET_BIG_ENDIAN);
     if (!decode(dc, ir)) {
         trap_illegal(dc, true);
     }
-- 
2.45.2

Introduce an abstract machine parent class which defines
the 'little_endian' property. Duplicate the current machine,
which endian is tied to the binary endianness, to one big
endian and a little endian machine; updating the machine
description. Keep the current default machine for each binary.

'petalogix-s3adsp1800' machine is aliased as:
- 'petalogix-s3adsp1800-be' on big-endian binary,
- 'petalogix-s3adsp1800-le' on little-endian one.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/microblaze/petalogix_s3adsp1800_mmu.c | 62 +++++++++++++++++++-----
 1 file changed, 51 insertions(+), 11 deletions(-)

diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
@@ -XXX,XX +XXX,XX @@
 #define ETHLITE_IRQ         1
 #define UARTLITE_IRQ        3
 
+typedef struct PetalogixS3adsp1800MachineClass {
+    MachineClass parent_obj;
+
+    bool little_endian;
+} PetalogixS3adsp1800MachineClass;
+
 #define TYPE_PETALOGIX_S3ADSP1800_MACHINE \
-            MACHINE_TYPE_NAME("petalogix-s3adsp1800")
+            MACHINE_TYPE_NAME("petalogix-s3adsp1800-common")
+DECLARE_CLASS_CHECKERS(PetalogixS3adsp1800MachineClass,
+                       PETALOGIX_S3ADSP1800_MACHINE,
+                       TYPE_PETALOGIX_S3ADSP1800_MACHINE)
 
 static void
 petalogix_s3adsp1800_init(MachineState *machine)
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
     qemu_irq irq[32];
     MemoryRegion *sysmem = get_system_memory();
+    PetalogixS3adsp1800MachineClass *pmc;
 
+    pmc = PETALOGIX_S3ADSP1800_MACHINE_GET_CLASS(machine);
     cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
     object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort);
     object_property_set_bool(OBJECT(cpu), "little-endian",
-                             !TARGET_BIG_ENDIAN, &error_abort);
+                             pmc->little_endian, &error_abort);
     qdev_realize(DEVICE(cpu), NULL, &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
                           64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
 
     dev = qdev_new("xlnx.xps-intc");
-    qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN);
+    qdev_prop_set_bit(dev, "little-endian", pmc->little_endian);
     qdev_prop_set_uint32(dev, "kind-of-intr",
                          1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
     }
 
     dev = qdev_new(TYPE_XILINX_UARTLITE);
-    qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN);
+    qdev_prop_set_bit(dev, "little-endian", pmc->little_endian);
     qdev_prop_set_chr(dev, "chardev", serial_hd(0));
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
 
     /* 2 timers at irq 2 @ 62 Mhz.  */
     dev = qdev_new("xlnx.xps-timer");
-    qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN);
+    qdev_prop_set_bit(dev, "little-endian", pmc->little_endian);
     qdev_prop_set_uint32(dev, "one-timer-only", 0);
     qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
     qemu_configure_nic_device(dev, true, NULL);
     qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
     qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
-    qdev_prop_set_bit(dev, "little-endian-model", !TARGET_BIG_ENDIAN);
+    qdev_prop_set_bit(dev, "little-endian", pmc->little_endian);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
 
     create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000);
 
-    microblaze_load_kernel(cpu, !TARGET_BIG_ENDIAN, ddr_base, ram_size,
+    microblaze_load_kernel(cpu, pmc->little_endian, ddr_base, ram_size,
                            machine->initrd_filename,
                            BINARY_DEVICE_TREE_FILE,
                            NULL);
 }
 
-static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, void *data)
+static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc,
+                                                    bool little_endian)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
+    PetalogixS3adsp1800MachineClass *pmc = PETALOGIX_S3ADSP1800_MACHINE_CLASS(oc);
 
-    mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800";
     mc->init = petalogix_s3adsp1800_init;
-    mc->is_default = true;
+    pmc->little_endian = little_endian;
+    mc->desc = little_endian
+        ? "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800 (little endian)"
+        : "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800 (big endian)";
+    if (little_endian == !TARGET_BIG_ENDIAN) {
+        mc->is_default = true;
+        mc->alias = "petalogix-s3adsp1800";
+    }
+}
+
+static void petalogix_s3adsp1800_machine_class_init_be(ObjectClass *oc, void *data)
+{
+    petalogix_s3adsp1800_machine_class_init(oc, false);
+}
+
+static void petalogix_s3adsp1800_machine_class_init_le(ObjectClass *oc, void *data)
+{
+    petalogix_s3adsp1800_machine_class_init(oc, true);
 }
 
 static const TypeInfo petalogix_s3adsp1800_machine_types[] = {
     {
         .name           = TYPE_PETALOGIX_S3ADSP1800_MACHINE,
         .parent         = TYPE_MACHINE,
-        .class_init     = petalogix_s3adsp1800_machine_class_init,
+        .abstract       = true,
+        .class_size     = sizeof(PetalogixS3adsp1800MachineClass),
+    },
+    {
+        .name           = MACHINE_TYPE_NAME("petalogix-s3adsp1800-be"),
+        .parent         = TYPE_PETALOGIX_S3ADSP1800_MACHINE,
+        .class_init     = petalogix_s3adsp1800_machine_class_init_be,
+    },
+    {
+        .name           = MACHINE_TYPE_NAME("petalogix-s3adsp1800-le"),
+        .parent         = TYPE_PETALOGIX_S3ADSP1800_MACHINE,
+        .class_init     = petalogix_s3adsp1800_machine_class_init_le,
     },
 };
 
-- 
2.45.2

The archive used in test_microblaze_s3adsp1800.py (testing a
big-endian target) contains a big-endian kernel. Rename using
the _BE suffix.

Similarly, the archive in test_microblazeel_s3adsp1800 (testing
a little-endian target) contains a little-endian kernel. Rename
using _LE suffix.

These changes will help when adding cross-endian kernel tests.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 tests/functional/test_microblaze_s3adsp1800.py   | 6 +++---
 tests/functional/test_microblazeel_s3adsp1800.py | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

Copy/paste the current tests, but call the opposite endianness
machines, testing:
- petalogix-s3adsp1800-le machine (little-endian CPU) on the
  qemu-system-microblaze binary (big-endian)
- petalogix-s3adsp1800-be machine (big-endian CPU) on the
  qemu-system-microblazeel binary (little-endian).

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 .../functional/test_microblaze_s3adsp1800.py  | 21 +++++++++++++++++++
 .../test_microblazeel_s3adsp1800.py           | 19 +++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py
index XXXXXXX..XXXXXXX 100755
--- a/tests/functional/test_microblaze_s3adsp1800.py
+++ b/tests/functional/test_microblaze_s3adsp1800.py
@@ -XXX,XX +XXX,XX @@ def test_microblaze_s3adsp1800_be(self):
         # message, that's why we don't test for a later string here. This
         # needs some investigation by a microblaze wizard one day...
 
+    ASSET_IMAGE_LE = Asset(
+        ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'),
+        'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22')
+
+    def test_microblaze_s3adsp1800_le(self):
+        self.require_netdev('user')
+        self.set_machine('petalogix-s3adsp1800-le')
+        file_path = self.ASSET_IMAGE_LE.fetch()
+        archive_extract(file_path, self.workdir)
+        self.vm.set_console()
+        self.vm.add_args('-kernel', self.workdir + '/day13/xmaton.bin')
+        self.vm.add_args('-nic', 'user,tftp=' + self.workdir + '/day13/')
+        self.vm.launch()
+        wait_for_console_pattern(self, 'QEMU Advent Calendar 2023')
+        time.sleep(0.1)
+        exec_command(self, 'root')
+        time.sleep(0.1)
+        exec_command_and_wait_for_pattern(self,
+                'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png',
+                '821cd3cab8efd16ad6ee5acc3642a8ea')
+
 if __name__ == '__main__':
     QemuSystemTest.main()
diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py
index XXXXXXX..XXXXXXX 100755
--- a/tests/functional/test_microblazeel_s3adsp1800.py
+++ b/tests/functional/test_microblazeel_s3adsp1800.py
@@ -XXX,XX +XXX,XX @@ def test_microblazeel_s3adsp1800_le(self):
                 'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png',
                 '821cd3cab8efd16ad6ee5acc3642a8ea')
 
+    ASSET_IMAGE_BE = Asset(
+        ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/'
+         'day17.tar.xz'),
+        '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057')
+
+    def test_microblazeel_s3adsp1800_be(self):
+        self.set_machine('petalogix-s3adsp1800-be')
+        file_path = self.ASSET_IMAGE_BE.fetch()
+        archive_extract(file_path, self.workdir)
+        self.vm.set_console()
+        self.vm.add_args('-kernel', self.workdir + '/day17/ballerina.bin')
+        self.vm.launch()
+        wait_for_console_pattern(self, 'This architecture does not have '
+                                       'kernel memory protection')
+        # Note:
+        # The kernel sometimes gets stuck after the "This architecture ..."
+        # message, that's why we don't test for a later string here. This
+        # needs some investigation by a microblaze wizard one day...
+
 if __name__ == '__main__':
     QemuSystemTest.main()
-- 
2.45.2

Since v5:
- Introduce QAPI EndianMode
- Update RISCV machine while rebasing
- Fixed INTC use on PPC (Thomas)
- Dropped patch adding more machines (Daniel)

Since v4 & v3:
- Addressed Thomas review comments

Since v2:
- Addressed Richard's review comments

Since v1:
- Make device endianness configurable (Edgar)
- Convert more Xilinx devices
- Avoid preprocessor #if (Richard)
- Add R-b tags

Philippe Mathieu-Daudé (11):
  hw/qdev-properties-system: Introduce EndianMode QAPI enum
  hw/intc/xilinx_intc: Make device endianness configurable
  hw/net/xilinx_ethlite: Make device endianness configurable
  hw/timer/xilinx_timer: Make device endianness configurable
  hw/char/xilinx_uartlite: Make device endianness configurable
  hw/ssi/xilinx_spi: Make device endianness configurable
  tests/functional: Avoid using www.qemu-advent-calendar.org URL
  tests/functional: Explicit endianness of microblaze assets
  tests/functional: Allow microblaze tests to take a machine name
    argument
  tests/functional: Remove sleep() kludges from microblaze tests
  tests/functional: Have microblaze tests inherit common parent class

qapi/common.json                              | 16 +++++
 include/hw/qdev-properties-system.h           |  7 +++
 hw/char/xilinx_uartlite.c                     | 34 +++++++----
 hw/core/qdev-properties-system.c              | 11 ++++
 hw/intc/xilinx_intc.c                         | 60 ++++++++++++++-----
 hw/microblaze/petalogix_ml605_mmu.c           |  3 +
 hw/microblaze/petalogix_s3adsp1800_mmu.c      |  6 ++
 hw/net/xilinx_ethlite.c                       | 27 +++++++--
 hw/ppc/virtex_ml507.c                         |  2 +
 hw/riscv/microblaze-v-generic.c               |  5 ++
 hw/ssi/xilinx_spi.c                           | 32 +++++++---
 hw/timer/xilinx_timer.c                       | 43 +++++++++----
 .../functional/test_microblaze_s3adsp1800.py  | 35 +++++++++--
 .../test_microblazeel_s3adsp1800.py           | 32 ++--------
 14 files changed, 229 insertions(+), 84 deletions(-)

-- 
2.47.1

Introduce the EndianMode type and the DEFINE_PROP_ENDIAN() macros.
Endianness can be BIG, LITTLE or unspecified (default).

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 qapi/common.json                    | 16 ++++++++++++++++
 include/hw/qdev-properties-system.h |  7 +++++++
 hw/core/qdev-properties-system.c    | 11 +++++++++++
 3 files changed, 34 insertions(+)

diff --git a/qapi/common.json b/qapi/common.json
index XXXXXXX..XXXXXXX 100644
--- a/qapi/common.json
+++ b/qapi/common.json
@@ -XXX,XX +XXX,XX @@
 ##
 { 'struct': 'HumanReadableText',
   'data': { 'human-readable-text': 'str' } }
+
+##
+# @EndianMode:
+#
+# An enumeration of three options: little, big, and unspecified
+#
+# @little: Little endianness
+#
+# @big: Big endianness
+#
+# @unspecified: Endianness not specified
+#
+# Since: 10.0
+##
+{ 'enum': 'EndianMode',
+  'data': [ 'little', 'big', 'unspecified' ] }
diff --git a/include/hw/qdev-properties-system.h b/include/hw/qdev-properties-system.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/qdev-properties-system.h
+++ b/include/hw/qdev-properties-system.h
@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_pcie_link_speed;
 extern const PropertyInfo qdev_prop_pcie_link_width;
 extern const PropertyInfo qdev_prop_cpus390entitlement;
 extern const PropertyInfo qdev_prop_iothread_vq_mapping_list;
+extern const PropertyInfo qdev_prop_endian_mode;
 
 #define DEFINE_PROP_PCI_DEVFN(_n, _s, _f, _d)                   \
     DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_pci_devfn, int32_t)
@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_iothread_vq_mapping_list;
     DEFINE_PROP(_name, _state, _field, qdev_prop_iothread_vq_mapping_list, \
                 IOThreadVirtQueueMappingList *)
 
+#define DEFINE_PROP_ENDIAN(_name, _state, _field, _default) \
+    DEFINE_PROP_UNSIGNED(_name, _state, _field, _default, \
+                         qdev_prop_endian_mode, EndianMode)
+#define DEFINE_PROP_ENDIAN_NODEFAULT(_name, _state, _field) \
+    DEFINE_PROP_ENDIAN(_name, _state, _field, ENDIAN_MODE_UNSPECIFIED)
+
 #endif
diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/qdev-properties-system.c
+++ b/hw/core/qdev-properties-system.c
@@ -XXX,XX +XXX,XX @@ const PropertyInfo qdev_prop_iothread_vq_mapping_list = {
     .set = set_iothread_vq_mapping_list,
     .release = release_iothread_vq_mapping_list,
 };
+
+/* --- Endian modes */
+
+const PropertyInfo qdev_prop_endian_mode = {
+    .name = "EndianMode",
+    .description = "Endian mode, big/little/unspecified",
+    .enum_table = &EndianMode_lookup,
+    .get = qdev_propinfo_get_enum,
+    .set = qdev_propinfo_set_enum,
+    .set_default_value = qdev_propinfo_set_default_value_enum,
+};
-- 
2.47.1

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/intc/xilinx_intc.c                    | 60 ++++++++++++++++++------
 hw/microblaze/petalogix_ml605_mmu.c      |  1 +
 hw/microblaze/petalogix_s3adsp1800_mmu.c |  3 ++
 hw/ppc/virtex_ml507.c                    |  1 +
 hw/riscv/microblaze-v-generic.c          |  1 +
 5 files changed, 52 insertions(+), 14 deletions(-)

diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -XXX,XX +XXX,XX @@
  *
  * Copyright (c) 2009 Edgar E. Iglesias.
  *
+ * https://docs.amd.com/v/u/en-US/xps_intc
+ * DS572: LogiCORE IP XPS Interrupt Controller (v2.01a)
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qapi/error.h"
 #include "hw/sysbus.h"
 #include "qemu/module.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
 #include "qom/object.h"
 
 #define D(x)
@@ -XXX,XX +XXX,XX @@ struct XpsIntc
 {
     SysBusDevice parent_obj;
 
+    EndianMode model_endianness;
     MemoryRegion mmio;
     qemu_irq parent_irq;
 
@@ -XXX,XX +XXX,XX @@ static void pic_write(void *opaque, hwaddr addr,
     update_irq(p);
 }
 
-static const MemoryRegionOps pic_ops = {
-    .read = pic_read,
-    .write = pic_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
-    .impl = {
-        .min_access_size = 4,
-        .max_access_size = 4,
+static const MemoryRegionOps pic_ops[2] = {
+    [0 ... 1] = {
+        .read = pic_read,
+        .write = pic_write,
+        .endianness = DEVICE_BIG_ENDIAN,
+        .impl = {
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
+        .valid = {
+            /*
+             * All XPS INTC registers are accessed through the PLB interface.
+             * The base address for these registers is provided by the
+             * configuration parameter, C_BASEADDR. Each register is 32 bits
+             * although some bits may be unused and is accessed on a 4-byte
+             * boundary offset from the base address.
+             */
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
     },
-    .valid = {
-        .min_access_size = 4,
-        .max_access_size = 4
-    }
+    [ENDIAN_MODE_BIG].endianness = DEVICE_BIG_ENDIAN,
+    [ENDIAN_MODE_LITTLE].endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 static void irq_handler(void *opaque, int irq, int level)
@@ -XXX,XX +XXX,XX @@ static void xilinx_intc_init(Object *obj)
 
     qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq);
-
-    memory_region_init_io(&p->mmio, obj, &pic_ops, p, "xlnx.xps-intc",
-                          R_MAX * 4);
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio);
 }
 
+static void xilinx_intc_realize(DeviceState *dev, Error **errp)
+{
+    XpsIntc *p = XILINX_INTC(dev);
+
+    if (p->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
+        error_setg(errp, TYPE_XILINX_INTC " property 'endianness'"
+                         " must be set to 'big' or 'little'");
+        return;
+    }
+
+    memory_region_init_io(&p->mmio, OBJECT(dev),
+                          &pic_ops[p->model_endianness],
+                          p, "xlnx.xps-intc",
+                          R_MAX * 4);
+}
+
 static const Property xilinx_intc_properties[] = {
+    DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XpsIntc, model_endianness),
     DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0),
 };
 
@@ -XXX,XX +XXX,XX @@ static void xilinx_intc_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
 
+    dc->realize = xilinx_intc_realize;
     device_class_set_props(dc, xilinx_intc_properties);
 }
 
diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -XXX,XX +XXX,XX @@ petalogix_ml605_init(MachineState *machine)
 
 
     dev = qdev_new("xlnx.xps-intc");
+    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
     qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
     qemu_irq irq[32];
     MemoryRegion *sysmem = get_system_memory();
+    EndianMode endianness = TARGET_BIG_ENDIAN ? ENDIAN_MODE_BIG
+                                              : ENDIAN_MODE_LITTLE;
 
     cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
     object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort);
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
                           64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
 
     dev = qdev_new("xlnx.xps-intc");
+    qdev_prop_set_enum(dev, "endianness", endianness);
     qdev_prop_set_uint32(dev, "kind-of-intr",
                          1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ppc/virtex_ml507.c
+++ b/hw/ppc/virtex_ml507.c
@@ -XXX,XX +XXX,XX @@ static void virtex_init(MachineState *machine)
 
     cpu_irq = qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT);
     dev = qdev_new("xlnx.xps-intc");
+    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_BIG);
     qdev_prop_set_uint32(dev, "kind-of-intr", 0);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microblaze-v-generic.c
+++ b/hw/riscv/microblaze-v-generic.c
@@ -XXX,XX +XXX,XX @@ static void mb_v_generic_init(MachineState *machine)
     memory_region_add_subregion(sysmem, ddr_base, phys_ram);
 
     dev = qdev_new("xlnx.xps-intc");
+    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
     qdev_prop_set_uint32(dev, "kind-of-intr",
                          1 << UARTLITE_IRQ);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-- 
2.47.1

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/microblaze/petalogix_s3adsp1800_mmu.c |  1 +
 hw/net/xilinx_ethlite.c                  | 27 ++++++++++++++++++------
 hw/riscv/microblaze-v-generic.c          |  1 +
 3 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
 
     dev = qdev_new("xlnx.xps-ethernetlite");
+    qdev_prop_set_enum(dev, "endianness", endianness);
     qemu_configure_nic_device(dev, true, NULL);
     qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
     qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
 #include "hw/misc/unimp.h"
 #include "net/net.h"
 #include "trace.h"
@@ -XXX,XX +XXX,XX @@ struct XlnxXpsEthLite
 {
     SysBusDevice parent_obj;
 
+    EndianMode model_endianness;
     MemoryRegion container;
     qemu_irq irq;
     NICState *nic;
@@ -XXX,XX +XXX,XX @@ static void port_tx_write(void *opaque, hwaddr addr, uint64_t value,
     }
 }
 
-static const MemoryRegionOps eth_porttx_ops = {
+static const MemoryRegionOps eth_porttx_ops[2] = {
+    [0 ... 1] = {
         .read = port_tx_read,
         .write = port_tx_write,
-        .endianness = DEVICE_NATIVE_ENDIAN,
         .impl = {
             .min_access_size = 4,
             .max_access_size = 4,
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps eth_porttx_ops = {
             .min_access_size = 4,
             .max_access_size = 4,
         },
+    },
+    [ENDIAN_MODE_BIG].endianness = DEVICE_BIG_ENDIAN,
+    [ENDIAN_MODE_LITTLE].endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 static uint64_t port_rx_read(void *opaque, hwaddr addr, unsigned int size)
@@ -XXX,XX +XXX,XX @@ static void port_rx_write(void *opaque, hwaddr addr, uint64_t value,
     }
 }
 
-static const MemoryRegionOps eth_portrx_ops = {
+static const MemoryRegionOps eth_portrx_ops[2] = {
+    [0 ... 1] = {
         .read = port_rx_read,
         .write = port_rx_write,
-        .endianness = DEVICE_NATIVE_ENDIAN,
         .impl = {
             .min_access_size = 4,
             .max_access_size = 4,
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps eth_portrx_ops = {
             .min_access_size = 4,
             .max_access_size = 4,
         },
+    },
+    [ENDIAN_MODE_BIG].endianness = DEVICE_BIG_ENDIAN,
+    [ENDIAN_MODE_LITTLE].endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 static bool eth_can_rx(NetClientState *nc)
@@ -XXX,XX +XXX,XX @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
 {
     XlnxXpsEthLite *s = XILINX_ETHLITE(dev);
 
+    if (s->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
+        error_setg(errp, TYPE_XILINX_ETHLITE " property 'endianness'"
+                         " must be set to 'big' or 'little'");
+        return;
+    }
+
     memory_region_init(&s->container, OBJECT(dev),
                        "xlnx.xps-ethernetlite", 0x2000);
 
@@ -XXX,XX +XXX,XX @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
                                BUFSZ_MAX, &error_abort);
         memory_region_add_subregion(&s->container, 0x0800 * i, &s->port[i].txbuf);
         memory_region_init_io(&s->port[i].txio, OBJECT(dev),
-                              &eth_porttx_ops, s,
+                              &eth_porttx_ops[s->model_endianness], s,
                               i ? "ethlite.tx[1]io" : "ethlite.tx[0]io",
                               4 * TX_MAX);
         memory_region_add_subregion(&s->container, i ? A_TX_BASE1 : A_TX_BASE0,
@@ -XXX,XX +XXX,XX @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
         memory_region_add_subregion(&s->container, 0x1000 + 0x0800 * i,
                                     &s->port[i].rxbuf);
         memory_region_init_io(&s->port[i].rxio, OBJECT(dev),
-                              &eth_portrx_ops, s,
+                              &eth_portrx_ops[s->model_endianness], s,
                               i ? "ethlite.rx[1]io" : "ethlite.rx[0]io",
                               4 * RX_MAX);
         memory_region_add_subregion(&s->container, i ? A_RX_BASE1 : A_RX_BASE0,
@@ -XXX,XX +XXX,XX @@ static void xilinx_ethlite_init(Object *obj)
 }
 
 static const Property xilinx_ethlite_properties[] = {
+    DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XlnxXpsEthLite, model_endianness),
     DEFINE_PROP_UINT32("tx-ping-pong", XlnxXpsEthLite, c_tx_pingpong, 1),
     DEFINE_PROP_UINT32("rx-ping-pong", XlnxXpsEthLite, c_rx_pingpong, 1),
     DEFINE_NIC_PROPERTIES(XlnxXpsEthLite, conf),
diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microblaze-v-generic.c
+++ b/hw/riscv/microblaze-v-generic.c
@@ -XXX,XX +XXX,XX @@ static void mb_v_generic_init(MachineState *machine)
 
     /* Emaclite */
     dev = qdev_new("xlnx.xps-ethernetlite");
+    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
     qemu_configure_nic_device(dev, true, NULL);
     qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
     qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
-- 
2.47.1

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/microblaze/petalogix_ml605_mmu.c      |  1 +
 hw/microblaze/petalogix_s3adsp1800_mmu.c |  1 +
 hw/ppc/virtex_ml507.c                    |  1 +
 hw/riscv/microblaze-v-generic.c          |  2 ++
 hw/timer/xilinx_timer.c                  | 43 +++++++++++++++++-------
 5 files changed, 35 insertions(+), 13 deletions(-)

diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -XXX,XX +XXX,XX @@ petalogix_ml605_init(MachineState *machine)
 
     /* 2 timers at irq 2 @ 100 Mhz.  */
     dev = qdev_new("xlnx.xps-timer");
+    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
     qdev_prop_set_uint32(dev, "one-timer-only", 0);
     qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
 
     /* 2 timers at irq 2 @ 62 Mhz.  */
     dev = qdev_new("xlnx.xps-timer");
+    qdev_prop_set_enum(dev, "endianness", endianness);
     qdev_prop_set_uint32(dev, "one-timer-only", 0);
     qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ppc/virtex_ml507.c
+++ b/hw/ppc/virtex_ml507.c
@@ -XXX,XX +XXX,XX @@ static void virtex_init(MachineState *machine)
 
     /* 2 timers at irq 2 @ 62 Mhz.  */
     dev = qdev_new("xlnx.xps-timer");
+    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_BIG);
     qdev_prop_set_uint32(dev, "one-timer-only", 0);
     qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microblaze-v-generic.c
+++ b/hw/riscv/microblaze-v-generic.c
@@ -XXX,XX +XXX,XX @@ static void mb_v_generic_init(MachineState *machine)
 
     /* 2 timers at irq 0 @ 100 Mhz.  */
     dev = qdev_new("xlnx.xps-timer");
+    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
     qdev_prop_set_uint32(dev, "one-timer-only", 0);
     qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void mb_v_generic_init(MachineState *machine)
 
     /* 2 timers at irq 3 @ 100 Mhz.  */
     dev = qdev_new("xlnx.xps-timer");
+    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
     qdev_prop_set_uint32(dev, "one-timer-only", 0);
     qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/xilinx_timer.c
+++ b/hw/timer/xilinx_timer.c
@@ -XXX,XX +XXX,XX @@
  *
  * Copyright (c) 2009 Edgar E. Iglesias.
  *
+ * DS573: https://docs.amd.com/v/u/en-US/xps_timer
+ * LogiCORE IP XPS Timer/Counter (v1.02a)
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qapi/error.h"
 #include "hw/sysbus.h"
 #include "hw/irq.h"
 #include "hw/ptimer.h"
 #include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct XpsTimerState
 {
     SysBusDevice parent_obj;
 
+    EndianMode model_endianness;
     MemoryRegion mmio;
     qemu_irq irq;
     uint8_t one_timer_only;
@@ -XXX,XX +XXX,XX @@ timer_write(void *opaque, hwaddr addr,
     timer_update_irq(t);
 }
 
-static const MemoryRegionOps timer_ops = {
-    .read = timer_read,
-    .write = timer_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
-    .impl = {
-        .min_access_size = 4,
-        .max_access_size = 4,
+static const MemoryRegionOps timer_ops[2] = {
+    [0 ... 1] = {
+        .read = timer_read,
+        .write = timer_write,
+        .impl = {
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
+        .valid = {
+            .min_access_size = 4,
+            .max_access_size = 4,
+        },
     },
-    .valid = {
-        .min_access_size = 4,
-        .max_access_size = 4
-    }
+    [ENDIAN_MODE_BIG].endianness = DEVICE_BIG_ENDIAN,
+    [ENDIAN_MODE_LITTLE].endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 static void timer_hit(void *opaque)
@@ -XXX,XX +XXX,XX @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp)
     XpsTimerState *t = XILINX_TIMER(dev);
     unsigned int i;
 
+    if (t->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
+        error_setg(errp, TYPE_XILINX_TIMER " property 'endianness'"
+                         " must be set to 'big' or 'little'");
+        return;
+    }
+
     /* Init all the ptimers.  */
     t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
     for (i = 0; i < num_timers(t); i++) {
@@ -XXX,XX +XXX,XX @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp)
         ptimer_transaction_commit(xt->ptimer);
     }
 
-    memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer",
-                          R_MAX * 4 * num_timers(t));
+    memory_region_init_io(&t->mmio, OBJECT(t),
+                          &timer_ops[t->model_endianness], t,
+                          "xlnx.xps-timer", R_MAX * 4 * num_timers(t));
     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio);
 }
 
@@ -XXX,XX +XXX,XX @@ static void xilinx_timer_init(Object *obj)
 }
 
 static const Property xilinx_timer_properties[] = {
+    DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XpsTimerState, model_endianness),
     DEFINE_PROP_UINT32("clock-frequency", XpsTimerState, freq_hz, 62 * 1000000),
     DEFINE_PROP_UINT8("one-timer-only", XpsTimerState, one_timer_only, 0),
 };
-- 
2.47.1

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/char/xilinx_uartlite.c                | 34 ++++++++++++++++--------
 hw/microblaze/petalogix_s3adsp1800_mmu.c |  1 +
 hw/riscv/microblaze-v-generic.c          |  1 +
 3 files changed, 25 insertions(+), 11 deletions(-)

diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/xilinx_uartlite.c
+++ b/hw/char/xilinx_uartlite.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "qemu/log.h"
+#include "qapi/error.h"
 #include "hw/char/xilinx_uartlite.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
@@ -XXX,XX +XXX,XX @@
 struct XilinxUARTLite {
     SysBusDevice parent_obj;
 
+    EndianMode model_endianness;
     MemoryRegion mmio;
     CharBackend chr;
     qemu_irq irq;
@@ -XXX,XX +XXX,XX @@ uart_write(void *opaque, hwaddr addr,
     uart_update_irq(s);
 }
 
-static const MemoryRegionOps uart_ops = {
-    .read = uart_read,
-    .write = uart_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
-    .valid = {
-        .min_access_size = 1,
-        .max_access_size = 4
-    }
+static const MemoryRegionOps uart_ops[2] = {
+    [0 ... 1] = {
+        .read = uart_read,
+        .write = uart_write,
+        .valid = {
+            .min_access_size = 1,
+            .max_access_size = 4,
+        },
+    },
+    [ENDIAN_MODE_BIG].endianness = DEVICE_BIG_ENDIAN,
+    [ENDIAN_MODE_LITTLE].endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 static const Property xilinx_uartlite_properties[] = {
+    DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XilinxUARTLite, model_endianness),
     DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr),
 };
 
@@ -XXX,XX +XXX,XX @@ static void xilinx_uartlite_realize(DeviceState *dev, Error **errp)
 {
     XilinxUARTLite *s = XILINX_UARTLITE(dev);
 
+    if (s->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
+        error_setg(errp, TYPE_XILINX_UARTLITE " property 'endianness'"
+                         " must be set to 'big' or 'little'");
+        return;
+    }
+
+    memory_region_init_io(&s->mmio, OBJECT(dev),
+                          &uart_ops[s->model_endianness],
+                          s, "xlnx.xps-uartlite", R_MAX * 4);
     qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
                              uart_event, NULL, s, NULL, true);
 }
@@ -XXX,XX +XXX,XX @@ static void xilinx_uartlite_init(Object *obj)
     XilinxUARTLite *s = XILINX_UARTLITE(obj);
 
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
-
-    memory_region_init_io(&s->mmio, obj, &uart_ops, s,
-                          "xlnx.xps-uartlite", R_MAX * 4);
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 }
 
diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
     }
 
     dev = qdev_new(TYPE_XILINX_UARTLITE);
+    qdev_prop_set_enum(dev, "endianness", endianness);
     qdev_prop_set_chr(dev, "chardev", serial_hd(0));
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microblaze-v-generic.c
+++ b/hw/riscv/microblaze-v-generic.c
@@ -XXX,XX +XXX,XX @@ static void mb_v_generic_init(MachineState *machine)
 
     /* Uartlite */
     dev = qdev_new(TYPE_XILINX_UARTLITE);
+    qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
     qdev_prop_set_chr(dev, "chardev", serial_hd(0));
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
-- 
2.47.1

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/microblaze/petalogix_ml605_mmu.c |  1 +
 hw/ssi/xilinx_spi.c                 | 32 +++++++++++++++++++++--------
 2 files changed, 24 insertions(+), 9 deletions(-)

Avoid fetching assets from www.qemu-advent-calendar.org
website, prefer fetching microblaze assets from GitLab servers.

Suggested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 tests/functional/test_microblazeel_s3adsp1800.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

The archive used in test_microblaze_s3adsp1800.py (testing a
big-endian target) contains a big-endian kernel. Rename using
the _BE suffix.

Similarly, the archive in test_microblazeel_s3adsp1800 (testing
a little-endian target) contains a little-endian kernel. Rename
using _LE suffix.

These changes will help when adding cross-endian kernel tests.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20250206131052.30207-13-philmd@linaro.org>
---
 tests/functional/test_microblaze_s3adsp1800.py   | 6 +++---
 tests/functional/test_microblazeel_s3adsp1800.py | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

Make microblaze tests a bit more generic.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20250206131052.30207-14-philmd@linaro.org>
---
 tests/functional/test_microblaze_s3adsp1800.py   | 7 +++++--
 tests/functional/test_microblazeel_s3adsp1800.py | 7 +++++--
 2 files changed, 10 insertions(+), 4 deletions(-)

Commit f0ec14c78c4 ("tests/avocado: Fix console data loss") fixed
QEMUMachine's problem with console, we don't need to use the sleep()
kludges.

Suggested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250206131052.30207-15-philmd@linaro.org>
---
 tests/functional/test_microblazeel_s3adsp1800.py | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py
index XXXXXXX..XXXXXXX 100755
--- a/tests/functional/test_microblazeel_s3adsp1800.py
+++ b/tests/functional/test_microblazeel_s3adsp1800.py
@@ -XXX,XX +XXX,XX @@
 # This work is licensed under the terms of the GNU GPL, version 2 or
 # later. See the COPYING file in the top-level directory.
 
-import time
-from qemu_test import exec_command, exec_command_and_wait_for_pattern
+from qemu_test import exec_command_and_wait_for_pattern
 from qemu_test import QemuSystemTest, Asset
 from qemu_test import wait_for_console_pattern
 
@@ -XXX,XX +XXX,XX @@ def do_xmaton_le_test(self, machine):
         self.vm.add_args('-nic', f'user,tftp={tftproot}')
         self.vm.launch()
         wait_for_console_pattern(self, 'QEMU Advent Calendar 2023')
-        time.sleep(0.1)
-        exec_command(self, 'root')
-        time.sleep(0.1)
+        wait_for_console_pattern(self, 'buildroot login:')
+        exec_command_and_wait_for_pattern(self, 'root', '#')
         exec_command_and_wait_for_pattern(self,
                 'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png',
                 '821cd3cab8efd16ad6ee5acc3642a8ea')
-- 
2.47.1

Have the MicroblazeMachine class being common to both
MicroblazeBigEndianMachine and MicroblazeLittleEndianMachine
classes. Move the xmaton and ballerina tests to the parent class.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20250206131052.30207-16-philmd@linaro.org>
---
 .../functional/test_microblaze_s3adsp1800.py  | 24 +++++++++++++++
 .../test_microblazeel_s3adsp1800.py           | 30 ++-----------------
 2 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py
index XXXXXXX..XXXXXXX 100755
--- a/tests/functional/test_microblaze_s3adsp1800.py
+++ b/tests/functional/test_microblaze_s3adsp1800.py
@@ -XXX,XX +XXX,XX @@
 # This work is licensed under the terms of the GNU GPL, version 2 or
 # later. See the COPYING file in the top-level directory.
 
+from qemu_test import exec_command_and_wait_for_pattern
 from qemu_test import QemuSystemTest, Asset
 from qemu_test import wait_for_console_pattern
 
@@ -XXX,XX +XXX,XX @@ class MicroblazeMachine(QemuSystemTest):
          'day17.tar.xz'),
         '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057')
 
+    ASSET_IMAGE_LE = Asset(
+        ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/'
+         'day05.tar.xz'),
+        'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22')
+
     def do_ballerina_be_test(self, machine):
         self.set_machine(machine)
         self.archive_extract(self.ASSET_IMAGE_BE)
@@ -XXX,XX +XXX,XX @@ def do_ballerina_be_test(self, machine):
         # message, that's why we don't test for a later string here. This
         # needs some investigation by a microblaze wizard one day...
 
+    def do_xmaton_le_test(self, machine):
+        self.require_netdev('user')
+        self.set_machine(machine)
+        self.archive_extract(self.ASSET_IMAGE_LE)
+        self.vm.set_console()
+        self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin'))
+        tftproot = self.scratch_file('day13')
+        self.vm.add_args('-nic', f'user,tftp={tftproot}')
+        self.vm.launch()
+        wait_for_console_pattern(self, 'QEMU Advent Calendar 2023')
+        wait_for_console_pattern(self, 'buildroot login:')
+        exec_command_and_wait_for_pattern(self, 'root', '#')
+        exec_command_and_wait_for_pattern(self,
+                'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png',
+                '821cd3cab8efd16ad6ee5acc3642a8ea')
+
+class MicroblazeBigEndianMachine(MicroblazeMachine):
+
     def test_microblaze_s3adsp1800_legacy_be(self):
         self.do_ballerina_be_test('petalogix-s3adsp1800')
 
diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py
index XXXXXXX..XXXXXXX 100755
--- a/tests/functional/test_microblazeel_s3adsp1800.py
+++ b/tests/functional/test_microblazeel_s3adsp1800.py
@@ -XXX,XX +XXX,XX @@
 # This work is licensed under the terms of the GNU GPL, version 2 or
 # later. See the COPYING file in the top-level directory.
 
-from qemu_test import exec_command_and_wait_for_pattern
-from qemu_test import QemuSystemTest, Asset
-from qemu_test import wait_for_console_pattern
+from qemu_test import QemuSystemTest
 
+from test_microblaze_s3adsp1800 import MicroblazeMachine
 
-class MicroblazeelMachine(QemuSystemTest):
-
-    timeout = 90
-
-    ASSET_IMAGE_LE = Asset(
-        ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/'
-         'day05.tar.xz'),
-        'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22')
-
-    def do_xmaton_le_test(self, machine):
-        self.require_netdev('user')
-        self.set_machine(machine)
-        self.archive_extract(self.ASSET_IMAGE_LE)
-        self.vm.set_console()
-        self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin'))
-        tftproot = self.scratch_file('day13')
-        self.vm.add_args('-nic', f'user,tftp={tftproot}')
-        self.vm.launch()
-        wait_for_console_pattern(self, 'QEMU Advent Calendar 2023')
-        wait_for_console_pattern(self, 'buildroot login:')
-        exec_command_and_wait_for_pattern(self, 'root', '#')
-        exec_command_and_wait_for_pattern(self,
-                'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png',
-                '821cd3cab8efd16ad6ee5acc3642a8ea')
+class MicroblazeLittleEndianMachine(MicroblazeMachine):
 
     def test_microblaze_s3adsp1800_legacy_le(self):
         self.do_xmaton_le_test('petalogix-s3adsp1800')
-- 
2.47.1