The following changes since commit 11b8920ed2093848f79f93d106afe8a69a61a523:

Merge tag 'pull-request-2024-11-04' of https://gitlab.com/thuth/qemu into staging (2024-11-04 17:37:59 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241105

for you to fetch changes up to 374cdc8efe4a039510cca47e8399d54a1aeb4f2d:

target/arm: Enable FEAT_CMOW for -cpu max (2024-11-05 10:10:00 +0000)

* Fix MMU indexes for AArch32 Secure PL1&0 in a less complex and buggy way

* Fix SVE SDOT/UDOT/USDOT (4-way, indexed)

* softfloat: set 2-operand NaN propagation rule at runtime

* disas: Fix build against Capstone v6 (again)

* hw/rtc/ds1338: Trace send and receive operations

* hw/timer/imx_gpt: Convert DPRINTF to trace events

* hw/watchdog/wdt_imx2: Remove redundant assignment

* hw/sensor/tmp105: Convert printf() to trace event, add tracing for read/write access

* hw/net/npcm_gmac: Change error log to trace event

* target/arm: Enable FEAT_CMOW for -cpu max

Bernhard Beschow (4):

hw/rtc/ds1338: Trace send and receive operations

hw/timer/imx_gpt: Convert DPRINTF to trace events

hw/watchdog/wdt_imx2: Remove redundant assignment

hw/sensor/tmp105: Convert printf() to trace event, add tracing for read/write access

Gustavo Romero (1):

target/arm: Enable FEAT_CMOW for -cpu max

Nabih Estefan (1):

hw/net/npcm_gmac: Change error log to trace event

Peter Maydell (24):

softfloat: Allow 2-operand NaN propagation rule to be set at runtime

tests/fp: Explicitly set 2-NaN propagation rule

target/arm: Explicitly set 2-NaN propagation rule

target/mips: Explicitly set 2-NaN propagation rule

target/loongarch: Explicitly set 2-NaN propagation rule

target/hppa: Explicitly set 2-NaN propagation rule

target/s390x: Explicitly set 2-NaN propagation rule

target/ppc: Explicitly set 2-NaN propagation rule

target/m68k: Explicitly set 2-NaN propagation rule

target/m68k: Initialize float_status fields in gdb set/get functions

target/sparc: Move cpu_put_fsr(env, 0) call to reset

target/sparc: Explicitly set 2-NaN propagation rule

target/xtensa: Factor out calls to set_use_first_nan()

target/xtensa: Explicitly set 2-NaN propagation rule

target/i386: Set 2-NaN propagation rule explicitly

target/alpha: Explicitly set 2-NaN propagation rule

target/microblaze: Move setting of float rounding mode to reset

target/microblaze: Explicitly set 2-NaN propagation rule

target/openrisc: Explicitly set 2-NaN propagation rule

target/rx: Explicitly set 2-NaN propagation rule

softfloat: Remove fallback rule from pickNaN()

Revert "target/arm: Fix usage of MMU indexes when EL3 is AArch32"

target/arm: Add new MMU indexes for AArch32 Secure PL1&0

target/arm: Fix SVE SDOT/UDOT/USDOT (4-way, indexed)

Richard Henderson (1):

disas: Fix build against Capstone v6 (again)

docs/system/arm/emulation.rst | 1 +

meson.build | 1 +

hw/sensor/trace.h | 1 +

include/disas/capstone.h | 1 +

include/fpu/softfloat-helpers.h | 11 +++

include/fpu/softfloat-types.h | 38 ++++++++++

target/arm/cpu-features.h | 5 ++

target/arm/cpu.h | 49 ++++++------

target/arm/internals.h | 41 +++++-----

target/arm/tcg/translate.h | 2 -

target/i386/cpu.h | 3 +

target/mips/fpu_helper.h | 22 ++++++

target/xtensa/cpu.h | 6 ++

hw/net/npcm_gmac.c | 5 +-

hw/rtc/ds1338.c | 6 ++

hw/sensor/tmp105.c | 7 +-

hw/timer/imx_gpt.c | 18 ++---

hw/watchdog/wdt_imx2.c | 1 -

linux-user/arm/nwfpe/fpa11.c | 18 +++++

target/alpha/cpu.c | 11 +++

target/arm/cpu.c | 25 ++++--

target/arm/helper.c | 73 ++++++++++++------

target/arm/ptw.c | 10 +--

target/arm/tcg/cpu64.c | 1 +

target/arm/tcg/hflags.c | 4 -

target/arm/tcg/op_helper.c | 14 +++-

target/arm/tcg/translate-a64.c | 2 +-

target/arm/tcg/translate.c | 12 +--

target/arm/tcg/vec_helper.c | 9 ++-

target/hppa/fpu_helper.c | 6 ++

target/i386/cpu.c | 4 +

target/i386/tcg/fpu_helper.c | 40 ++++++++++

target/loongarch/tcg/fpu_helper.c | 1 +

target/m68k/cpu.c | 16 ++++

target/m68k/fpu_helper.c | 1 +

target/m68k/helper.c | 4 +-

target/microblaze/cpu.c | 10 ++-

target/mips/cpu.c | 2 +-

target/mips/msa.c | 17 +++++

target/openrisc/cpu.c | 6 ++

target/ppc/cpu_init.c | 8 ++

target/rx/cpu.c | 7 ++

target/s390x/cpu.c | 1 +

target/sparc/cpu.c | 10 ++-

target/sparc/fop_helper.c | 10 ++-

target/xtensa/cpu.c | 2 +-

target/xtensa/fpu_helper.c | 35 +++++----

tests/fp/fp-bench.c | 2 +

tests/fp/fp-test-log2.c | 1 +

tests/fp/fp-test.c | 2 +

fpu/softfloat-specialize.c.inc | 156 ++++++++++++++------------------------

hw/net/trace-events | 1 +

hw/rtc/trace-events | 4 +

hw/sensor/trace-events | 6 ++

hw/timer/trace-events | 6 ++

55 files changed, 516 insertions(+), 239 deletions(-)

create mode 100644 hw/sensor/trace.h

create mode 100644 hw/sensor/trace-events

From: Bernhard Beschow <shentey@gmail.com>

The same statement is executed unconditionally right before the if statement.

Cc: Guenter Roeck <linux@roeck-us.net>

Reviewed-by: Guenter Roeck <linux@roeck-us.net>

Signed-off-by: Bernhard Beschow <shentey@gmail.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20241103143330.123596-4-shentey@gmail.com

hw/watchdog/wdt_imx2.c | 1 -

1 file changed, 1 deletion(-)

diff --git a/hw/watchdog/wdt_imx2.c b/hw/watchdog/wdt_imx2.c

--- a/hw/watchdog/wdt_imx2.c

+++ b/hw/watchdog/wdt_imx2.c

@@ -XXX,XX +XXX,XX @@ static void imx2_wdt_expired(void *opaque)

/* Perform watchdog action if watchdog is enabled */

if (s->wcr & IMX2_WDT_WCR_WDE) {

- s->wrsr = IMX2_WDT_WRSR_TOUT;

watchdog_perform_action();

}

}

From: Bernhard Beschow <shentey@gmail.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Signed-off-by: Bernhard Beschow <shentey@gmail.com>

Message-id: 20241103143330.123596-3-shentey@gmail.com

hw/timer/imx_gpt.c | 18 +++++-------------

hw/timer/trace-events | 6 ++++++

2 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c

--- a/hw/timer/imx_gpt.c

+++ b/hw/timer/imx_gpt.c

@@ -XXX,XX +XXX,XX @@

#include "migration/vmstate.h"

#include "qemu/module.h"

#include "qemu/log.h"

+#include "trace.h"

#ifndef DEBUG_IMX_GPT

#define DEBUG_IMX_GPT 0

#endif

-#define DPRINTF(fmt, args...) \

- do { \

- if (DEBUG_IMX_GPT) { \

- fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPT, \

- __func__, ##args); \

- } \

- } while (0)

-

static const char *imx_gpt_reg_name(uint32_t reg)

{

switch (reg) {

@@ -XXX,XX +XXX,XX @@ static void imx_gpt_set_freq(IMXGPTState *s)

s->freq = imx_ccm_get_clock_frequency(s->ccm,

s->clocks[clksrc]) / (1 + s->pr);

- DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, s->freq);

+ trace_imx_gpt_set_freq(clksrc, s->freq);

if (s->freq) {

ptimer_set_freq(s->timer, s->freq);

@@ -XXX,XX +XXX,XX @@ static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size)

break;

- DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(offset >> 2), reg_value);

+ trace_imx_gpt_read(imx_gpt_reg_name(offset >> 2), reg_value);

return reg_value;

}

@@ -XXX,XX +XXX,XX @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,

IMXGPTState *s = IMX_GPT(opaque);

uint32_t oldreg;

- DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(offset >> 2),

- (uint32_t)value);

+ trace_imx_gpt_write(imx_gpt_reg_name(offset >> 2), (uint32_t)value);

switch (offset >> 2) {

case 0:

@@ -XXX,XX +XXX,XX @@ static void imx_gpt_timeout(void *opaque)

{

IMXGPTState *s = IMX_GPT(opaque);

- DPRINTF("\n");

+ trace_imx_gpt_timeout();

s->sr |= s->next_int;

s->next_int = 0;

diff --git a/hw/timer/trace-events b/hw/timer/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/timer/trace-events

+++ b/hw/timer/trace-events

@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK A

cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB dualtimer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"

cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"

+# imx_gpt.c

+imx_gpt_set_freq(uint32_t clksrc, uint32_t freq) "Setting clksrc %u to %u Hz"

+imx_gpt_read(const char *name, uint64_t value) "%s -> 0x%08" PRIx64

+imx_gpt_write(const char *name, uint64_t value) "%s <- 0x%08" PRIx64

+imx_gpt_timeout(void) ""

+

# npcm7xx_timer.c

npcm7xx_timer_read(const char *id, uint64_t offset, uint64_t value) " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64

npcm7xx_timer_write(const char *id, uint64_t offset, uint64_t value) "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64

From: Nabih Estefan <nabihestefan@google.com>

Convert the LOG_GUEST_ERROR for the "tx descriptor is owned

by software" to a trace message. This condition is normal

when there is there is nothing to transmit, and we would

otherwise spam the logs with it in that situation.

Signed-off-by: Nabih Estefan <nabihestefan@google.com>

Signed-off-by: Roque Arcudia Hernandez <roqueh@google.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Message-id: 20241014184847.1594056-1-roqueh@google.com

[PMM: tweaked commit message]

hw/net/npcm_gmac.c | 5 ++---

hw/net/trace-events | 1 +

2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c

--- a/hw/net/npcm_gmac.c

+++ b/hw/net/npcm_gmac.c

@@ -XXX,XX +XXX,XX @@ static void gmac_try_send_next_packet(NPCMGMACState *gmac)

/* 1 = DMA Owned, 0 = Software Owned */

if (!(tx_desc.tdes0 & TX_DESC_TDES0_OWN)) {

- qemu_log_mask(LOG_GUEST_ERROR,

- "TX Descriptor @ 0x%x is owned by software\n",

- desc_addr);

+ trace_npcm_gmac_tx_desc_owner(DEVICE(gmac)->canonical_path,

+ desc_addr);

gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_TU;

gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT,

NPCM_DMA_STATUS_TX_SUSPENDED_STATE);

diff --git a/hw/net/trace-events b/hw/net/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/net/trace-events

+++ b/hw/net/trace-events

@@ -XXX,XX +XXX,XX @@ npcm_gmac_packet_received(const char* name, uint32_t len) "%s: Reception finishe

npcm_gmac_packet_sent(const char* name, uint16_t len) "%s: TX packet sent!, length: 0x%04" PRIX16

npcm_gmac_debug_desc_data(const char* name, void* addr, uint32_t des0, uint32_t des1, uint32_t des2, uint32_t des3)"%s: Address: %p Descriptor 0: 0x%04" PRIX32 " Descriptor 1: 0x%04" PRIX32 "Descriptor 2: 0x%04" PRIX32 " Descriptor 3: 0x%04" PRIX32

npcm_gmac_packet_tx_desc_data(const char* name, uint32_t tdes0, uint32_t tdes1) "%s: Tdes0: 0x%04" PRIX32 " Tdes1: 0x%04" PRIX32

+npcm_gmac_tx_desc_owner(const char* name, uint32_t desc_addr) "%s: TX Descriptor @0x%04" PRIX32 " is owned by software"

# npcm_pcs.c

npcm_pcs_reg_read(const char *name, uint16_t indirect_access_baes, uint64_t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 " value: 0x%04" PRIx16

From: Bernhard Beschow <shentey@gmail.com>

printf() unconditionally prints to the console which disturbs `-serial stdio`.

Fix that by converting into a trace event. While at it, add some tracing for

read and write access.

Fixes: 7e7c5e4c1ba5 "Nokia N800 machine support (ARM)."

Signed-off-by: Bernhard Beschow <shentey@gmail.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Message-id: 20241103143330.123596-5-shentey@gmail.com

meson.build | 1 +

hw/sensor/trace.h | 1 +

hw/sensor/tmp105.c | 7 ++++++-

hw/sensor/trace-events | 6 ++++++

4 files changed, 14 insertions(+), 1 deletion(-)

create mode 100644 hw/sensor/trace.h

create mode 100644 hw/sensor/trace-events

diff --git a/meson.build b/meson.build

--- a/meson.build

+++ b/meson.build

@@ -XXX,XX +XXX,XX @@ if have_system

'hw/s390x',

'hw/scsi',

'hw/sd',

+ 'hw/sensor',

'hw/sh4',

'hw/sparc',

'hw/sparc64',

diff --git a/hw/sensor/trace.h b/hw/sensor/trace.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/sensor/trace.h

@@ -0,0 +1 @@

+#include "trace/trace-hw_sensor.h"

diff --git a/hw/sensor/tmp105.c b/hw/sensor/tmp105.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/sensor/tmp105.c

+++ b/hw/sensor/tmp105.c

@@ -XXX,XX +XXX,XX @@

#include "qapi/visitor.h"

#include "qemu/module.h"

#include "hw/registerfields.h"

+#include "trace.h"

FIELD(CONFIG, SHUTDOWN_MODE, 0, 1)

FIELD(CONFIG, THERMOSTAT_MODE, 1, 1)

@@ -XXX,XX +XXX,XX @@ static void tmp105_read(TMP105State *s)

s->buf[s->len++] = ((uint16_t) s->limit[1]) >> 0;

break;

}

+

+ trace_tmp105_read(s->i2c.address, s->pointer);

}

static void tmp105_write(TMP105State *s)

{

+ trace_tmp105_write(s->i2c.address, s->pointer);

+

switch (s->pointer & 3) {

case TMP105_REG_TEMPERATURE:

break;

case TMP105_REG_CONFIG:

if (FIELD_EX8(s->buf[0] & ~s->config, CONFIG, SHUTDOWN_MODE)) {

- printf("%s: TMP105 shutdown\n", __func__);

+ trace_tmp105_write_shutdown(s->i2c.address);

}

s->config = FIELD_DP8(s->buf[0], CONFIG, ONE_SHOT, 0);

s->faults = tmp105_faultq[FIELD_EX8(s->config, CONFIG, FAULT_QUEUE)];

diff --git a/hw/sensor/trace-events b/hw/sensor/trace-events

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/sensor/trace-events

@@ -XXX,XX +XXX,XX @@

+# See docs/devel/tracing.rst for syntax documentation.

+

+# tmp105.c

+tmp105_read(uint8_t dev, uint8_t addr) "device: 0x%02x, addr: 0x%02x"

+tmp105_write(uint8_t dev, uint8_t addr) "device: 0x%02x, addr 0x%02x"

+tmp105_write_shutdown(uint8_t dev) "device: 0x%02x"

Currently we call cpu_put_fsr(0) in sparc_cpu_realizefn(), which

initializes various fields in the CPU struct:

* fsr_cexc_ftt

* fcc[]

* fsr_qne

* fsr

It also sets the rounding mode in env->fp_status.

This is largely pointless, because when we later reset the CPU

this will zero out all the fields up until the "end_reset_fields"

label, which includes all of these (but not fp_status!)

Move the cpu_put_fsr(env, 0) call to reset, because that expresses

the logical requirement: we want to reset FSR to 0 on every reset.

This isn't a behaviour change because the fields are all zero anyway.

target/sparc/cpu.c | 2 +-

diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c

--- a/target/sparc/cpu.c

+++ b/target/sparc/cpu.c

@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_reset_hold(Object *obj, ResetType type)

env->npc = env->pc + 4;

#endif

env->cache_control = 0;

+ cpu_put_fsr(env, 0);

}

#ifndef CONFIG_USER_ONLY

@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)

env->version |= env->def.maxtl << 8;

env->version |= env->def.nwindows - 1;

#endif

- cpu_put_fsr(env, 0);

cpu_exec_realizefn(cs, &local_err);

if (local_err != NULL) {

From: Bernhard Beschow <shentey@gmail.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Signed-off-by: Bernhard Beschow <shentey@gmail.com>

Message-id: 20241103143330.123596-2-shentey@gmail.com

hw/rtc/ds1338.c | 6 ++++++

hw/rtc/trace-events | 4 ++++

2 files changed, 10 insertions(+)

diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c

--- a/hw/rtc/ds1338.c

+++ b/hw/rtc/ds1338.c

@@ -XXX,XX +XXX,XX @@

#include "qemu/module.h"

#include "qom/object.h"

#include "sysemu/rtc.h"

+#include "trace.h"

/* Size of NVRAM including both the user-accessible area and the

* secondary register area.

@@ -XXX,XX +XXX,XX @@ static uint8_t ds1338_recv(I2CSlave *i2c)

uint8_t res;

res = s->nvram[s->ptr];

+

+ trace_ds1338_recv(s->ptr, res);

+

inc_regptr(s);

return res;

}

@@ -XXX,XX +XXX,XX @@ static int ds1338_send(I2CSlave *i2c, uint8_t data)

{

DS1338State *s = DS1338(i2c);

+ trace_ds1338_send(s->ptr, data);

+

if (s->addr_byte) {

s->ptr = data & (NVRAM_SIZE - 1);

s->addr_byte = false;

diff --git a/hw/rtc/trace-events b/hw/rtc/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/rtc/trace-events

+++ b/hw/rtc/trace-events

@@ -XXX,XX +XXX,XX @@ pl031_set_alarm(uint32_t ticks) "alarm set for %u ticks"

aspeed_rtc_read(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64

aspeed_rtc_write(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64

+# ds1338.c

+ds1338_recv(uint32_t addr, uint8_t value) "[0x%" PRIx32 "] -> 0x%02" PRIx8

+ds1338_send(uint32_t addr, uint8_t value) "[0x%" PRIx32 "] <- 0x%02" PRIx8

+

# m48t59.c

m48txx_nvram_io_read(uint64_t addr, uint64_t value) "io read addr:0x%04" PRIx64 " value:0x%02" PRIx64

m48txx_nvram_io_write(uint64_t addr, uint64_t value) "io write addr:0x%04" PRIx64 " value:0x%02" PRIx64

IEEE 758 does not define a fixed rule for which NaN to pick as the

result if both operands of a 2-operand operation are NaNs. As a

result different architectures have ended up with different rules for

propagating NaNs.

QEMU currently hardcodes the NaN propagation logic into the binary

because pickNaN() has an ifdef ladder for different targets. We want

to make the propagation rule instead be selectable at runtime,

because:

* this will let us have multiple targets in one QEMU binary

* the Arm FEAT_AFP architectural feature includes letting

the guest select a NaN propagation rule at runtime

* x86 specifies different propagation rules for x87 FPU ops

and for SSE ops, and specifying the rule in the float_status

would let us emulate this, instead of wrongly using the

x87 rules everywhere

In this commit we add an enum for the propagation rule, the field in

float_status, and the corresponding getters and setters. We change

pickNaN to honour this, but because all targets still leave this

field at its default 0 value, the fallback logic will pick the rule

type with the old ifdef ladder.

It's valid not to set a propagation rule if default_nan_mode is

enabled, because in that case there's no need to pick a NaN; all the

callers of pickNaN() catch this case and skip calling it. So we can

already assert that we don't get into the "no rule defined" codepath

for our four targets which always set default_nan_mode: Hexagon,

RiscV, SH4 and Tricore, and for the one target which does not have FP

at all: avr. These targets will not need to be updated to call

set_float_2nan_prop_rule().

Message-id: 20241025141254.2141506-2-peter.maydell@linaro.org

include/fpu/softfloat-helpers.h | 11 ++

include/fpu/softfloat-types.h | 42 ++++++

fpu/softfloat-specialize.c.inc | 229 ++++++++++++++++++--------------

3 files changed, 185 insertions(+), 97 deletions(-)

diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h

--- a/include/fpu/softfloat-helpers.h

+++ b/include/fpu/softfloat-helpers.h

@@ -XXX,XX +XXX,XX @@ static inline void set_floatx80_rounding_precision(FloatX80RoundPrec val,

status->floatx80_rounding_precision = val;

+static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,

+ float_status *status)

+{

+ status->float_2nan_prop_rule = rule;

+}

+

static inline void set_flush_to_zero(bool val, float_status *status)

{

status->flush_to_zero = val;

@@ -XXX,XX +XXX,XX @@ get_floatx80_rounding_precision(float_status *status)

return status->floatx80_rounding_precision;

}

+static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)

+{

+ return status->float_2nan_prop_rule;

+}

+

static inline bool get_flush_to_zero(float_status *status)

{

return status->flush_to_zero;

diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h

index XXXXXXX..XXXXXXX 100644

--- a/include/fpu/softfloat-types.h

+++ b/include/fpu/softfloat-types.h

@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {

floatx80_precision_s,

} FloatX80RoundPrec;

+/*

+ * 2-input NaN propagation rule. Individual architectures have

+ * different rules for which input NaN is propagated to the output

+ * when there is more than one NaN on the input.

+ *

+ * If default_nan_mode is enabled then it is valid not to set a

+ * NaN propagation rule, because the softfloat code guarantees

+ * not to try to pick a NaN to propagate in default NaN mode.

+ *

+ * For transition, currently the 'none' rule will cause us to

+ * fall back to picking the propagation rule based on the existing

+ * ifdef ladder. When all targets are converted it will be an error

+ * not to set the rule in float_status unless in default_nan_mode,

+ * and we will assert if we need to handle an input NaN and no

+ * rule was selected.

+ */

+typedef enum __attribute__((__packed__)) {

+ /* No propagation rule specified */

+ float_2nan_prop_none = 0,

+ /* Prefer SNaN over QNaN, then operand A over B */

+ float_2nan_prop_s_ab,

+ /* Prefer SNaN over QNaN, then operand B over A */

+ float_2nan_prop_s_ba,

+ /* Prefer A over B regardless of SNaN vs QNaN */

+ float_2nan_prop_ab,

+ /* Prefer B over A regardless of SNaN vs QNaN */

+ float_2nan_prop_ba,

+ /*

+ * This implements x87 NaN propagation rules:

+ * SNaN + QNaN => return the QNaN

+ * two SNaNs => return the one with the larger significand, silenced

+ * two QNaNs => return the one with the larger significand

+ * SNaN and a non-NaN => return the SNaN, silenced

+ * QNaN and a non-NaN => return the QNaN

+ *

+ * If we get down to comparing significands and they are the same,

+ * return the NaN with the positive sign bit (if any).

+ */

+ float_2nan_prop_x87,

+} Float2NaNPropRule;

+

/*

* Floating Point Status. Individual architectures may maintain

* several versions of float_status for different functions. The

@@ -XXX,XX +XXX,XX @@ typedef struct float_status {

uint16_t float_exception_flags;

FloatRoundMode float_rounding_mode;

FloatX80RoundPrec floatx80_rounding_precision;

+ Float2NaNPropRule float_2nan_prop_rule;

bool tininess_before_rounding;

/* should denormalised results go to zero and set the inexact flag? */

bool flush_to_zero;

diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/fpu/softfloat-specialize.c.inc

+++ b/fpu/softfloat-specialize.c.inc

@@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status)

static int pickNaN(FloatClass a_cls, FloatClass b_cls,

bool aIsLargerSignificand, float_status *status)

{

-#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) || \

- defined(TARGET_LOONGARCH64) || defined(TARGET_S390X)

- /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take

- * the first of:

- * 1. A if it is signaling

- * 2. B if it is signaling

- * 3. A (quiet)

- * 4. B (quiet)

- * A signaling NaN is always quietened before returning it.

- */

- /* According to MIPS specifications, if one of the two operands is

- * a sNaN, a new qNaN has to be generated. This is done in

- * floatXX_silence_nan(). For qNaN inputs the specifications

- * says: "When possible, this QNaN result is one of the operand QNaN

- * values." In practice it seems that most implementations choose

- * the first operand if both operands are qNaN. In short this gives

- * the following rules:

- * 1. A if it is signaling

- * 2. B if it is signaling

- * 3. A (quiet)

- * 4. B (quiet)

- * A signaling NaN is always silenced before returning it.

- */

- if (is_snan(a_cls)) {

- return 0;

- } else if (is_snan(b_cls)) {

- return 1;

- } else if (is_qnan(a_cls)) {

- return 0;

- } else {

- return 1;

- }

-#elif defined(TARGET_PPC) || defined(TARGET_M68K)

- /* PowerPC propagation rules:

- * 1. A if it sNaN or qNaN

- * 2. B if it sNaN or qNaN

- * A signaling NaN is always silenced before returning it.

- */

- /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL

- * 3.4 FLOATING-POINT INSTRUCTION DETAILS

- * If either operand, but not both operands, of an operation is a

- * nonsignaling NaN, then that NaN is returned as the result. If both

- * operands are nonsignaling NaNs, then the destination operand

- * nonsignaling NaN is returned as the result.

- * If either operand to an operation is a signaling NaN (SNaN), then the

- * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit

- * is set in the FPCR ENABLE byte, then the exception is taken and the

- * destination is not modified. If the SNaN exception enable bit is not

- * set, setting the SNaN bit in the operand to a one converts the SNaN to

- * a nonsignaling NaN. The operation then continues as described in the

- * preceding paragraph for nonsignaling NaNs.

- */

- if (is_nan(a_cls)) {

- return 0;

- } else {

- return 1;

- }

-#elif defined(TARGET_SPARC)

- /* Prefer SNaN over QNaN, order B then A. */

- if (is_snan(b_cls)) {

- return 1;

- } else if (is_snan(a_cls)) {

- return 0;

- } else if (is_qnan(b_cls)) {

- return 1;

-#elif defined(TARGET_XTENSA)

+ Float2NaNPropRule rule = status->float_2nan_prop_rule;

+

/*

- * Xtensa has two NaN propagation modes.

- * Which one is active is controlled by float_status::use_first_nan.

+ * We guarantee not to require the target to tell us how to

+ * pick a NaN if we're always returning the default NaN.

*/

- if (status->use_first_nan) {

+ assert(!status->default_nan_mode);

+

+ if (rule == float_2nan_prop_none) {

+ /* target didn't set the rule: fall back to old ifdef choices */

+#if defined(TARGET_AVR) || defined(TARGET_HEXAGON) \

+ || defined(TARGET_RISCV) || defined(TARGET_SH4) \

+ || defined(TARGET_TRICORE)

+ g_assert_not_reached();

+#elif defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) || \

+ defined(TARGET_LOONGARCH64) || defined(TARGET_S390X)

+ /*

+ * ARM mandated NaN propagation rules (see FPProcessNaNs()), take

+ * the first of:

+ * 1. A if it is signaling

+ * 2. B if it is signaling

+ * 3. A (quiet)

+ * 4. B (quiet)

+ * A signaling NaN is always quietened before returning it.

+ */

+ /*

+ * According to MIPS specifications, if one of the two operands is

+ * a sNaN, a new qNaN has to be generated. This is done in

+ * floatXX_silence_nan(). For qNaN inputs the specifications

+ * says: "When possible, this QNaN result is one of the operand QNaN

+ * values." In practice it seems that most implementations choose

+ * the first operand if both operands are qNaN. In short this gives

+ * the following rules:

+ * 1. A if it is signaling

+ * 2. B if it is signaling

+ * 3. A (quiet)

+ * 4. B (quiet)

+ * A signaling NaN is always silenced before returning it.

+ */

+ rule = float_2nan_prop_s_ab;

+#elif defined(TARGET_PPC) || defined(TARGET_M68K)

+ /*

+ * PowerPC propagation rules:

+ * 1. A if it sNaN or qNaN

+ * 2. B if it sNaN or qNaN

+ * A signaling NaN is always silenced before returning it.

+ */

+ /*

+ * M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL

+ * 3.4 FLOATING-POINT INSTRUCTION DETAILS

+ * If either operand, but not both operands, of an operation is a

+ * nonsignaling NaN, then that NaN is returned as the result. If both

+ * operands are nonsignaling NaNs, then the destination operand

+ * nonsignaling NaN is returned as the result.

+ * If either operand to an operation is a signaling NaN (SNaN), then the

+ * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit

+ * is set in the FPCR ENABLE byte, then the exception is taken and the

+ * destination is not modified. If the SNaN exception enable bit is not

+ * set, setting the SNaN bit in the operand to a one converts the SNaN to

+ * a nonsignaling NaN. The operation then continues as described in the

+ * preceding paragraph for nonsignaling NaNs.

+ */

+ rule = float_2nan_prop_ab;

+#elif defined(TARGET_SPARC)

+ /* Prefer SNaN over QNaN, order B then A. */

+ rule = float_2nan_prop_s_ba;

+#elif defined(TARGET_XTENSA)

+ /*

+ * Xtensa has two NaN propagation modes.

+ * Which one is active is controlled by float_status::use_first_nan.

+ */

+ if (status->use_first_nan) {

+ rule = float_2nan_prop_ab;

+ rule = float_2nan_prop_ba;

+#else

+ rule = float_2nan_prop_x87;

+#endif

+ }

+

+ switch (rule) {

+ case float_2nan_prop_s_ab:

+ if (is_snan(a_cls)) {

+ return 0;

+ } else if (is_snan(b_cls)) {

+ return 1;

+ } else if (is_qnan(a_cls)) {

+ return 0;

+ return 1;

+ break;

+ case float_2nan_prop_s_ba:

+ if (is_snan(b_cls)) {

+ return 1;

+ } else if (is_snan(a_cls)) {

+ return 0;

+ } else if (is_qnan(b_cls)) {

+ return 1;

+ return 0;

+ break;

+ case float_2nan_prop_ab:

if (is_nan(a_cls)) {

return 0;

} else {

return 1;

}

- } else {

+ break;

+ case float_2nan_prop_ba:

if (is_nan(b_cls)) {

return 1;

} else {

return 0;

}

- }

-#else

- /* This implements x87 NaN propagation rules:

- * SNaN + QNaN => return the QNaN

- * two SNaNs => return the one with the larger significand, silenced

- * two QNaNs => return the one with the larger significand

- * SNaN and a non-NaN => return the SNaN, silenced

- * QNaN and a non-NaN => return the QNaN

- *

- * If we get down to comparing significands and they are the same,

- * return the NaN with the positive sign bit (if any).

- */

- if (is_snan(a_cls)) {

- if (is_snan(b_cls)) {

- return aIsLargerSignificand ? 0 : 1;

- }

- return is_qnan(b_cls) ? 1 : 0;

- } else if (is_qnan(a_cls)) {

- if (is_snan(b_cls) || !is_qnan(b_cls)) {

- return 0;

+ break;

+ case float_2nan_prop_x87:

+ /*

+ * This implements x87 NaN propagation rules:

+ * SNaN + QNaN => return the QNaN

+ * two SNaNs => return the one with the larger significand, silenced

+ * two QNaNs => return the one with the larger significand

+ * SNaN and a non-NaN => return the SNaN, silenced

+ * QNaN and a non-NaN => return the QNaN

+ *

+ * If we get down to comparing significands and they are the same,

+ * return the NaN with the positive sign bit (if any).

+ */

+ if (is_snan(a_cls)) {

+ if (is_snan(b_cls)) {

+ return aIsLargerSignificand ? 0 : 1;

+ }

+ return is_qnan(b_cls) ? 1 : 0;

+ } else if (is_qnan(a_cls)) {

+ if (is_snan(b_cls) || !is_qnan(b_cls)) {

+ return 0;

+ } else {

+ return aIsLargerSignificand ? 0 : 1;

+ }

} else {

- return aIsLargerSignificand ? 0 : 1;

+ return 1;

}

- } else {

- return 1;

+ default:

+ g_assert_not_reached();

}

-#endif

}

/*----------------------------------------------------------------------------