[RFC PATCH v2 0/1] Sbsa-ref CXL Enablement
[RFC PATCH v4 0/1] Sbsa-ref CXL Enablement
1
v3 -> v4:
2
- based on 'cxl/cxl-host: Support creation of a new CXL Host Bridge'[1]
3
- Align base addresses of CXL relevant Windows
4
- Remove redundant header files
5
6
v2 -> v3:
7
- create a new host bridge type: TYPE_SBSA_CXL_HOST
8
- CXL exclusive ECAM, PIO, MMIO32 & MMIO64 space in sbsa-ref
9
- combine all cxl infrastructure creating into one function
10
1
v1 -> v2:
11
v1 -> v2:
2
- provide CXL exclusive MMIO32 & MMIO64 space
12
- provide CXL exclusive MMIO32 & MMIO64 space
3
- hard coded two cxl root ports
13
- hard coded two cxl root ports
4
14
5
RFC because
15
RFC because
6
- Many contents are ported from Jonathan' patch on qemu virt design
16
- Many contents are ported from Jonathan' patch on qemu virt design
7
17
8
- Less experience and not particularly confident in sbsa-ref address space design
18
- Less experience and not particularly confident in sbsa-ref address space design
9
so this might be stupidly broken in a way I've not considered.
19
so this might be stupidly broken in a way I've not considered.
10
20
11
Currently the base CXL support for arm platforms is only on Jonathan's patches[1]
21
Background
22
==========
23
Currently the base CXL support for arm platforms is only on Jonathan's patches[2]
12
which have not yet merged into upstream. SBSA-REF can be more like a real machine,
24
which have not yet merged into upstream. SBSA-REF can be more like a real machine,
13
thus the support of cxl could be meaningful.
25
thus my initial purpose is to support the simplest cxl VH topology on sbsa-ref to
26
verify the basic cxl function usage, therefore, some real machine could refer the
27
cxl running result on sbsa-ref.
14
28
15
This series leverages Jonathan's patches[1] to design [SBSA_CXL_HOST] and
29
This series leverages Jonathan's patches to design [SBSA_CXL_CHBCR] and
16
[SBSA_CXL_FIXED_WINDOW] spaces for sbsa-ref layout.
30
[SBSA_CXL_FIXED_WINDOW] spaces for sbsa-ref layout.
17
31
18
For [SBSA_CXL_HOST], since this creates a default pxb-cxl (bus_nr=0xc0) bridge
32
Regard to the burden of edk2 firmware, I try to build a static CEDT table and add
19
with two cxl root ports on sbsa-ref, the new memory layout places 64K space for
33
acpi0016, acpi0017 and other cxl relevant contents into acpi tables[3][4]. Hence it
20
one hard coded cxl host bridge register regions in the sbsa-ref memmap.
34
doesn't need to communicate cxl contents via DT to edk2.
21
35
22
According to above design, for now only two cxl type3 devices could be added on
36
CXL HOST design
23
the cxl host.
37
===============
38
In previous version, the pxb-cxl-host with any cxl root ports and cxl endpoint devices
39
would occupy the BDF number of the original pcie domain resulting in the max available
40
pcie devices on sbsa-ref would decrease, which seems to bring a series of trouble. With
41
this patch[1], sbsa-ref could use the new cxl host bridge type (TYPE_CXL_HOST) to
42
avoid above problem.
24
43
25
With the 'create_pxb_cxl', users don't need to input '-device pxb-cxl' and
44
For [SBSA_CXL_CHBCR], this creates a default cxl host bridge (0001:00) with two cxl root
26
'-device cxl-rp' parameters.
45
ports on sbsa-ref, and the new memory layout places 64K space for one hard coded cxl host
46
bridge register regions in the sbsa-ref memmap. It means for now only two cxl type3
47
devices could be added on the cxl host, but personally it could satisfy my initial purpose
48
mentioned above.
27
49
28
In addition, this support indepentent mmio32(32M) & mmio64(1M) space which are
50
And the memory layout provides separate space windows for the cxl host bridge in the
29
enough for cxl components, because in this way the previous pcie mmio32/64 space
51
sbsa-ref memmap:
30
would not be divided and affected.
52
- 64K CXL Host Bridge Component Registers (CHBCR)
53
- 64K CXL_PIO
54
- 128M CXL_MMIO
55
- 256M CXL_ECAM
56
- 4G CXL_MMIO_HIGH
31
57
32
However, with the pxb-cxl-host, any cxl root ports and cxl endpoint devices would
58
CXL FIXED WINDOW design
33
occupy the BDF number of the original pcie domain. Hence, the max available pcie
59
=======================
34
devices on sbsa-ref would decrease, which seems to bring a series of trouble.
35
I'm looking for some comments on the problems and suggestions on if there are better
36
ways to do it.
37
38
For [SBSA_CXL_FIXED_WINDOW], in order to provide CFMWs on sbsa-ref, this extends 1TB
60
For [SBSA_CXL_FIXED_WINDOW], in order to provide CFMWs on sbsa-ref, this extends 1TB
39
space from the hole above RAM Memory [SBSA_MEM] for CXL Fixed Memory Window.
61
space from the hole above RAM Memory [SBSA_MEM] for CXL Fixed Memory Window.
62
- 1T CXL_FIXED_WINDOW
63
40
0xA0000000000 is chosen as the base address of this space because of 3 reasons:
64
0xA0000000000 is chosen as the base address of this space because of 3 reasons:
41
42
1) It is more suitable to choose a static address instead of that
65
1) It is more suitable to choose a static address instead of that
43
implementation in virt, since a dynamic address space layout of
66
implementation in virt, since a dynamic address space layout of
44
sbsa-ref is not appropriate for its original purpose as a reference
67
sbsa-ref is not appropriate for its original purpose as a reference
45
platform.
68
platform.
46
69
...
...
49
It is satisfied the requirements of memory hotplug in linux kernel.
72
It is satisfied the requirements of memory hotplug in linux kernel.
50
73
51
3) The start pfn of CFMW should exceed the reserved_pfn_range for
74
3) The start pfn of CFMW should exceed the reserved_pfn_range for
52
onlined numa node.
75
onlined numa node.
53
76
54
Based on 'cxl_fmws_link_targets', this adds a new function
77
Usage of cxl on sbsa-ref
55
'sbsa_cxl_fmws_link_targets' for binding cfmws.target with the default
78
========================
56
pxb-cxl-bus on sbsa-ref.
79
With the 'create_cxl' and 'create_cxl_fixed_window', users don't need to input
57
80
'-device pxb-cxl' , '-device cxl-rp' and '-M cxl-fmw' parameters.
58
In addition, this also adds 'create_cxl_fixed_window_region' to support
59
creating a static cfmw region on sbsa-ref, so users don't need to input
60
'-M cxl-fmw' parameter.
61
81
62
Thus, to run sbsa-ref with a cxl device could use:
82
Thus, to run sbsa-ref with a cxl device could use:
63
qemu-system-aarch64 \
83
qemu-system-aarch64 \
64
-object memory-backend-file,id=mem2,mem-path=/tmp/mem2,size=256M,share=true \
84
-object memory-backend-file,id=mem2,mem-path=/tmp/mem2,size=256M,share=true \
65
-device cxl-type3,bus=cxl.0,volatile-memdev=mem2,id=cxl-mem1 \
85
-device cxl-type3,bus=cxl.0,volatile-memdev=mem2,id=cxl-mem1 \
66
86
67
By the way, since the matched firmware correspond to this patch would allocate
87
Incompatibility problem
68
pcie bus 0xc0 ~ 0xff to pxb-cxl-host, we should add "bus=pcie.0" when we want
88
=======================
69
to plug some devices on the original pcie bus, for example:
89
Although the new cxl host bridge has been separated from the original pcie host, the
90
incompatibility problem of "-device qemu-xhci" is not resolved. Because the new device
91
to plug by qemu command would be enumerated at the largest domain(0001), for example,
92
if we add "-device qemu-xhci" to boot sbsa-ref with cxl, the lspci would show:
93
94
root@ubuntu-jammy-arm64:~# lspci
95
0000:00:00.0 Host bridge: Red Hat, Inc. QEMU PCIe Host bridge
96
0000:00:01.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection
97
0000:00:02.0 Display controller: Device 1234:1111 (rev 02)
98
0001:00:00.0 PCI bridge: Intel Corporation Device 7075
99
0001:00:01.0 PCI bridge: Intel Corporation Device 7075
100
0001:00:02.0 USB controller: Red Hat, Inc. QEMU XHCI Host Controller (rev 01)
101
0001:01:00.0 CXL: Intel Corporation Device 0d93 (rev 01)
102
103
root@ubuntu-jammy-arm64:~# lspci -tv
104
-+-[0001:00]-+-00.0-[01]----00.0 Intel Corporation Device 0d93
105
| +-01.0-[02]--
106
| \-02.0 Red Hat, Inc. QEMU XHCI Host Controller
107
\-[0000:00]-+-00.0 Red Hat, Inc. QEMU PCIe Host bridge
108
+-01.0 Intel Corporation 82574L Gigabit Network Connection
109
\-02.0 Device 1234:1111
110
111
Hence we should add "bus=pcie.0" when we want to plug some devices on the original
112
pcie bus, for example:
70
-device qemu-xhci,bus=pcie.0 \
113
-device qemu-xhci,bus=pcie.0 \
71
or
114
or
72
-device nvme,serial=deadbeef,bus=pcie.0,drive=hdd \
115
-device nvme,serial=deadbeef,bus=pcie.0,drive=hdd \
73
-drive file=../disk/hdd.qcow2,format=qcow2,id=hdd,if=none \
116
-drive file=../disk/hdd.qcow2,format=qcow2,id=hdd,if=none \
74
117
118
So the result is:
119
root@ubuntu-jammy-arm64:~# lspci
120
0000:00:00.0 Host bridge: Red Hat, Inc. QEMU PCIe Host bridge
121
0000:00:01.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection
122
0000:00:02.0 Display controller: Device 1234:1111 (rev 02)
123
0000:00:03.0 USB controller: Red Hat, Inc. QEMU XHCI Host Controller (rev 01)
124
0001:00:00.0 PCI bridge: Intel Corporation Device 7075
125
0001:00:01.0 PCI bridge: Intel Corporation Device 7075
126
0001:01:00.0 CXL: Intel Corporation Device 0d93 (rev 01)
127
128
root@ubuntu-jammy-arm64:~# lspci -tv
129
-+-[0001:00]-+-00.0-[01]----00.0 Intel Corporation Device 0d93
130
| \-01.0-[02]--
131
\-[0000:00]-+-00.0 Red Hat, Inc. QEMU PCIe Host bridge
132
+-01.0 Intel Corporation 82574L Gigabit Network Connection
133
+-02.0 Device 1234:1111
134
\-03.0 Red Hat, Inc. QEMU XHCI Host Controller
135
136
I am looking for suggestions on if there are better ways to do it.
137
75
This series patches are here to hopefully some comments to guide me!
138
This series patches are here to hopefully some comments to guide me!
76
139
77
Link:
140
Link:
78
[1]: https://lore.kernel.org/linux-cxl/20220616141950.23374-1-Jonathan.Cameron@huawei.com/
141
[1]: https://lists.nongnu.org/archive/html/qemu-arm/2024-12/msg00350.html
79
[2]: https://edk2.groups.io/g/devel/topic/rfc_edk2_patch_v3_0_1/109403423#
142
[2]: https://lore.kernel.org/linux-cxl/20220616141950.23374-1-Jonathan.Cameron@huawei.com/
80
[3]: https://edk2.groups.io/g/devel/topic/rfc_patch_edk2_platforms_v2/109403456
143
[3]: https://edk2.groups.io/g/devel/message/120851
144
[4]: https://edk2.groups.io/g/devel/topic/rfc_patch_edk2_platforms_v4/110023229
81
145
82
Yuquan Wang (1):
146
Yuquan Wang (1):
83
hw/arm/sbsa-ref: Support CXL Host Bridge & CFMW
147
hw/arm/sbsa-ref: Support CXL Host Bridge & CFMW
84
148
85
docs/system/arm/sbsa.rst | 4 ++
149
docs/system/arm/sbsa.rst | 4 ++
86
hw/arm/sbsa-ref.c | 122 +++++++++++++++++++++++++++++++++++++-
150
hw/arm/sbsa-ref.c | 135 ++++++++++++++++++++++++++++++++++++++-
87
hw/cxl/cxl-host-stubs.c | 2 +
151
2 files changed, 138 insertions(+), 1 deletion(-)
88
hw/cxl/cxl-host.c | 2 +-
89
include/hw/cxl/cxl_host.h | 2 +
90
5 files changed, 130 insertions(+), 2 deletions(-)
91
152
92
--
153
--
93
2.34.1
154
2.34.1
diff view generated by jsdifflib
[RFC PATCH v2 1/1] hw/arm/sbsa-ref: Support CXL Host Bridge & CFMW
[RFC PATCH v4 1/1] hw/arm/sbsa-ref: Support CXL Host Bridge & CFMW
1
This creates a default pxb-cxl (bus_nr=0xc0) bridge with two
1
This creates a specific cxl host bridge (0001:00) with two cxl
2
cxl root ports on sbsa-ref. And the memory layout places 64K
2
root ports on sbsa-ref. And the memory layout provides separate
3
space for the cxl host bridge register regions(CHBCR) in the
3
space windows for the cxl host bridge in the sbsa-ref memmap:
4
sbsa-ref memmap.
4
5
5
- 64K CXL Host Bridge Component Registers (CHBCR)
6
In addition, this support indepentent mmio32(32M) & mmio64(1M)
6
- 64K CXL_PIO
7
space for cxl components.
7
- 128M CXL_MMIO
8
- 256M CXL_ECAM
9
- 4G CXL_MMIO_HIGH
8
10
9
To provide CFMWs on sbsa-ref, this extends 1TB space from the
11
To provide CFMWs on sbsa-ref, this extends 1TB space from the
10
hole above RAM Memory [SBSA_MEM] for CXL Fixed Memory Window.
12
hole above RAM Memory [SBSA_MEM] for CXL Fixed Memory Window:
13
14
- 1T CXL_FIXED_WINDOW
11
15
12
Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn>
16
Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn>
13
---
17
---
14
docs/system/arm/sbsa.rst | 4 ++
18
docs/system/arm/sbsa.rst | 4 ++
15
hw/arm/sbsa-ref.c | 122 +++++++++++++++++++++++++++++++++++++-
19
hw/arm/sbsa-ref.c | 135 ++++++++++++++++++++++++++++++++++++++-
16
hw/cxl/cxl-host-stubs.c | 2 +
20
2 files changed, 138 insertions(+), 1 deletion(-)
17
hw/cxl/cxl-host.c | 2 +-
18
include/hw/cxl/cxl_host.h | 2 +
19
5 files changed, 130 insertions(+), 2 deletions(-)
20
21
21
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
22
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
22
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
23
--- a/docs/system/arm/sbsa.rst
24
--- a/docs/system/arm/sbsa.rst
24
+++ b/docs/system/arm/sbsa.rst
25
+++ b/docs/system/arm/sbsa.rst
...
...
50
#include "hw/ide/ide-bus.h"
51
#include "hw/ide/ide-bus.h"
51
#include "hw/ide/ahci-sysbus.h"
52
#include "hw/ide/ahci-sysbus.h"
52
#include "hw/intc/arm_gicv3_common.h"
53
#include "hw/intc/arm_gicv3_common.h"
53
#include "hw/intc/arm_gicv3_its_common.h"
54
#include "hw/intc/arm_gicv3_its_common.h"
54
#include "hw/loader.h"
55
#include "hw/loader.h"
55
+#include "hw/pci/pci_bridge.h"
56
+#include "hw/pci/pci_bus.h"
57
+#include "hw/pci/pcie_port.h"
56
+#include "hw/pci/pcie_port.h"
58
#include "hw/pci-host/gpex.h"
57
#include "hw/pci-host/gpex.h"
59
+#include "hw/pci-bridge/pci_expander_bridge.h"
60
#include "hw/qdev-properties.h"
58
#include "hw/qdev-properties.h"
61
#include "hw/usb.h"
59
#include "hw/usb.h"
62
#include "hw/usb/xhci.h"
63
@@ -XXX,XX +XXX,XX @@ enum {
60
@@ -XXX,XX +XXX,XX @@ enum {
64
SBSA_SECURE_MEM,
61
SBSA_SECURE_MEM,
65
SBSA_AHCI,
62
SBSA_AHCI,
66
SBSA_XHCI,
63
SBSA_XHCI,
67
+ SBSA_CXL_HOST,
64
+ SBSA_CXL,
65
+ SBSA_CXL_CHBCR,
68
+ SBSA_CXL_MMIO,
66
+ SBSA_CXL_MMIO,
69
+ SBSA_CXL_MMIO_HIGH,
67
+ SBSA_CXL_MMIO_HIGH,
68
+ SBSA_CXL_PIO,
69
+ SBSA_CXL_ECAM,
70
+ SBSA_CXL_FIXED_WINDOW,
70
+ SBSA_CXL_FIXED_WINDOW,
71
};
71
};
72
72
73
struct SBSAMachineState {
73
struct SBSAMachineState {
74
@@ -XXX,XX +XXX,XX @@ struct SBSAMachineState {
74
@@ -XXX,XX +XXX,XX @@ struct SBSAMachineState {
75
int psci_conduit;
75
int psci_conduit;
76
DeviceState *gic;
76
DeviceState *gic;
77
PFlashCFI01 *flash[2];
77
PFlashCFI01 *flash[2];
78
+ CXLState cxl_devices_state;
78
+ CXLState cxl_devices_state;
79
+ PCIBus *cxlbus;
79
};
80
};
81
80
82
#define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
81
#define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
83
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sbsa_ref_memmap[] = {
82
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sbsa_ref_memmap[] = {
84
/* Space here reserved for more SMMUs */
83
/* Space here reserved for more SMMUs */
85
[SBSA_AHCI] = { 0x60100000, 0x00010000 },
84
[SBSA_AHCI] = { 0x60100000, 0x00010000 },
86
[SBSA_XHCI] = { 0x60110000, 0x00010000 },
85
[SBSA_XHCI] = { 0x60110000, 0x00010000 },
87
+ /* 64KiB CXL Host Bridge Registers space */
86
+ /* 64K CXL Host Bridge Registers space */
88
+ [SBSA_CXL_HOST] = { 0x60120000, 0x00010000 },
87
+ [SBSA_CXL_CHBCR] = { 0x60200000, 0x00010000 },
89
+ /* 32M CXL 32-bit MMIO space */
88
+ /* 64K CXL PIO space */
90
+ [SBSA_CXL_MMIO] = { 0x60130000, 0x02000000 },
89
+ [SBSA_CXL_PIO] = { 0x60300000, 0x00010000 },
90
+ /* 128M CXL 32-bit MMIO space */
91
+ [SBSA_CXL_MMIO] = { 0x60400000, 0x08000000 },
92
+ /* 256M CXL ECAM space */
93
+ [SBSA_CXL_ECAM] = { 0x68500000, 0x10000000 },
91
/* Space here reserved for other devices */
94
/* Space here reserved for other devices */
92
[SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 },
95
[SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 },
93
/* 32-bit address PCIE MMIO space */
96
/* 32-bit address PCIE MMIO space */
94
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sbsa_ref_memmap[] = {
97
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sbsa_ref_memmap[] = {
95
/* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */
98
/* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */
96
[SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL },
99
[SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL },
97
[SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES },
100
[SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES },
98
+ /* 1M CXL 64-bit MMIO space */
101
+ /* 4G CXL 64-bit MMIO space */
99
+ [SBSA_CXL_MMIO_HIGH] = { 0x90000000000ULL, 0x00100000 },
102
+ [SBSA_CXL_MMIO_HIGH] = { 0x90000000000ULL, 0x100000000ULL },
100
+ /* 1TB CXL FIXED WINDOW space */
103
+ /* 1TB CXL FIXED WINDOW space */
101
+ [SBSA_CXL_FIXED_WINDOW] = { 0xA0000000000ULL, 0x10000000000ULL },
104
+ [SBSA_CXL_FIXED_WINDOW] = { 0xA0000000000ULL, 0x10000000000ULL },
102
};
105
};
103
106
104
static const int sbsa_ref_irqmap[] = {
107
static const int sbsa_ref_irqmap[] = {
108
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
109
[SBSA_XHCI] = 11,
110
[SBSA_SMMU] = 12, /* ... to 15 */
111
[SBSA_GWDT_WS0] = 16,
112
+ [SBSA_CXL] = 17, /* ... to 20 */
113
};
114
115
static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
105
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
116
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
106
* fw compatibility.
117
* fw compatibility.
107
*/
118
*/
108
qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
119
qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
109
- qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 4);
120
- qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 4);
...
...
113
int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
124
int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
114
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
125
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
115
}
126
}
116
}
127
}
117
128
118
+static void create_pxb_cxl(SBSAMachineState *sms, PCIBus *bus)
129
+static void create_cxl_fixed_window(SBSAMachineState *sms,
130
+ MemoryRegion *mem, CXLHostBridge *host)
119
+{
131
+{
120
+ DeviceState *qdev = qdev_new(TYPE_PXB_CXL_DEV);
132
+ PCIBus *cxlbus = PCI_HOST_BRIDGE(host)->bus;
121
+ PCIDevice *dev = PCI_DEVICE(qdev);
133
+ char *cxl_host = object_get_canonical_path(OBJECT(cxlbus));
122
+ CXLHost *host;
123
+ PCIHostState *cxl;
124
+ PCIDevice *cxlrp;
125
+ PCIEPort *p;
126
+ PCIESlot *s;
127
+ int i;
128
+
129
+ sms->cxl_devices_state.is_enabled = true;
130
+ qdev_prop_set_uint32(qdev, "bus_nr", 0xc0);
131
+ pci_realize_and_unref(dev, bus, &error_fatal);
132
+
133
+ host = PXB_CXL_DEV(dev)->cxl_host_bridge;
134
+ cxl = PCI_HOST_BRIDGE(host);
135
+ sms->cxlbus = cxl->bus;
136
+
137
+ for (i = 0; i < 2; i++) {
138
+ cxlrp = pci_new(-1, "cxl-rp");
139
+ p = PCIE_PORT(cxlrp);
140
+ s = PCIE_SLOT(cxlrp);
141
+ p->port = i;
142
+ s->slot = i;
143
+ pci_realize_and_unref(cxlrp, sms->cxlbus, &error_fatal);
144
+ }
145
+}
146
+
147
static void create_pcie(SBSAMachineState *sms)
148
{
149
hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
150
@@ -XXX,XX +XXX,XX @@ static void create_pcie(SBSAMachineState *sms)
151
hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base;
152
hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size;
153
hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base;
154
+ hwaddr cxl_base_mmio = sbsa_ref_memmap[SBSA_CXL_MMIO].base;
155
+ hwaddr cxl_size_mmio = sbsa_ref_memmap[SBSA_CXL_MMIO].size;
156
+ hwaddr cxl_base_mmio_high = sbsa_ref_memmap[SBSA_CXL_MMIO_HIGH].base;
157
+ hwaddr cxl_size_mmio_high = sbsa_ref_memmap[SBSA_CXL_MMIO_HIGH].size;
158
int irq = sbsa_ref_irqmap[SBSA_PCIE];
159
MachineClass *mc = MACHINE_GET_CLASS(sms);
160
MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg;
161
@@ -XXX,XX +XXX,XX @@ static void create_pcie(SBSAMachineState *sms)
162
pci_create_simple(pci->bus, -1, "bochs-display");
163
164
create_smmu(sms, pci->bus);
165
+
166
+ /* Map CXL MMIO space */
167
+ mmio_alias = g_new0(MemoryRegion, 1);
168
+ mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
169
+ memory_region_init_alias(mmio_alias, OBJECT(dev), "cxl-mmio",
170
+ mmio_reg, cxl_base_mmio, cxl_size_mmio);
171
+ memory_region_add_subregion(get_system_memory(), cxl_base_mmio, mmio_alias);
172
+
173
+ /* Map CXL MMIO_HIGH space */
174
+ mmio_alias_high = g_new0(MemoryRegion, 1);
175
+ memory_region_init_alias(mmio_alias_high, OBJECT(dev), "cxl-mmio-high",
176
+ mmio_reg, cxl_base_mmio_high, cxl_size_mmio_high);
177
+ memory_region_add_subregion(get_system_memory(), cxl_base_mmio_high,
178
+ mmio_alias_high);
179
+
180
+ create_pxb_cxl(sms, pci->bus);
181
+}
182
+
183
+static void create_cxl_host_reg_region(SBSAMachineState *sms)
184
+{
185
+ MemoryRegion *sysmem = get_system_memory();
186
+ MemoryRegion *mr = &sms->cxl_devices_state.host_mr;
187
+
188
+ memory_region_init(mr, OBJECT(sms), "cxl_host_reg",
189
+ sbsa_ref_memmap[SBSA_CXL_HOST].size);
190
+ memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_CXL_HOST].base, mr);
191
+}
192
+
193
+static void create_cxl_fixed_window_region(SBSAMachineState *sms,
194
+ MemoryRegion *mem)
195
+{
196
+ char *cxl_host = object_get_canonical_path(OBJECT(sms->cxlbus));
197
+ hwaddr base = sbsa_ref_memmap[SBSA_CXL_FIXED_WINDOW].base;
134
+ hwaddr base = sbsa_ref_memmap[SBSA_CXL_FIXED_WINDOW].base;
198
+ GList *it;
135
+ GList *it;
199
+ strList host_target = { NULL, cxl_host };
136
+ strList host_target = { NULL, cxl_host };
200
+ CXLFixedMemoryWindowOptions sbsa_ref_cfmwoptions = {
137
+ CXLFixedMemoryWindowOptions sbsa_ref_cfmwoptions = {
201
+ .size = 1 * TiB,
138
+ .size = 1 * TiB,
202
+ .has_interleave_granularity = false,
139
+ .has_interleave_granularity = false,
203
+ .targets = &host_target,
140
+ .targets = &host_target,
204
+ };
141
+ };
205
+ CXLFixedWindow *fw;
142
+ CXLFixedWindow *fw;
206
+
143
+
207
+ cxl_fixed_memory_window_config(&sms->cxl_devices_state,
144
+ cxl_fixed_memory_window_config(&sms->cxl_devices_state,
208
+ &sbsa_ref_cfmwoptions, &error_fatal);
145
+ &sbsa_ref_cfmwoptions, &error_fatal);
209
+
146
+
210
+ it = sms->cxl_devices_state.fixed_windows;
147
+ it = sms->cxl_devices_state.fixed_windows;
211
+ fw = it->data;
148
+ fw = it->data;
212
+ fw->base = base;
149
+ fw->base = base;
150
+ fw->target_chb[0] = host;
151
+
213
+ memory_region_init_io(&fw->mr, OBJECT(sms), &cfmws_ops, fw,
152
+ memory_region_init_io(&fw->mr, OBJECT(sms), &cfmws_ops, fw,
214
+ "cxl-fixed-memory-region", fw->size);
153
+ "cxl-fixed-memory-region", fw->size);
215
+
154
+
216
+ memory_region_add_subregion(mem, fw->base, &fw->mr);
155
+ memory_region_add_subregion(mem, fw->base, &fw->mr);
217
+}
156
+}
218
+
157
+
219
+static void sbsa_cxl_fmws_link_targets(SBSAMachineState *sms,
158
+static void create_cxl(SBSAMachineState *sms)
220
+ Error **errp)
221
+{
159
+{
222
+ GList *it = sms->cxl_devices_state.fixed_windows;
160
+ hwaddr base_pio = sbsa_ref_memmap[SBSA_CXL_PIO].base;
223
+ CXLFixedWindow *fw = it->data;
161
+ int irq = sbsa_ref_irqmap[SBSA_CXL];
224
+
162
+ MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg;
225
+ fw->target_hbs[0] = PXB_CXL_DEV(pci_bridge_get_device(sms->cxlbus));
163
+ MemoryRegion *ecam_alias, *ecam_reg;
226
}
164
+ MemoryRegion *sysmem = get_system_memory();
227
165
+ MemoryRegion *chbcr = &sms->cxl_devices_state.host_mr;
228
static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size)
166
+ DeviceState *dev;
167
+ CXLHostBridge *host;
168
+ PCIHostState *cxl;
169
+ PCIDevice *cxlrp;
170
+ PCIEPort *p;
171
+ PCIESlot *s;
172
+ int i;
173
+
174
+ dev = qdev_new(TYPE_CXL_HOST);
175
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
176
+ sms->cxl_devices_state.is_enabled = true;
177
+
178
+ /* Map CXL ECAM space */
179
+ ecam_alias = g_new0(MemoryRegion, 1);
180
+ ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
181
+ memory_region_init_alias(ecam_alias, OBJECT(dev), "cxl-ecam",
182
+ ecam_reg, 0, sbsa_ref_memmap[SBSA_CXL_ECAM].size);
183
+ memory_region_add_subregion(get_system_memory(),
184
+ sbsa_ref_memmap[SBSA_CXL_ECAM].base, ecam_alias);
185
+
186
+ /* Map CXL MMIO space */
187
+ mmio_alias = g_new0(MemoryRegion, 1);
188
+ mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 2);
189
+ memory_region_init_alias(mmio_alias, OBJECT(dev), "cxl-mmio",
190
+ mmio_reg, sbsa_ref_memmap[SBSA_CXL_MMIO].base,
191
+ sbsa_ref_memmap[SBSA_CXL_MMIO].size);
192
+ memory_region_add_subregion(get_system_memory(),
193
+ sbsa_ref_memmap[SBSA_CXL_MMIO].base, mmio_alias);
194
+
195
+ /* Map CXL MMIO_HIGH space */
196
+ mmio_alias_high = g_new0(MemoryRegion, 1);
197
+ memory_region_init_alias(mmio_alias_high, OBJECT(dev), "cxl-mmio-high",
198
+ mmio_reg, sbsa_ref_memmap[SBSA_CXL_MMIO_HIGH].base,
199
+ sbsa_ref_memmap[SBSA_CXL_MMIO_HIGH].size);
200
+ memory_region_add_subregion(get_system_memory(),
201
+ sbsa_ref_memmap[SBSA_CXL_MMIO_HIGH].base, mmio_alias_high);
202
+
203
+ /* Map CXL IO port space */
204
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 3, base_pio);
205
+
206
+ for (i = 0; i < CXL_HOST_NUM_IRQS; i++) {
207
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
208
+ qdev_get_gpio_in(sms->gic, irq + i));
209
+ cxl_host_set_irq_num(CXL_HOST(dev), i, irq + i);
210
+ }
211
+
212
+ /* Map CXL CHBCR space */
213
+ memory_region_init(chbcr, OBJECT(sms), "cxl_host_reg",
214
+ sbsa_ref_memmap[SBSA_CXL_CHBCR].size);
215
+ memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_CXL_CHBCR].base,
216
+ chbcr);
217
+
218
+ cxl = PCI_HOST_BRIDGE(dev);
219
+
220
+ /* Connect two cxl root ports */
221
+ for (i = 0; i < 2; i++) {
222
+ cxlrp = pci_new(-1, "cxl-rp");
223
+ p = PCIE_PORT(cxlrp);
224
+ s = PCIE_SLOT(cxlrp);
225
+ p->port = i;
226
+ s->slot = i;
227
+ pci_realize_and_unref(cxlrp, cxl->bus, &error_fatal);
228
+ }
229
+
230
+ host = CXL_HOST(dev);
231
+ cxl_host_hook_up_registers(&sms->cxl_devices_state, host, &error_fatal);
232
+
233
+ create_cxl_fixed_window(sms, sysmem, host);
234
+}
235
+
236
static void create_pcie(SBSAMachineState *sms)
237
{
238
hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
229
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
239
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
230
240
231
create_pcie(sms);
241
create_pcie(sms);
232
242
233
+ create_cxl_host_reg_region(sms);
243
+ create_cxl(sms);
234
+ create_cxl_fixed_window_region(sms, sysmem);
235
+ pxb_cxl_hook_up_registers(&sms->cxl_devices_state, sms->cxlbus,
236
+ &error_fatal);
237
+ sbsa_cxl_fmws_link_targets(sms, &error_fatal);
238
+
244
+
239
create_secure_ec(secure_sysmem);
245
create_secure_ec(secure_sysmem);
240
246
241
sms->bootinfo.ram_size = machine->ram_size;
247
sms->bootinfo.ram_size = machine->ram_size;
242
diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c
243
index XXXXXXX..XXXXXXX 100644
244
--- a/hw/cxl/cxl-host-stubs.c
245
+++ b/hw/cxl/cxl-host-stubs.c
246
@@ -XXX,XX +XXX,XX @@
247
void cxl_fmws_link_targets(CXLState *stat, Error **errp) {};
248
void cxl_machine_init(Object *obj, CXLState *state) {};
249
void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp) {};
250
+void cxl_fixed_memory_window_config(CXLState *cxl_state,
251
+ CXLFixedMemoryWindowOptions *object, Error **errp) {};
252
253
const MemoryRegionOps cfmws_ops;
254
diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
255
index XXXXXXX..XXXXXXX 100644
256
--- a/hw/cxl/cxl-host.c
257
+++ b/hw/cxl/cxl-host.c
258
@@ -XXX,XX +XXX,XX @@
259
#include "hw/pci/pcie_port.h"
260
#include "hw/pci-bridge/pci_expander_bridge.h"
261
262
-static void cxl_fixed_memory_window_config(CXLState *cxl_state,
263
+void cxl_fixed_memory_window_config(CXLState *cxl_state,
264
CXLFixedMemoryWindowOptions *object,
265
Error **errp)
266
{
267
diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h
268
index XXXXXXX..XXXXXXX 100644
269
--- a/include/hw/cxl/cxl_host.h
270
+++ b/include/hw/cxl/cxl_host.h
271
@@ -XXX,XX +XXX,XX @@
272
void cxl_machine_init(Object *obj, CXLState *state);
273
void cxl_fmws_link_targets(CXLState *stat, Error **errp);
274
void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp);
275
+void cxl_fixed_memory_window_config(CXLState *cxl_state,
276
+ CXLFixedMemoryWindowOptions *object, Error **errp);
277
278
extern const MemoryRegionOps cfmws_ops;
279
280
--
248
--
281
2.34.1
249
2.34.1
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