hw/riscv/riscv-iommu: Coverity fixes

[PATCH 2/2] hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check

Posted by Daniel Henrique Barboza 2 weeks, 5 days ago

'mode' will never be RISCV_IOMMU_CAP_SV32. We are erroring out in the
'switch' right before it if 'mode' isn't 0, 8, 9 or 10.

'mode' should be check with RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32.

Reported by Coverity via a "DEADCODE" ticket.

Resolves: Coverity CID 1564781
Fixes: 0c54acb8243 ("hw/riscv: add RISC-V IOMMU base emulation")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 hw/riscv/riscv-iommu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 05341ad20b..dd102b3c70 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -803,7 +803,7 @@ static bool riscv_iommu_validate_process_ctx(RISCVIOMMUState *s,
     }
 
     if (ctx->tc & RISCV_IOMMU_DC_TC_SXL) {
-        if (mode == RISCV_IOMMU_CAP_SV32 &&
+        if (mode == RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32 &&
             !(s->cap & RISCV_IOMMU_CAP_SV32)) {
                 return false;
         }
-- 
2.45.2

Re: [PATCH 2/2] hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check

Posted by Alistair Francis 2 weeks, 4 days ago

On Mon, Nov 4, 2024 at 10:40 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> 'mode' will never be RISCV_IOMMU_CAP_SV32. We are erroring out in the
> 'switch' right before it if 'mode' isn't 0, 8, 9 or 10.
>
> 'mode' should be check with RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32.
>
> Reported by Coverity via a "DEADCODE" ticket.
>
> Resolves: Coverity CID 1564781
> Fixes: 0c54acb8243 ("hw/riscv: add RISC-V IOMMU base emulation")
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/riscv-iommu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index 05341ad20b..dd102b3c70 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -803,7 +803,7 @@ static bool riscv_iommu_validate_process_ctx(RISCVIOMMUState *s,
>      }
>
>      if (ctx->tc & RISCV_IOMMU_DC_TC_SXL) {
> -        if (mode == RISCV_IOMMU_CAP_SV32 &&
> +        if (mode == RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32 &&
>              !(s->cap & RISCV_IOMMU_CAP_SV32)) {
>                  return false;
>          }
> --
> 2.45.2
>
>

[PATCH 1/2] hw/riscv/riscv-iommu: change 'depth' to int
[PATCH 2/2] hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check