The following changes since commit 92ec7805190313c9e628f8fc4eb4f932c15247bd:
Merge tag 'pull-riscv-to-apply-20241031-1' of https://github.com/alistair23/qemu into staging (2024-10-31 16:34:25 +0000)
are available in the Git repository at:
https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.2-1-20241104
for you to fetch changes up to bd4be4d9bd20a252e677239a18b6409ecee98f56:
MAINTAINERS: Remove myself as reviewer (2024-11-04 10:09:36 +1000)
----------------------------------------------------------------
* Various bug fixes
* Big cleanup of deprecated machines
* Power11 support for spapr
* XIVE improvements
* Goodbye Cedric and David as ppc reviewers, thank you both o7
----------------------------------------------------------------
Aditya Gupta (5):
target/ppc: Introduce 'PowerPCCPUClass::spapr_logical_pvr'
target/ppc: Fix regression due to Power10 and Power11 having same PCR
target/ppc: Add Power11 DD2.0 processor
ppc/pseries: Add Power11 cpu type
hw/ppc: Implement -dtb support for PowerNV
Amit Machhiwal (2):
spapr: nested: Add support for DPDES SPR in GSB for TCG L0
spapr: nested: Add Power11 capability support for Nested PAPR guests in TCG L0
BALATON Zoltan (2):
hw/ppc: Consolidate e500 initial mapping creation functions
hw/ppc: Consolidate ppc440 initial mapping creation functions
Chalapathi V (1):
hw/ssi/pnv_spi: Fixes Coverity CID 1558831
Clément Chigot (1):
hw/ppc: fix decrementer with BookE timers
Cédric Le Goater (2):
MAINTAINERS: Remove myself from the PowerNV machines
MAINTAINERS: Remove myself from XIVE
David Gibson (1):
MAINTAINERS: Remove myself as reviewer
Frederic Barrat (5):
pnv/xive2: Define OGEN field in the TIMA
ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line"
ppc/xive2: Dump more NVP state with 'info pic'
ppc/xive2: Dump the VP-group and crowd tables with 'info pic'
tests/qtest: Add XIVE tests for the powernv10 machine
Glenn Miles (7):
pnv/xive2: Support for "OS LGS Push" TIMA operation
ppc/xive2: Allow 1-byte write of Target field in TIMA
ppc/xive2: Support "Pull Thread Context to Register" operation
ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line"
pnv/xive: Add special handling for pool targets
pnv/xive: Update PIPR when updating CPPR
pnv/xive2: TIMA support for 8-byte OS context push for PHYP
Harsh Prateek Bora (23):
ppc/spapr: remove deprecated machine pseries-2.1
ppc/spapr: remove deprecated machine pseries-2.2
ppc/spapr: remove deprecated machine pseries-2.3
ppc/spapr: remove deprecated machine pseries-2.4
ppc/spapr: remove deprecated machine pseries-2.5
ppc/spapr: remove deprecated machine pseries-2.6
ppc/spapr: remove deprecated machine pseries-2.7
ppc/spapr: remove deprecated machine pseries-2.8
ppc/spapr: remove deprecated machine pseries-2.9
ppc/spapr: remove deprecated machine pseries-2.10
ppc/spapr: remove deprecated machine pseries-2.11
ppc/spapr: remove deprecated machine pseries-2.12-sxxm
ppc/spapr: remove deprecated machine pseries-2.12
target/ppc: Reduce code duplication across Power9/10 init code
target/ppc: use locally stored msr and avoid indirect access
target/ppc: optimize hreg_compute_pmu_hflags_value
target/ppc: optimize hreg_compute_pmu_hflags_value
target/ppc: optimize p9 exception handling routines
target/ppc: optimize p8 exception handling routines
target/ppc: optimize p7 exception handling routines
target/ppc: simplify var usage in ppc_next_unmasked_interrupt
target/ppc: combine multiple ail checks into one
target/ppc: reduce duplicate code between init_proc_POWER{9, 10}
Ilya Leoshkevich (3):
target/ppc: Set ctx->opcode for decode_insn32()
target/ppc: Make divd[u] handler method decodetree compatible
tests/tcg: Replace -mpower8-vector with -mcpu=power8
Michael Kowal (3):
pnv/xive: TIMA patch sets pre-req alignment and formatting changes
ppc/xive2: Change context/ring specific functions to be generic
pnv/xive2: TIMA CI ops using alternative offsets or byte lengths
Nicholas Piggin (9):
ppc/pnv: Fix LPC serirq routing calculation
ppc/pnv: Fix LPC POWER8 register sanity check
target/ppc: Fix mtDPDES targeting SMT siblings
target/ppc: PMIs are level triggered
target/ppc: Fix doorbell delivery to threads in powersave
target/ppc: Fix HFSCR facility checks
target/ppc: Fix VRMA to not check virtual page class key protection
ppc/pnv: ADU fix possible buffer overrun with invalid size
ppc/xive: Fix ESB length overflow on 32-bit hosts
Philippe Mathieu-Daudé (3):
MAINTAINERS: Cover PowerPC SPI model in PowerNV section
hw/ssi/pnv_spi: Match _xfer_buffer_free() with _xfer_buffer_new()
hw/ssi/pnv_spi: Return early in transfer()
MAINTAINERS | 7 +-
docs/about/deprecated.rst | 8 -
docs/system/ppc/pseries.rst | 17 +-
hw/core/machine.c | 27 ---
hw/intc/pnv_xive2.c | 44 ++++-
hw/intc/spapr_xive_kvm.c | 4 +-
hw/intc/xics.c | 16 --
hw/intc/xive.c | 203 ++++++++++++++-----
hw/intc/xive2.c | 317 +++++++++++++++++++++++++-----
hw/ppc/e500.c | 41 ++--
hw/ppc/e500.h | 2 -
hw/ppc/pnv.c | 51 +++--
hw/ppc/pnv_adu.c | 12 ++
hw/ppc/pnv_lpc.c | 14 +-
hw/ppc/ppc.c | 4 +-
hw/ppc/ppc440_bamboo.c | 28 +--
hw/ppc/ppc_booke.c | 10 +
hw/ppc/ppce500_spin.c | 30 +--
hw/ppc/sam460ex.c | 45 +----
hw/ppc/spapr.c | 387 +------------------------------------
hw/ppc/spapr_cpu_core.c | 13 +-
hw/ppc/spapr_nested.c | 13 +-
hw/ppc/spapr_pci.c | 92 +--------
hw/ppc/virtex_ml507.c | 28 +--
hw/ssi/pnv_spi.c | 12 +-
include/hw/boards.h | 9 -
include/hw/pci-host/spapr.h | 5 -
include/hw/ppc/ppc.h | 7 +
include/hw/ppc/spapr.h | 3 -
include/hw/ppc/spapr_cpu_core.h | 1 -
include/hw/ppc/spapr_nested.h | 8 +-
include/hw/ppc/xive.h | 4 +-
include/hw/ppc/xive2.h | 18 ++
include/hw/ppc/xive2_regs.h | 25 ++-
include/hw/ppc/xive_regs.h | 45 +++--
migration/savevm.c | 19 --
target/ppc/compat.c | 11 ++
target/ppc/cpu-models.c | 3 +
target/ppc/cpu-models.h | 3 +
target/ppc/cpu.h | 18 +-
target/ppc/cpu_init.c | 252 +++++++++---------------
target/ppc/cpu_init.h | 91 +++++++++
target/ppc/excp_helper.c | 255 ++++++++++++------------
target/ppc/helper_regs.c | 19 +-
target/ppc/machine.c | 72 +------
target/ppc/misc_helper.c | 2 +-
target/ppc/mmu-hash64.c | 9 +-
target/ppc/translate.c | 5 +-
tests/qtest/meson.build | 2 +
tests/qtest/pnv-xive2-common.c | 190 ++++++++++++++++++
tests/qtest/pnv-xive2-common.h | 111 +++++++++++
tests/qtest/pnv-xive2-flush-sync.c | 205 ++++++++++++++++++++
tests/qtest/pnv-xive2-test.c | 344 +++++++++++++++++++++++++++++++++
tests/tcg/ppc64/Makefile.target | 10 +-
54 files changed, 1946 insertions(+), 1225 deletions(-)
create mode 100644 target/ppc/cpu_init.h
create mode 100644 tests/qtest/pnv-xive2-common.c
create mode 100644 tests/qtest/pnv-xive2-common.h
create mode 100644 tests/qtest/pnv-xive2-flush-sync.c
create mode 100644 tests/qtest/pnv-xive2-test.c