These were accidentally introduced by my last series.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/next-cube.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c
index 9832213e7e..7a503e0707 100644
--- a/hw/m68k/next-cube.c
+++ b/hw/m68k/next-cube.c
@@ -404,7 +404,7 @@ static void next_scr_writefn(void *opaque, hwaddr addr, uint64_t val,
switch (addr) {
case 0x14108:
- DPRINTF("FDCSR Write: %x\n", value);
+ DPRINTF("FDCSR Write: %"PRIx64 "\n", val);
if (val == 0x0) {
/* qemu_irq_raise(s->fd_irq[0]); */
}
@@ -468,15 +468,15 @@ static void next_scr_writefn(void *opaque, hwaddr addr, uint64_t val,
/* int_mask |= 0x1000; */
/* s->scsi_csr_1 |= 0x80; */
}
- DPRINTF("SCSICSR Write: %x\n", val);
+ DPRINTF("SCSICSR Write: %"PRIx64 "\n", val);
/* s->scsi_csr_1 = val; */
break;
/* Hardware timer latch - not implemented yet */
case 0x1a000:
default:
- DPRINTF("BMAP Write @ 0x%x with 0x%x size %u\n", (unsigned int)addr,
- val, size);
+ DPRINTF("BMAP Write @ 0x%x with 0x%"PRIx64 " size %u\n",
+ (unsigned int)addr, val, size);
}
}
@@ -585,7 +585,7 @@ static void next_dma_write(void *opaque, hwaddr addr, uint64_t val,
break;
default:
- DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)value);
+ DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)val);
}
}
--
2.39.5