Hi,
In this new version we fixed address alignment issues in some command
queue commands, pointed out by Jason in v9.
No other changes made. Series based on alistair/riscv-to-apply.next.
All patches reviewed.
Changes from v9:
- patch 3:
- fixed cmd.dword1 alignment in riscv_iommu_process_cq_tail()
- patch 8:
- fixed cmd.dword1 alignment in riscv_iommu_process_cq_tail()
- v9 link: https://lore.kernel.org/qemu-riscv/20241004155721.2154626-1-dbarboza@ventanamicro.com/
Daniel Henrique Barboza (4):
pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
test/qtest: add riscv-iommu-pci tests
qtest/riscv-iommu-test: add init queues test
docs/specs: add riscv-iommu
Tomasz Jeznach (8):
exec/memtxattr: add process identifier to the transaction attributes
hw/riscv: add riscv-iommu-bits.h
hw/riscv: add RISC-V IOMMU base emulation
hw/riscv: add riscv-iommu-pci reference device
hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
hw/riscv/riscv-iommu: add ATS support
hw/riscv/riscv-iommu: add DBG support
docs/specs/index.rst | 1 +
docs/specs/pci-ids.rst | 2 +
docs/specs/riscv-iommu.rst | 90 ++
docs/system/riscv/virt.rst | 13 +
hw/riscv/Kconfig | 4 +
hw/riscv/meson.build | 1 +
hw/riscv/riscv-iommu-bits.h | 421 ++++++
hw/riscv/riscv-iommu-pci.c | 202 +++
hw/riscv/riscv-iommu.c | 2399 ++++++++++++++++++++++++++++++
hw/riscv/riscv-iommu.h | 130 ++
hw/riscv/trace-events | 17 +
hw/riscv/trace.h | 1 +
hw/riscv/virt.c | 33 +-
include/exec/memattrs.h | 5 +
include/hw/pci/pci.h | 1 +
include/hw/riscv/iommu.h | 36 +
meson.build | 1 +
tests/qtest/libqos/meson.build | 4 +
tests/qtest/libqos/riscv-iommu.c | 76 +
tests/qtest/libqos/riscv-iommu.h | 101 ++
tests/qtest/meson.build | 1 +
tests/qtest/riscv-iommu-test.c | 210 +++
22 files changed, 3748 insertions(+), 1 deletion(-)
create mode 100644 docs/specs/riscv-iommu.rst
create mode 100644 hw/riscv/riscv-iommu-bits.h
create mode 100644 hw/riscv/riscv-iommu-pci.c
create mode 100644 hw/riscv/riscv-iommu.c
create mode 100644 hw/riscv/riscv-iommu.h
create mode 100644 hw/riscv/trace-events
create mode 100644 hw/riscv/trace.h
create mode 100644 include/hw/riscv/iommu.h
create mode 100644 tests/qtest/libqos/riscv-iommu.c
create mode 100644 tests/qtest/libqos/riscv-iommu.h
create mode 100644 tests/qtest/riscv-iommu-test.c
--
2.45.2