On 2024/10/21 09:42, Alistair Francis wrote:
> On Thu, Oct 17, 2024 at 5:33 AM Richard Henderson
> <richard.henderson@linaro.org> wrote:
>> Introduce support for the RISC-V vector extension in the TCG backend.
>>
>> v5: https://lore.kernel.org/qemu-devel/20241007025700.47259-1-zhiwei_liu@linux.alibaba.com/
>>
>> Changes for v6:
>> - Fix problem with TB overflow restart wrt the constant pool.
>> - Fix vsetivli disassembly.
>> - Change set_vtype to precompute all instructions.
>> - Extract one element before comparison in tcg_out_dupi_vec.
>> - Extract one element before comparison in tcg_target_const_match.
>> - Drop 'vm' parameter from most tcg_out_opc_* functions.
>> - Add tcg_out_opc_vv_vi and accept K constants for operations
>> which have .v.i instructions.
>> - Do not expand cmp_vec early.
>> - Fix expansion of rotls_vec.
>>
>> I've tested this on cfarm95, a banana pi bpi-f3 with 256-bit rvv-1.0,
>> with qemu-aarch64 and some vectorized test cases.
>>
>> Barring further comment, I plan to include this in a PR at the
>> end of the week.
>>
>>
>> r~
>>
>>
>> Huang Shiyuan (1):
>> tcg/riscv: Add basic support for vector
>>
>> Richard Henderson (3):
>> tcg: Reset data_gen_ptr correctly
>> disas/riscv: Fix vsetivli disassembly
>> tcg/riscv: Accept constant first argument to sub_vec
>>
>> TANG Tiancheng (10):
>> util: Add RISC-V vector extension probe in cpuinfo
>> tcg/riscv: Implement vector mov/dup{m/i}
>> tcg/riscv: Add support for basic vector opcodes
>> tcg/riscv: Implement vector cmp/cmpsel ops
>> tcg/riscv: Implement vector neg ops
>> tcg/riscv: Implement vector sat/mul ops
>> tcg/riscv: Implement vector min/max ops
>> tcg/riscv: Implement vector shi/s/v ops
>> tcg/riscv: Implement vector roti/v/x ops
>> tcg/riscv: Enable native vector support for TCG host
> Thanks!
>
> Applied to riscv-to-apply.next
>
> I have removed the Swung0x48 Signed-off-by line.
I think we should use this tag as pointed here[1]:
Signed-off-by: Huang Shiyuan <swung0x48@outlook.com>
[1]: https://mail.gnu.org/archive/html/qemu-riscv/2024-09/msg00526.html
Thanks,
Zhiwei
>
> Alistair
>
>> disas/riscv.h | 2 +-
>> host/include/riscv/host/cpuinfo.h | 2 +
>> include/tcg/tcg.h | 6 +
>> tcg/riscv/tcg-target-con-set.h | 9 +
>> tcg/riscv/tcg-target-con-str.h | 3 +
>> tcg/riscv/tcg-target.h | 78 ++-
>> tcg/riscv/tcg-target.opc.h | 12 +
>> disas/riscv.c | 2 +-
>> tcg/tcg.c | 2 +-
>> util/cpuinfo-riscv.c | 24 +-
>> tcg/riscv/tcg-target.c.inc | 994 +++++++++++++++++++++++++++---
>> 11 files changed, 1011 insertions(+), 123 deletions(-)
>> create mode 100644 tcg/riscv/tcg-target.opc.h
>>
>> --
>> 2.43.0
>>
>>