On 10/14/24 03:48, Manos Pitsidianakis wrote:
> Add FEAT_XS feature report value in max cpu's ID_AA64ISAR1 sys register.
>
> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
> ---
> target/arm/tcg/cpu64.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index 0168920828651492b1114d66ab0fc72c20dda2a8..8c8f88d84151952872f1b1987e98d789b501fb23 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -1163,6 +1163,7 @@ void aarch64_max_tcg_initfn(Object *obj)
> t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF16 */
> t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
> t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
> + t = FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */
> cpu->isar.id_aa64isar1 = t;
>
> t = cpu->isar.id_aa64isar2;
>
Actually, this or a follow-up is missing the change to
docs/system/arm/emulation.rst.
r~