From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>

RISC-V always requires 4MB alignment for RV32.

Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
---
 hw/riscv/boot.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 1a2c1ff9e0..7ce0d8f08f 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -69,7 +69,8 @@ char *riscv_plic_hart_config_string(int hart_count)
 
 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
                                           target_ulong firmware_end_addr) {
-    if (riscv_is_32bit(harts)) {
+    RISCVCPU *cpu = &harts->harts[0];
+    if (riscv_is_32bit(harts) || cpu->cfg.sxl32) {
         return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
     } else {
         return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
-- 
2.43.0