target/riscv: Support SXL32 on RV64 CPU

[PATCH v1 2/7] target/riscv: Fix satp read and write implicitly or explicitly.

Posted by LIU Zhiwei 1 month, 2 weeks ago

From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>

CSR satp is SXLEN bits in length and always has the $layout determined by
the SXL configuration, regardless of the current XLEN.

Only process CSR satp, as we still don't have a riscv_cpu_vsxl API
currently.

Added sxl32 property to control sxlen as 32 in s-mode for QEMU RV64.

Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Fixes: c7b9517188 (RISC-V: Implement modular CSR helper interface)
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
---
 target/riscv/cpu_cfg.h |  4 ++++
 target/riscv/csr.c     | 25 +++++++++++++++++++------
 2 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 8b272fb826..cdbd2afe29 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -173,6 +173,10 @@ struct RISCVCPUConfig {
     bool short_isa_string;
 
 #ifndef CONFIG_USER_ONLY
+    /*
+     * true when RV64 QEMU running with mxlen==64 but sxlen==32.
+     */
+    bool sxl32;
     RISCVSATPMap satp_mode;
 #endif
 };
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b33cc1ec23..93a5cf87ed 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1504,16 +1504,29 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
 
 static bool validate_vm(CPURISCVState *env, target_ulong vm)
 {
-    uint64_t mode_supported = riscv_cpu_cfg(env)->satp_mode.map;
+    uint64_t mode_supported = 0;
+    if (riscv_cpu_cfg(env)->sxl32 && (riscv_cpu_mxl(env) != MXL_RV32)) {
+        mode_supported = (1 << VM_1_10_MBARE) | (1 << VM_1_10_SV32);
+    } else {
+        mode_supported = riscv_cpu_cfg(env)->satp_mode.map;
+    }
     return get_field(mode_supported, (1 << vm));
 }
 
 static target_ulong legalize_xatp(CPURISCVState *env, target_ulong old_xatp,
-                                  target_ulong val)
+                                  target_ulong val, int csrno)
 {
     target_ulong mask;
     bool vm;
-    if (riscv_cpu_mxl(env) == MXL_RV32) {
+    RISCVMXL xl;
+
+    if (csrno == CSR_SATP) {
+        xl = riscv_cpu_sxl(env);
+    } else {
+        xl = riscv_cpu_mxl(env);
+    }
+
+    if (xl == MXL_RV32) {
         vm = validate_vm(env, get_field(val, SATP32_MODE));
         mask = (val ^ old_xatp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
     } else {
@@ -3316,7 +3329,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
 
-    env->satp = legalize_xatp(env, env->satp, val);
+    env->satp = legalize_xatp(env, env->satp, val, csrno);
     return RISCV_EXCP_NONE;
 }
 
@@ -3834,7 +3847,7 @@ static RISCVException read_hgatp(CPURISCVState *env, int csrno,
 static RISCVException write_hgatp(CPURISCVState *env, int csrno,
                                   target_ulong val)
 {
-    env->hgatp = legalize_xatp(env, env->hgatp, val);
+    env->hgatp = legalize_xatp(env, env->hgatp, val, csrno);
     return RISCV_EXCP_NONE;
 }
 
@@ -4116,7 +4129,7 @@ static RISCVException read_vsatp(CPURISCVState *env, int csrno,
 static RISCVException write_vsatp(CPURISCVState *env, int csrno,
                                   target_ulong val)
 {
-    env->vsatp = legalize_xatp(env, env->vsatp, val);
+    env->vsatp = legalize_xatp(env, env->vsatp, val, csrno);
     return RISCV_EXCP_NONE;
 }
 
-- 
2.43.0

Re: [PATCH v1 2/7] target/riscv: Fix satp read and write implicitly or explicitly.

Posted by Alistair Francis 1 month, 1 week ago

On Mon, Oct 7, 2024 at 1:35 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>
> CSR satp is SXLEN bits in length and always has the $layout determined by
> the SXL configuration, regardless of the current XLEN.
>
> Only process CSR satp, as we still don't have a riscv_cpu_vsxl API
> currently.
>
> Added sxl32 property to control sxlen as 32 in s-mode for QEMU RV64.
>
> Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
> Fixes: c7b9517188 (RISC-V: Implement modular CSR helper interface)
> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
>  target/riscv/cpu_cfg.h |  4 ++++
>  target/riscv/csr.c     | 25 +++++++++++++++++++------
>  2 files changed, 23 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 8b272fb826..cdbd2afe29 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -173,6 +173,10 @@ struct RISCVCPUConfig {
>      bool short_isa_string;
>
>  #ifndef CONFIG_USER_ONLY
> +    /*
> +     * true when RV64 QEMU running with mxlen==64 but sxlen==32.
> +     */
> +    bool sxl32;
>      RISCVSATPMap satp_mode;
>  #endif
>  };
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index b33cc1ec23..93a5cf87ed 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1504,16 +1504,29 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
>
>  static bool validate_vm(CPURISCVState *env, target_ulong vm)
>  {
> -    uint64_t mode_supported = riscv_cpu_cfg(env)->satp_mode.map;
> +    uint64_t mode_supported = 0;
> +    if (riscv_cpu_cfg(env)->sxl32 && (riscv_cpu_mxl(env) != MXL_RV32)) {

This should be using the actual SXLEN values, not this special
property. What happens if the property is set to false but the guest
software sets SXLEN to 32-bits? This will break

Alistair

> +        mode_supported = (1 << VM_1_10_MBARE) | (1 << VM_1_10_SV32);
> +    } else {
> +        mode_supported = riscv_cpu_cfg(env)->satp_mode.map;
> +    }
>      return get_field(mode_supported, (1 << vm));
>  }
>
>  static target_ulong legalize_xatp(CPURISCVState *env, target_ulong old_xatp,
> -                                  target_ulong val)
> +                                  target_ulong val, int csrno)
>  {
>      target_ulong mask;
>      bool vm;
> -    if (riscv_cpu_mxl(env) == MXL_RV32) {
> +    RISCVMXL xl;
> +
> +    if (csrno == CSR_SATP) {
> +        xl = riscv_cpu_sxl(env);
> +    } else {
> +        xl = riscv_cpu_mxl(env);
> +    }
> +
> +    if (xl == MXL_RV32) {
>          vm = validate_vm(env, get_field(val, SATP32_MODE));
>          mask = (val ^ old_xatp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
>      } else {
> @@ -3316,7 +3329,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
>          return RISCV_EXCP_NONE;
>      }
>
> -    env->satp = legalize_xatp(env, env->satp, val);
> +    env->satp = legalize_xatp(env, env->satp, val, csrno);
>      return RISCV_EXCP_NONE;
>  }
>
> @@ -3834,7 +3847,7 @@ static RISCVException read_hgatp(CPURISCVState *env, int csrno,
>  static RISCVException write_hgatp(CPURISCVState *env, int csrno,
>                                    target_ulong val)
>  {
> -    env->hgatp = legalize_xatp(env, env->hgatp, val);
> +    env->hgatp = legalize_xatp(env, env->hgatp, val, csrno);
>      return RISCV_EXCP_NONE;
>  }
>
> @@ -4116,7 +4129,7 @@ static RISCVException read_vsatp(CPURISCVState *env, int csrno,
>  static RISCVException write_vsatp(CPURISCVState *env, int csrno,
>                                    target_ulong val)
>  {
> -    env->vsatp = legalize_xatp(env, env->vsatp, val);
> +    env->vsatp = legalize_xatp(env, env->vsatp, val, csrno);
>      return RISCV_EXCP_NONE;
>  }
>
> --
> 2.43.0
>
>

[PATCH v1 1/7] target/riscv: Fix sstatus read and write
[PATCH v1 2/7] target/riscv: Fix satp read and write implicitly or explicitly.
[PATCH v1 3/7] target/riscv: Read pte and satp based on SXL in PTW
[PATCH v1 4/7] hw/riscv: Align kernel to 4MB when sxl32 is on.
[PATCH v1 5/7] target/riscv: Enable 32-bit only registers for RV64 with sxl32
[PATCH v1 6/7] target/riscv: Reset SXL and UXL according to sxl32
[PATCH v1 7/7] target/riscv: Expose sxl32 configuration in RISC-V CPU