On 9/30/24 10:52, Jamin Lin wrote:
> The register set of GPIO have a significant change since AST2700.
> Each GPIO pin has their own individual control register and users are able to
> set one GPIO pin’s direction, interrupt enable, input mask and so on in the
> same one control register.
>
> AST2700 does not have GPIO18_XXX registers for GPIO 1.8v, removes
> ASPEED_DEV_GPIO_1_8V. It is enough to only have ASPEED_DEV_GPIO
> device in AST2700.
>
> The AST2700 GPIO controller interrupt is connected to GICINT130_INTC at
> bit 18. Therefore, correct GPIO irq 130.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> hw/arm/aspeed_ast27x0.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 761ee11657..99135edc1e 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -87,8 +87,7 @@ static const int aspeed_soc_ast2700_irqmap[] = {
> [ASPEED_DEV_ADC] = 130,
> [ASPEED_DEV_XDMA] = 5,
> [ASPEED_DEV_EMMC] = 15,
> - [ASPEED_DEV_GPIO] = 11,
> - [ASPEED_DEV_GPIO_1_8V] = 130,
> + [ASPEED_DEV_GPIO] = 130,
> [ASPEED_DEV_RTC] = 13,
> [ASPEED_DEV_TIMER1] = 16,
> [ASPEED_DEV_TIMER2] = 17,
> @@ -124,7 +123,7 @@ static const int aspeed_soc_ast2700_gic128_intcmap[] = {
> static const int aspeed_soc_ast2700_gic130_intcmap[] = {
> [ASPEED_DEV_I2C] = 0,
> [ASPEED_DEV_ADC] = 16,
> - [ASPEED_DEV_GPIO_1_8V] = 18,
> + [ASPEED_DEV_GPIO] = 18,
> };
>
> /* GICINT 131 */