[PULL 0/7] loongarch-to-apply queue
[PULL 00/18] loongarch-to-apply queue
1
The following changes since commit 3b14a767eaca3df5534a162851f04787b363670e:
1
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
2
2
3
Merge tag 'qemu-openbios-20240924' of https://github.com/mcayland/qemu into staging (2024-09-28 12:34:44 +0100)
3
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240929
7
https://gitlab.com/bibo-mao/qemu.git pull-loongarch-20241213
8
8
9
for you to fetch changes up to f7c8ef7bad7495d8c84b262a8b243efe39e56b13:
9
for you to fetch changes up to 78aa256571aa06f32001bd80635a1858187c609b:
10
10
11
hw/loongarch/fw_cfg: Build in common_ss[] (2024-09-29 16:22:56 +0800)
11
hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic (2024-12-13 14:39:39 +0800)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
pull-loongarch-20240929
14
pull-loongarch-20241213
15
15
16
----------------------------------------------------------------
16
----------------------------------------------------------------
17
Bibo Mao (3):
17
Bibo Mao (8):
18
acpi: ged: Add macro for acpi sleep control register
18
include: Add loongarch_pic_common header file
19
hw/loongarch/virt: Add FDT table support with acpi ged pm register
19
include: Move struct LoongArchPCHPIC to loongarch_pic_common header file
20
target/loongarch: Avoid bits shift exceeding width of bool type
20
hw/intc/loongarch_pch: Merge instance_init() into realize()
21
hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonState
22
hw/intc/loongarch_pch: Move some functions to file loongarch_pic_common
23
hw/intc/loongarch_pch: Inherit from loongarch_pic_common
24
hw/intc/loongarch_pch: Add pre_save and post_load interfaces
25
hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic
21
26
22
Jiaxun Yang (2):
27
hw/intc/loongarch_pch_pic.c | 106 +++++++++++----------------------
23
hw/loongarch/boot: Refactor EFI booting protocol generation
28
hw/intc/loongarch_pic_common.c | 97 ++++++++++++++++++++++++++++++
24
hw/loongarch/boot: Rework boot code generation
29
hw/intc/meson.build | 2 +-
25
30
hw/loongarch/virt.c | 2 +-
26
Philippe Mathieu-Daudé (2):
31
include/hw/intc/loongarch_pch_pic.h | 70 +++++-----------------
27
hw/loongarch/virt: Remove unnecessary 'cpu.h' inclusion
32
include/hw/intc/loongarch_pic_common.h | 82 +++++++++++++++++++++++++
28
hw/loongarch/fw_cfg: Build in common_ss[]
33
6 files changed, 230 insertions(+), 129 deletions(-)
29
34
create mode 100644 hw/intc/loongarch_pic_common.c
30
hw/acpi/generic_event_device.c | 6 +-
35
create mode 100644 include/hw/intc/loongarch_pic_common.h
31
hw/loongarch/boot.c | 321 +++++++++++++++++++++------------
32
hw/loongarch/meson.build | 2 +-
33
hw/loongarch/virt.c | 39 ++++
34
include/hw/acpi/generic_event_device.h | 7 +-
35
include/hw/loongarch/boot.h | 106 +++++++++--
36
include/hw/loongarch/virt.h | 1 -
37
target/loongarch/arch_dump.c | 6 +-
38
8 files changed, 342 insertions(+), 146 deletions(-)
39
40
diff view generated by jsdifflib
New patch
[PULL 01/18] include: Add loongarch_pic_common header file
1
Add common header file hw/intc/loongarch_pic_common.h, and move
2
some macro definition from hw/intc/loongarch_pch_pic.h to the common
3
header file.
1
4
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
include/hw/intc/loongarch_pch_pic.h | 36 +++-------------------
9
include/hw/intc/loongarch_pic_common.h | 42 ++++++++++++++++++++++++++
10
2 files changed, 47 insertions(+), 31 deletions(-)
11
create mode 100644 include/hw/intc/loongarch_pic_common.h
12
13
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/intc/loongarch_pch_pic.h
16
+++ b/include/hw/intc/loongarch_pch_pic.h
17
@@ -XXX,XX +XXX,XX @@
18
* Copyright (c) 2021 Loongson Technology Corporation Limited
19
*/
20
21
-#include "hw/sysbus.h"
22
+#ifndef HW_LOONGARCH_PCH_PIC_H
23
+#define HW_LOONGARCH_PCH_PIC_H
24
+
25
+#include "hw/intc/loongarch_pic_common.h"
26
27
#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
28
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
29
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
30
31
-#define PCH_PIC_INT_ID_VAL 0x7000000UL
32
-#define PCH_PIC_INT_ID_VER 0x1UL
33
-
34
-#define PCH_PIC_INT_ID_LO 0x00
35
-#define PCH_PIC_INT_ID_HI 0x04
36
-#define PCH_PIC_INT_MASK_LO 0x20
37
-#define PCH_PIC_INT_MASK_HI 0x24
38
-#define PCH_PIC_HTMSI_EN_LO 0x40
39
-#define PCH_PIC_HTMSI_EN_HI 0x44
40
-#define PCH_PIC_INT_EDGE_LO 0x60
41
-#define PCH_PIC_INT_EDGE_HI 0x64
42
-#define PCH_PIC_INT_CLEAR_LO 0x80
43
-#define PCH_PIC_INT_CLEAR_HI 0x84
44
-#define PCH_PIC_AUTO_CTRL0_LO 0xc0
45
-#define PCH_PIC_AUTO_CTRL0_HI 0xc4
46
-#define PCH_PIC_AUTO_CTRL1_LO 0xe0
47
-#define PCH_PIC_AUTO_CTRL1_HI 0xe4
48
-#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100
49
-#define PCH_PIC_ROUTE_ENTRY_END 0x13f
50
-#define PCH_PIC_HTMSI_VEC_OFFSET 0x200
51
-#define PCH_PIC_HTMSI_VEC_END 0x23f
52
-#define PCH_PIC_INT_STATUS_LO 0x3a0
53
-#define PCH_PIC_INT_STATUS_HI 0x3a4
54
-#define PCH_PIC_INT_POL_LO 0x3e0
55
-#define PCH_PIC_INT_POL_HI 0x3e4
56
-
57
-#define STATUS_LO_START 0
58
-#define STATUS_HI_START 0x4
59
-#define POL_LO_START 0x40
60
-#define POL_HI_START 0x44
61
struct LoongArchPCHPIC {
62
SysBusDevice parent_obj;
63
qemu_irq parent_irq[64];
64
@@ -XXX,XX +XXX,XX @@ struct LoongArchPCHPIC {
65
MemoryRegion iomem8;
66
unsigned int irq_num;
67
};
68
+#endif /* HW_LOONGARCH_PCH_PIC_H */
69
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
70
new file mode 100644
71
index XXXXXXX..XXXXXXX
72
--- /dev/null
73
+++ b/include/hw/intc/loongarch_pic_common.h
74
@@ -XXX,XX +XXX,XX @@
75
+/* SPDX-License-Identifier: GPL-2.0-or-later */
76
+/*
77
+ * LoongArch 7A1000 I/O interrupt controller definitions
78
+ * Copyright (c) 2024 Loongson Technology Corporation Limited
79
+ */
80
+
81
+#ifndef HW_LOONGARCH_PIC_COMMON_H
82
+#define HW_LOONGARCH_PIC_COMMON_H
83
+
84
+#include "hw/pci-host/ls7a.h"
85
+#include "hw/sysbus.h"
86
+
87
+#define PCH_PIC_INT_ID_VAL 0x7000000UL
88
+#define PCH_PIC_INT_ID_VER 0x1UL
89
+#define PCH_PIC_INT_ID_LO 0x00
90
+#define PCH_PIC_INT_ID_HI 0x04
91
+#define PCH_PIC_INT_MASK_LO 0x20
92
+#define PCH_PIC_INT_MASK_HI 0x24
93
+#define PCH_PIC_HTMSI_EN_LO 0x40
94
+#define PCH_PIC_HTMSI_EN_HI 0x44
95
+#define PCH_PIC_INT_EDGE_LO 0x60
96
+#define PCH_PIC_INT_EDGE_HI 0x64
97
+#define PCH_PIC_INT_CLEAR_LO 0x80
98
+#define PCH_PIC_INT_CLEAR_HI 0x84
99
+#define PCH_PIC_AUTO_CTRL0_LO 0xc0
100
+#define PCH_PIC_AUTO_CTRL0_HI 0xc4
101
+#define PCH_PIC_AUTO_CTRL1_LO 0xe0
102
+#define PCH_PIC_AUTO_CTRL1_HI 0xe4
103
+#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100
104
+#define PCH_PIC_ROUTE_ENTRY_END 0x13f
105
+#define PCH_PIC_HTMSI_VEC_OFFSET 0x200
106
+#define PCH_PIC_HTMSI_VEC_END 0x23f
107
+#define PCH_PIC_INT_STATUS_LO 0x3a0
108
+#define PCH_PIC_INT_STATUS_HI 0x3a4
109
+#define PCH_PIC_INT_POL_LO 0x3e0
110
+#define PCH_PIC_INT_POL_HI 0x3e4
111
+
112
+#define STATUS_LO_START 0
113
+#define STATUS_HI_START 0x4
114
+#define POL_LO_START 0x40
115
+#define POL_HI_START 0x44
116
+#endif /* HW_LOONGARCH_PIC_COMMON_H */
117
--
118
2.43.5
diff view generated by jsdifflib
New patch
[PULL 02/18] include: Move struct LoongArchPCHPIC to loongarch_pic_common header file
1
Move structure LoongArchPCHPIC from header file loongarch_pch_pic.h
2
to file loongarch_pic_common.h, and rename structure name with
3
LoongArchPICCommonState.
1
4
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
include/hw/intc/loongarch_pch_pic.h | 27 +------------------------
9
include/hw/intc/loongarch_pic_common.h | 28 ++++++++++++++++++++++++++
10
2 files changed, 29 insertions(+), 26 deletions(-)
11
12
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/include/hw/intc/loongarch_pch_pic.h
15
+++ b/include/hw/intc/loongarch_pch_pic.h
16
@@ -XXX,XX +XXX,XX @@
17
18
#include "hw/intc/loongarch_pic_common.h"
19
20
+#define LoongArchPCHPIC LoongArchPICCommonState
21
#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
22
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
23
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
24
25
-struct LoongArchPCHPIC {
26
- SysBusDevice parent_obj;
27
- qemu_irq parent_irq[64];
28
- uint64_t int_mask; /*0x020 interrupt mask register*/
29
- uint64_t htmsi_en; /*0x040 1=msi*/
30
- uint64_t intedge; /*0x060 edge=1 level =0*/
31
- uint64_t intclr; /*0x080 for clean edge int,set 1 clean,set 0 is noused*/
32
- uint64_t auto_crtl0; /*0x0c0*/
33
- uint64_t auto_crtl1; /*0x0e0*/
34
- uint64_t last_intirr; /* edge detection */
35
- uint64_t intirr; /* 0x380 interrupt request register */
36
- uint64_t intisr; /* 0x3a0 interrupt service register */
37
- /*
38
- * 0x3e0 interrupt level polarity selection
39
- * register 0 for high level trigger
40
- */
41
- uint64_t int_polarity;
42
-
43
- uint8_t route_entry[64]; /*0x100 - 0x138*/
44
- uint8_t htmsi_vector[64]; /*0x200 - 0x238*/
45
-
46
- MemoryRegion iomem32_low;
47
- MemoryRegion iomem32_high;
48
- MemoryRegion iomem8;
49
- unsigned int irq_num;
50
-};
51
#endif /* HW_LOONGARCH_PCH_PIC_H */
52
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
53
index XXXXXXX..XXXXXXX 100644
54
--- a/include/hw/intc/loongarch_pic_common.h
55
+++ b/include/hw/intc/loongarch_pic_common.h
56
@@ -XXX,XX +XXX,XX @@
57
#define STATUS_HI_START 0x4
58
#define POL_LO_START 0x40
59
#define POL_HI_START 0x44
60
+
61
+struct LoongArchPICCommonState {
62
+ SysBusDevice parent_obj;
63
+
64
+ qemu_irq parent_irq[64];
65
+ uint64_t int_mask; /* 0x020 interrupt mask register */
66
+ uint64_t htmsi_en; /* 0x040 1=msi */
67
+ uint64_t intedge; /* 0x060 edge=1 level=0 */
68
+ uint64_t intclr; /* 0x080 clean edge int, set 1 clean, 0 noused */
69
+ uint64_t auto_crtl0; /* 0x0c0 */
70
+ uint64_t auto_crtl1; /* 0x0e0 */
71
+ uint64_t last_intirr; /* edge detection */
72
+ uint64_t intirr; /* 0x380 interrupt request register */
73
+ uint64_t intisr; /* 0x3a0 interrupt service register */
74
+ /*
75
+ * 0x3e0 interrupt level polarity selection
76
+ * register 0 for high level trigger
77
+ */
78
+ uint64_t int_polarity;
79
+
80
+ uint8_t route_entry[64]; /* 0x100 - 0x138 */
81
+ uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */
82
+
83
+ MemoryRegion iomem32_low;
84
+ MemoryRegion iomem32_high;
85
+ MemoryRegion iomem8;
86
+ unsigned int irq_num;
87
+};
88
#endif /* HW_LOONGARCH_PIC_COMMON_H */
89
--
90
2.43.5
diff view generated by jsdifflib
New patch
[PULL 03/18] hw/intc/loongarch_pch: Merge instance_init() into realize()
1
Memory region is created in instance_init(), merge it into function
2
realize(). There is no special class_init() for loongarch_pch object.
1
3
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
---
7
hw/intc/loongarch_pch_pic.c | 15 ++++-----------
8
1 file changed, 4 insertions(+), 11 deletions(-)
9
10
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/intc/loongarch_pch_pic.c
13
+++ b/hw/intc/loongarch_pch_pic.c
14
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
15
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
16
{
17
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
18
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
19
20
if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
21
error_setg(errp, "Invalid 'pic_irq_num'");
22
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
23
24
qdev_init_gpio_out(dev, s->parent_irq, s->irq_num);
25
qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num);
26
-}
27
-
28
-static void loongarch_pch_pic_init(Object *obj)
29
-{
30
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(obj);
31
- SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
32
-
33
- memory_region_init_io(&s->iomem32_low, obj,
34
+ memory_region_init_io(&s->iomem32_low, OBJECT(dev),
35
&loongarch_pch_pic_reg32_low_ops,
36
s, PCH_PIC_NAME(.reg32_part1), 0x100);
37
- memory_region_init_io(&s->iomem8, obj, &loongarch_pch_pic_reg8_ops,
38
+ memory_region_init_io(&s->iomem8, OBJECT(dev), &loongarch_pch_pic_reg8_ops,
39
s, PCH_PIC_NAME(.reg8), 0x2a0);
40
- memory_region_init_io(&s->iomem32_high, obj,
41
+ memory_region_init_io(&s->iomem32_high, OBJECT(dev),
42
&loongarch_pch_pic_reg32_high_ops,
43
s, PCH_PIC_NAME(.reg32_part2), 0xc60);
44
sysbus_init_mmio(sbd, &s->iomem32_low);
45
@@ -XXX,XX +XXX,XX @@ static const TypeInfo loongarch_pch_pic_info = {
46
.name = TYPE_LOONGARCH_PCH_PIC,
47
.parent = TYPE_SYS_BUS_DEVICE,
48
.instance_size = sizeof(LoongArchPCHPIC),
49
- .instance_init = loongarch_pch_pic_init,
50
.class_init = loongarch_pch_pic_class_init,
51
};
52
53
--
54
2.43.5
diff view generated by jsdifflib
New patch
[PULL 04/18] hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonState
1
With pic vmstate, rename structure name vmstate_loongarch_pch_pic with
2
vmstate_loongarch_pic_common, and with pic property rename
3
loongarch_pch_pic_properties with loongarch_pic_common_properties.
1
4
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
hw/intc/loongarch_pch_pic.c | 52 +++++++++++++++++++++++--------------
9
1 file changed, 32 insertions(+), 20 deletions(-)
10
11
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/loongarch_pch_pic.c
14
+++ b/hw/intc/loongarch_pch_pic.c
15
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
16
s->int_polarity = 0x0;
17
}
18
19
+static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
20
+{
21
+ LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
22
+
23
+ if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
24
+ error_setg(errp, "Invalid 'pic_irq_num'");
25
+ return;
26
+ }
27
+}
28
+
29
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
30
{
31
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
32
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
33
+ Error *local_err = NULL;
34
35
- if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
36
- error_setg(errp, "Invalid 'pic_irq_num'");
37
+ loongarch_pic_common_realize(dev, &local_err);
38
+ if (local_err) {
39
+ error_propagate(errp, local_err);
40
return;
41
}
42
43
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
44
45
}
46
47
-static Property loongarch_pch_pic_properties[] = {
48
- DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPCHPIC, irq_num, 0),
49
+static Property loongarch_pic_common_properties[] = {
50
+ DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
51
DEFINE_PROP_END_OF_LIST(),
52
};
53
54
-static const VMStateDescription vmstate_loongarch_pch_pic = {
55
- .name = TYPE_LOONGARCH_PCH_PIC,
56
+static const VMStateDescription vmstate_loongarch_pic_common = {
57
+ .name = "loongarch_pch_pic",
58
.version_id = 1,
59
.minimum_version_id = 1,
60
.fields = (const VMStateField[]) {
61
- VMSTATE_UINT64(int_mask, LoongArchPCHPIC),
62
- VMSTATE_UINT64(htmsi_en, LoongArchPCHPIC),
63
- VMSTATE_UINT64(intedge, LoongArchPCHPIC),
64
- VMSTATE_UINT64(intclr, LoongArchPCHPIC),
65
- VMSTATE_UINT64(auto_crtl0, LoongArchPCHPIC),
66
- VMSTATE_UINT64(auto_crtl1, LoongArchPCHPIC),
67
- VMSTATE_UINT8_ARRAY(route_entry, LoongArchPCHPIC, 64),
68
- VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPCHPIC, 64),
69
- VMSTATE_UINT64(last_intirr, LoongArchPCHPIC),
70
- VMSTATE_UINT64(intirr, LoongArchPCHPIC),
71
- VMSTATE_UINT64(intisr, LoongArchPCHPIC),
72
- VMSTATE_UINT64(int_polarity, LoongArchPCHPIC),
73
+ VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
74
+ VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
75
+ VMSTATE_UINT64(intedge, LoongArchPICCommonState),
76
+ VMSTATE_UINT64(intclr, LoongArchPICCommonState),
77
+ VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
78
+ VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
79
+ VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
80
+ VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
81
+ VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
82
+ VMSTATE_UINT64(intirr, LoongArchPICCommonState),
83
+ VMSTATE_UINT64(intisr, LoongArchPICCommonState),
84
+ VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
85
VMSTATE_END_OF_LIST()
86
}
87
};
88
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
89
90
dc->realize = loongarch_pch_pic_realize;
91
device_class_set_legacy_reset(dc, loongarch_pch_pic_reset);
92
- dc->vmsd = &vmstate_loongarch_pch_pic;
93
- device_class_set_props(dc, loongarch_pch_pic_properties);
94
+ dc->vmsd = &vmstate_loongarch_pic_common;
95
+ device_class_set_props(dc, loongarch_pic_common_properties);
96
}
97
98
static const TypeInfo loongarch_pch_pic_info = {
99
--
100
2.43.5
diff view generated by jsdifflib
New patch
[PULL 05/18] hw/intc/loongarch_pch: Move some functions to file loongarch_pic_common
1
Move some common functions to file loongarch_pic_common.c, the common
2
functions include loongarch_pic_common_realize(), property structure
3
loongarch_pic_common_properties and vmstate structure
4
vmstate_loongarch_pic_common.
1
5
6
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
7
Reviewed-by: Song Gao <gaosong@loongson.cn>
8
---
9
hw/intc/loongarch_pch_pic.c | 37 +-----------------------------
10
hw/intc/loongarch_pic_common.c | 41 ++++++++++++++++++++++++++++++++++
11
2 files changed, 42 insertions(+), 36 deletions(-)
12
create mode 100644 hw/intc/loongarch_pic_common.c
13
14
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/loongarch_pch_pic.c
17
+++ b/hw/intc/loongarch_pch_pic.c
18
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
19
s->int_polarity = 0x0;
20
}
21
22
-static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
23
-{
24
- LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
25
-
26
- if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
27
- error_setg(errp, "Invalid 'pic_irq_num'");
28
- return;
29
- }
30
-}
31
-
32
+#include "loongarch_pic_common.c"
33
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
34
{
35
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
36
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
37
38
}
39
40
-static Property loongarch_pic_common_properties[] = {
41
- DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
42
- DEFINE_PROP_END_OF_LIST(),
43
-};
44
-
45
-static const VMStateDescription vmstate_loongarch_pic_common = {
46
- .name = "loongarch_pch_pic",
47
- .version_id = 1,
48
- .minimum_version_id = 1,
49
- .fields = (const VMStateField[]) {
50
- VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
51
- VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
52
- VMSTATE_UINT64(intedge, LoongArchPICCommonState),
53
- VMSTATE_UINT64(intclr, LoongArchPICCommonState),
54
- VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
55
- VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
56
- VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
57
- VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
58
- VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
59
- VMSTATE_UINT64(intirr, LoongArchPICCommonState),
60
- VMSTATE_UINT64(intisr, LoongArchPICCommonState),
61
- VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
62
- VMSTATE_END_OF_LIST()
63
- }
64
-};
65
-
66
static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
67
{
68
DeviceClass *dc = DEVICE_CLASS(klass);
69
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
70
new file mode 100644
71
index XXXXXXX..XXXXXXX
72
--- /dev/null
73
+++ b/hw/intc/loongarch_pic_common.c
74
@@ -XXX,XX +XXX,XX @@
75
+/* SPDX-License-Identifier: GPL-2.0-or-later */
76
+/*
77
+ * QEMU Loongson 7A1000 I/O interrupt controller.
78
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
79
+ */
80
+
81
+static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
82
+{
83
+ LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
84
+
85
+ if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
86
+ error_setg(errp, "Invalid 'pic_irq_num'");
87
+ return;
88
+ }
89
+}
90
+
91
+static Property loongarch_pic_common_properties[] = {
92
+ DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
93
+ DEFINE_PROP_END_OF_LIST(),
94
+};
95
+
96
+static const VMStateDescription vmstate_loongarch_pic_common = {
97
+ .name = "loongarch_pch_pic",
98
+ .version_id = 1,
99
+ .minimum_version_id = 1,
100
+ .fields = (const VMStateField[]) {
101
+ VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
102
+ VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
103
+ VMSTATE_UINT64(intedge, LoongArchPICCommonState),
104
+ VMSTATE_UINT64(intclr, LoongArchPICCommonState),
105
+ VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
106
+ VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
107
+ VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
108
+ VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
109
+ VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
110
+ VMSTATE_UINT64(intirr, LoongArchPICCommonState),
111
+ VMSTATE_UINT64(intisr, LoongArchPICCommonState),
112
+ VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
113
+ VMSTATE_END_OF_LIST()
114
+ }
115
+};
116
--
117
2.43.5
diff view generated by jsdifflib
[PULL 3/7] hw/loongarch/boot: Refactor EFI booting protocol generation
[PULL 06/18] hw/intc/loongarch_pch: Inherit from loongarch_pic_common
1
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
1
Set TYPE_LOONGARCH_PIC inherit from TYPE_LOONGARCH_PIC_COMMON object,
2
it shares vmsate and property of TYPE_LOONGARCH_PIC_COMMON, and has
3
its own realize() function.
2
4
3
Refector EFI style booting data structure generation to
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
support 32bit EFI variant on LoongArch32 CPU.
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
hw/intc/loongarch_pch_pic.c | 38 ++++++++++++--------------
9
hw/intc/loongarch_pic_common.c | 32 +++++++++++++++++++++-
10
hw/intc/meson.build | 2 +-
11
include/hw/intc/loongarch_pch_pic.h | 21 +++++++++++---
12
include/hw/intc/loongarch_pic_common.h | 10 +++++++
13
5 files changed, 77 insertions(+), 26 deletions(-)
5
14
6
All data structs are filled with padding members if necessary
15
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
7
and marked as QEMU_PACKED to avoid host ABI alignment impact.
8
9
Host endian is being cared as well.
10
11
It also fixed various problems in old implementation such
12
as null pointer on empty string, memory desc map_size not set,
13
incorrect memory map definition and so on.
14
15
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
16
Reviewed-by: Song Gao <gaosong@loongson.cn>
17
Message-Id: <20240914-loongarch-booting-v1-1-1517cae11c10@flygoat.com>
18
Signed-off-by: Song Gao <gaosong@loongson.cn>
19
---
20
hw/loongarch/boot.c | 220 ++++++++++++++++++++++++------------
21
include/hw/loongarch/boot.h | 106 +++++++++++++----
22
2 files changed, 237 insertions(+), 89 deletions(-)
23
24
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
25
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/loongarch/boot.c
17
--- a/hw/intc/loongarch_pch_pic.c
27
+++ b/hw/loongarch/boot.c
18
+++ b/hw/intc/loongarch_pch_pic.c
28
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
29
* Copyright (c) 2023 Loongson Technology Corporation Limited
20
s->int_polarity = 0x0;
30
*/
31
32
+#include <zlib.h>
33
#include "qemu/osdep.h"
34
#include "qemu/units.h"
35
#include "target/loongarch/cpu.h"
36
@@ -XXX,XX +XXX,XX @@ static const unsigned int slave_boot_code[] = {
37
38
/* Clear mailbox. */
39
0x1400002d, /* lu12i.w $t1, 1(0x1) */
40
- 0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */
41
+ 0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */
42
0x06481da0, /* iocsrwr.d $zero, $t1 */
43
44
/* Enable IPI interrupt. */
45
@@ -XXX,XX +XXX,XX @@ static inline void *guidcpy(void *dst, const void *src)
46
return memcpy(dst, src, sizeof(efi_guid_t));
47
}
21
}
48
22
49
-static void init_efi_boot_memmap(struct efi_system_table *systab,
23
-#include "loongarch_pic_common.c"
50
- void *p, void *start)
24
-static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
51
+static void efi_hdr_crc32(efi_table_hdr_t *hdr)
25
+static void loongarch_pic_realize(DeviceState *dev, Error **errp)
52
{
26
{
53
- unsigned i;
27
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
54
- struct efi_boot_memmap *boot_memmap = p;
28
- SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
55
- efi_guid_t tbl_guid = LINUX_EFI_BOOT_MEMMAP_GUID;
29
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
56
-
30
+ LoongarchPICClass *lpc = LOONGARCH_PIC_GET_CLASS(dev);
57
- /* efi_configuration_table 1 */
31
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
58
- guidcpy(&systab->tables[0].guid, &tbl_guid);
32
Error *local_err = NULL;
59
- systab->tables[0].table = (struct efi_configuration_table *)(p - start);
33
60
- systab->nr_tables = 1;
34
- loongarch_pic_common_realize(dev, &local_err);
61
-
35
+ lpc->parent_realize(dev, &local_err);
62
- boot_memmap->desc_size = sizeof(efi_memory_desc_t);
36
if (local_err) {
63
- boot_memmap->desc_ver = 1;
37
error_propagate(errp, local_err);
64
- boot_memmap->map_size = 0;
38
return;
65
+ uint32_t val;
39
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
66
40
67
- efi_memory_desc_t *map = p + sizeof(struct efi_boot_memmap);
68
- for (i = 0; i < memmap_entries; i++) {
69
- map = (void *)boot_memmap + sizeof(*map);
70
- map[i].type = memmap_table[i].type;
71
- map[i].phys_addr = ROUND_UP(memmap_table[i].address, 64 * KiB);
72
- map[i].num_pages = ROUND_DOWN(memmap_table[i].address +
73
- memmap_table[i].length - map[i].phys_addr, 64 * KiB);
74
- p += sizeof(efi_memory_desc_t);
75
- }
76
+ hdr->crc32 = 0;
77
+ val = crc32(0, (const unsigned char *)hdr, hdr->headersize);
78
+ hdr->crc32 = cpu_to_le32(val);
79
}
41
}
80
42
81
-static void init_efi_initrd_table(struct efi_system_table *systab,
43
-static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
82
- void *p, void *start)
44
+static void loongarch_pic_class_init(ObjectClass *klass, void *data)
83
+static void init_efi_vendor_string(void **p)
84
{
45
{
85
- efi_guid_t tbl_guid = LINUX_EFI_INITRD_MEDIA_GUID;
46
DeviceClass *dc = DEVICE_CLASS(klass);
86
- struct efi_initrd *initrd_table = p;
47
+ LoongarchPICClass *lpc = LOONGARCH_PIC_CLASS(klass);
87
+ uint16_t *vendor_str = *p;
48
88
49
- dc->realize = loongarch_pch_pic_realize;
89
- /* efi_configuration_table 2 */
50
device_class_set_legacy_reset(dc, loongarch_pch_pic_reset);
90
- guidcpy(&systab->tables[1].guid, &tbl_guid);
51
- dc->vmsd = &vmstate_loongarch_pic_common;
91
- systab->tables[1].table = (struct efi_configuration_table *)(p - start);
52
- device_class_set_props(dc, loongarch_pic_common_properties);
92
- systab->nr_tables = 2;
53
+ device_class_set_parent_realize(dc, loongarch_pic_realize,
93
+ /* QEMU in UTF16-LE */
54
+ &lpc->parent_realize);
94
+ stw_le_p(vendor_str++, 0x0051); /* Q */
95
+ stw_le_p(vendor_str++, 0x0045); /* E */
96
+ stw_le_p(vendor_str++, 0x004D); /* M */
97
+ stw_le_p(vendor_str++, 0x0055); /* U */
98
+ stw_le_p(vendor_str++, 0x0000); /* \0 */
99
100
- initrd_table->base = initrd_offset;
101
- initrd_table->size = initrd_size;
102
+ *p = vendor_str;
103
+ *p = QEMU_ALIGN_PTR_UP(*p, sizeof(target_long));
104
}
55
}
105
56
106
-static void init_efi_fdt_table(struct efi_system_table *systab)
57
-static const TypeInfo loongarch_pch_pic_info = {
107
+static void memmap_write_descs(efi_memory_desc_t *map)
58
- .name = TYPE_LOONGARCH_PCH_PIC,
108
{
59
- .parent = TYPE_SYS_BUS_DEVICE,
109
- efi_guid_t tbl_guid = DEVICE_TREE_GUID;
60
- .instance_size = sizeof(LoongArchPCHPIC),
110
-
61
- .class_init = loongarch_pch_pic_class_init,
111
- /* efi_configuration_table 3 */
62
+static const TypeInfo loongarch_pic_types[] = {
112
- guidcpy(&systab->tables[2].guid, &tbl_guid);
63
+ {
113
- systab->tables[2].table = (void *)FDT_BASE;
64
+ .name = TYPE_LOONGARCH_PIC,
114
- systab->nr_tables = 3;
65
+ .parent = TYPE_LOONGARCH_PIC_COMMON,
66
+ .instance_size = sizeof(LoongarchPICState),
67
+ .class_size = sizeof(LoongarchPICClass),
68
+ .class_init = loongarch_pic_class_init,
69
+ }
70
};
71
72
-static void loongarch_pch_pic_register_types(void)
73
-{
74
- type_register_static(&loongarch_pch_pic_info);
115
-}
75
-}
116
-
76
-
117
-static void init_systab(struct loongarch_boot_info *info, void *p, void *start)
77
-type_init(loongarch_pch_pic_register_types)
118
-{
78
+DEFINE_TYPES(loongarch_pic_types)
119
- void *bp_tables_start;
79
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
120
- struct efi_system_table *systab = p;
80
index XXXXXXX..XXXXXXX 100644
121
+ int i;
81
--- a/hw/intc/loongarch_pic_common.c
122
82
+++ b/hw/intc/loongarch_pic_common.c
123
- info->a2 = p - start;
83
@@ -XXX,XX +XXX,XX @@
124
+ for (i = 0; i < memmap_entries; i++) {
84
* Copyright (C) 2024 Loongson Technology Corporation Limited
125
+ uint32_t efi_type;
85
*/
126
+ hwaddr start = memmap_table[i].address;
86
127
+ hwaddr end = memmap_table[i].address + memmap_table[i].length;
87
+#include "qemu/osdep.h"
88
+#include "qapi/error.h"
89
+#include "hw/intc/loongarch_pic_common.h"
90
+#include "hw/qdev-properties.h"
91
+#include "migration/vmstate.h"
128
+
92
+
129
+ switch (memmap_table[i].type) {
93
static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
130
+ case MEMMAP_TYPE_MEMORY:
94
{
131
+ efi_type = EFI_CONVENTIONAL_MEMORY;
95
- LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
132
+ break;
96
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
133
+ case MEMMAP_TYPE_RESERVED:
97
134
+ efi_type = EFI_RESERVED_TYPE;
98
if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
135
+ break;
99
error_setg(errp, "Invalid 'pic_irq_num'");
136
+ case MEMMAP_TYPE_ACPI:
100
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_pic_common = {
137
+ efi_type = EFI_ACPI_RECLAIM_MEMORY;
101
VMSTATE_END_OF_LIST()
138
+ break;
102
}
139
+ case MEMMAP_TYPE_NVS:
103
};
140
+ efi_type = EFI_ACPI_MEMORY_NVS;
104
+
141
+ break;
105
+static void loongarch_pic_common_class_init(ObjectClass *klass, void *data)
142
+ default:
106
+{
143
+ efi_type = EFI_RESERVED_TYPE;
107
+ DeviceClass *dc = DEVICE_CLASS(klass);
144
+ break;
108
+ LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_CLASS(klass);
145
+ }
109
+
146
110
+ device_class_set_parent_realize(dc, loongarch_pic_common_realize,
147
- systab->hdr.signature = EFI_SYSTEM_TABLE_SIGNATURE;
111
+ &lpcc->parent_realize);
148
- systab->hdr.revision = EFI_SPECIFICATION_VERSION;
112
+ device_class_set_props(dc, loongarch_pic_common_properties);
149
- systab->hdr.revision = sizeof(struct efi_system_table),
113
+ dc->vmsd = &vmstate_loongarch_pic_common;
150
- systab->fw_revision = FW_VERSION << 16 | FW_PATCHLEVEL << 8;
114
+}
151
- systab->runtime = 0;
115
+
152
- systab->boottime = 0;
116
+static const TypeInfo loongarch_pic_common_types[] = {
153
- systab->nr_tables = 0;
117
+ {
154
+ if (memmap_table[i].reserved) {
118
+ .name = TYPE_LOONGARCH_PIC_COMMON,
155
+ start = QEMU_ALIGN_DOWN(start, EFI_PAGE_SIZE);
119
+ .parent = TYPE_SYS_BUS_DEVICE,
156
+ end = QEMU_ALIGN_UP(end, EFI_PAGE_SIZE);
120
+ .instance_size = sizeof(LoongArchPICCommonState),
157
+ } else {
121
+ .class_size = sizeof(LoongArchPICCommonClass),
158
+ start = QEMU_ALIGN_UP(start, EFI_PAGE_SIZE);
122
+ .class_init = loongarch_pic_common_class_init,
159
+ end = QEMU_ALIGN_DOWN(end, EFI_PAGE_SIZE);
123
+ .abstract = true,
160
+ }
161
162
- p += ROUND_UP(sizeof(struct efi_system_table), 64 * KiB);
163
+ map[i].type = cpu_to_le32(efi_type);
164
+ map[i].phys_addr = cpu_to_le64(start);
165
+ map[i].virt_addr = cpu_to_le64(start);
166
+ map[i].num_pages = cpu_to_le64((end - start) >> EFI_PAGE_SHIFT);
167
+ }
124
+ }
168
+}
125
+};
169
170
- systab->tables = p;
171
- bp_tables_start = p;
172
+#define EFI_BOOT_MEMMAP_TABLE_GEN(type) \
173
+static void init_efi_boot_memmap_##type(void *guidp, void **p) \
174
+{ \
175
+ struct efi_boot_memmap_##type *boot_memmap = *p; \
176
+ efi_guid_t tbl_guid = LINUX_EFI_BOOT_MEMMAP_GUID; \
177
+ \
178
+ /* efi_configuration_table 1 */ \
179
+ guidcpy(guidp, &tbl_guid); \
180
+ \
181
+ boot_memmap->desc_size = cpu_to_le##type(sizeof(efi_memory_desc_t)); \
182
+ boot_memmap->desc_ver = cpu_to_le32(1); \
183
+ boot_memmap->map_size = cpu_to_le##type(boot_memmap->desc_size * \
184
+ memmap_entries); \
185
+ memmap_write_descs(boot_memmap->map); \
186
+ *p += sizeof(struct efi_boot_memmap_##type); \
187
+}
188
189
- init_efi_boot_memmap(systab, p, start);
190
- p += ROUND_UP(sizeof(struct efi_boot_memmap) +
191
- sizeof(efi_memory_desc_t) * memmap_entries, 64 * KiB);
192
- init_efi_initrd_table(systab, p, start);
193
- p += ROUND_UP(sizeof(struct efi_initrd), 64 * KiB);
194
- init_efi_fdt_table(systab);
195
+#define EFI_INITRD_TABLE_GEN(type) \
196
+static void init_efi_initrd_table_##type(void *guidp, void **p) \
197
+{ \
198
+ efi_guid_t tbl_guid = LINUX_EFI_INITRD_MEDIA_GUID; \
199
+ struct efi_initrd_##type *initrd_table = *p; \
200
+ \
201
+ /* efi_configuration_table */ \
202
+ guidcpy(guidp, &tbl_guid); \
203
+ \
204
+ initrd_table->base = cpu_to_le##type(initrd_offset); \
205
+ initrd_table->size = cpu_to_le##type(initrd_size); \
206
+ *p += sizeof(struct efi_initrd_##type); \
207
+}
208
209
- systab->tables = (struct efi_configuration_table *)(bp_tables_start - start);
210
+#define BOOTP_ALIGN_PTR_UP(p, s, n) \
211
+ ((typeof(p))((uintptr_t)(s) + \
212
+ QEMU_ALIGN_UP((uintptr_t)(p) - (uintptr_t)(s), n)))
213
+
126
+
214
+#define EFI_INIT_SYSTAB_GEN(type) \
127
+DEFINE_TYPES(loongarch_pic_common_types)
215
+ EFI_BOOT_MEMMAP_TABLE_GEN(type) \
128
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
216
+ EFI_INITRD_TABLE_GEN(type) \
129
index XXXXXXX..XXXXXXX 100644
217
+static void init_systab_##type(struct loongarch_boot_info *info, \
130
--- a/hw/intc/meson.build
218
+ void *p, void *start) \
131
+++ b/hw/intc/meson.build
219
+{ \
132
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
220
+ uint32_t nr_tables = 0; \
133
specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c'))
221
+ const efi_guid_t fdt_guid = DEVICE_TREE_GUID; \
134
specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c'))
222
+ struct efi_system_table_##type *systab; \
135
specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
223
+ struct efi_configuration_table_##type *cfg_tabs; \
136
-specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
224
+ \
137
+specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c', 'loongarch_pic_common.c'))
225
+ p = BOOTP_ALIGN_PTR_UP(p, start, EFI_TABLE_ALIGN); \
138
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
226
+ systab = p; \
139
specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c'))
227
+ info->a2 = p - start; \
140
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
228
+ \
141
index XXXXXXX..XXXXXXX 100644
229
+ systab->hdr.signature = cpu_to_le64(EFI_SYSTEM_TABLE_SIGNATURE); \
142
--- a/include/hw/intc/loongarch_pch_pic.h
230
+ systab->hdr.revision = cpu_to_le32(EFI_SPECIFICATION_VERSION); \
143
+++ b/include/hw/intc/loongarch_pch_pic.h
231
+ systab->hdr.headersize = \
144
@@ -XXX,XX +XXX,XX @@
232
+ cpu_to_le32(sizeof(struct efi_system_table_##type)); \
145
233
+ systab->fw_revision = \
146
#include "hw/intc/loongarch_pic_common.h"
234
+ cpu_to_le32(FW_VERSION << 16 | FW_PATCHLEVEL << 8); \
147
235
+ systab->runtime = 0; \
148
-#define LoongArchPCHPIC LoongArchPICCommonState
236
+ systab->boottime = 0; \
149
-#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
237
+ systab->nr_tables = 0; \
150
-#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
238
+ \
151
-OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
239
+ p += sizeof(struct efi_system_table_##type); \
152
+#define TYPE_LOONGARCH_PIC "loongarch_pic"
240
+ systab->fw_vendor = cpu_to_le##type(p - start); \
153
+#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PIC#name
241
+ init_efi_vendor_string(&p); \
154
+OBJECT_DECLARE_TYPE(LoongarchPICState, LoongarchPICClass, LOONGARCH_PIC)
242
+ \
243
+ p = BOOTP_ALIGN_PTR_UP(p, start, EFI_TABLE_ALIGN); \
244
+ systab->tables = cpu_to_le##type(p - start); \
245
+ cfg_tabs = p; \
246
+ p += sizeof(struct efi_configuration_table_##type) * 3; \
247
+ \
248
+ p = BOOTP_ALIGN_PTR_UP(p, start, EFI_TABLE_ALIGN); \
249
+ cfg_tabs[nr_tables].table = cpu_to_le##type(p - start); \
250
+ init_efi_boot_memmap_##type(&cfg_tabs[nr_tables].guid, &p); \
251
+ nr_tables++; \
252
+ \
253
+ if (initrd_size > 0) { \
254
+ cfg_tabs[nr_tables].table = cpu_to_le##type(p - start); \
255
+ init_efi_initrd_table_##type(&cfg_tabs[nr_tables].guid, &p); \
256
+ nr_tables++; \
257
+ } \
258
+ \
259
+ guidcpy(&cfg_tabs[nr_tables].guid, &fdt_guid); \
260
+ cfg_tabs[nr_tables].table = cpu_to_le##type(FDT_BASE); \
261
+ nr_tables++; \
262
+ \
263
+ systab->nr_tables = cpu_to_le32(nr_tables); \
264
+ efi_hdr_crc32(&systab->hdr); \
265
}
266
267
+EFI_INIT_SYSTAB_GEN(32)
268
+EFI_INIT_SYSTAB_GEN(64)
269
+
155
+
270
static void init_cmdline(struct loongarch_boot_info *info, void *p, void *start)
156
+struct LoongarchPICState {
271
{
157
+ LoongArchPICCommonState parent_obj;
272
hwaddr cmdline_addr = p - start;
158
+};
273
@@ -XXX,XX +XXX,XX @@ static void reset_load_elf(void *opaque)
159
+
274
160
+struct LoongarchPICClass {
275
cpu_reset(CPU(cpu));
161
+ LoongArchPICCommonClass parent_class;
276
if (env->load_elf) {
162
+
277
-    if (cpu == LOONGARCH_CPU(first_cpu)) {
163
+ DeviceRealize parent_realize;
278
+ if (cpu == LOONGARCH_CPU(first_cpu)) {
164
+};
279
env->gpr[4] = env->boot_info->a0;
165
+
280
env->gpr[5] = env->boot_info->a1;
166
+#define TYPE_LOONGARCH_PCH_PIC TYPE_LOONGARCH_PIC
281
env->gpr[6] = env->boot_info->a2;
167
+typedef struct LoongArchPICCommonState LoongArchPCHPIC;
282
@@ -XXX,XX +XXX,XX @@ static void loongarch_firmware_boot(LoongArchVirtMachineState *lvms,
168
+#define LOONGARCH_PCH_PIC(obj) ((struct LoongArchPICCommonState *)(obj))
283
fw_cfg_add_kernel_info(info, lvms->fw_cfg);
169
284
}
170
#endif /* HW_LOONGARCH_PCH_PIC_H */
285
171
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
286
-static void init_boot_rom(struct loongarch_boot_info *info, void *p)
287
+static void init_boot_rom(struct loongarch_boot_info *info, void *p,
288
+ bool is_64bit)
289
{
290
void *start = p;
291
292
init_cmdline(info, p, start);
293
p += COMMAND_LINE_SIZE;
294
295
- init_systab(info, p, start);
296
+ if (is_64bit)
297
+ init_systab_64(info, p, start);
298
+ else
299
+ init_systab_32(info, p, start);
300
}
301
302
static void loongarch_direct_kernel_boot(struct loongarch_boot_info *info)
303
{
304
void *p, *bp;
305
int64_t kernel_addr = 0;
306
- LoongArchCPU *lacpu;
307
+ LoongArchCPU *lacpu = LOONGARCH_CPU(first_cpu);
308
CPUState *cs;
309
310
if (info->kernel_filename) {
311
@@ -XXX,XX +XXX,XX @@ static void loongarch_direct_kernel_boot(struct loongarch_boot_info *info)
312
/* Load cmdline and system tables at [0 - 1 MiB] */
313
p = g_malloc0(1 * MiB);
314
bp = p;
315
- init_boot_rom(info, p);
316
+ init_boot_rom(info, p, is_la64(&lacpu->env));
317
rom_add_blob_fixed_as("boot_info", bp, 1 * MiB, 0, &address_space_memory);
318
319
/* Load slave boot code at pflash0 . */
320
diff --git a/include/hw/loongarch/boot.h b/include/hw/loongarch/boot.h
321
index XXXXXXX..XXXXXXX 100644
172
index XXXXXXX..XXXXXXX 100644
322
--- a/include/hw/loongarch/boot.h
173
--- a/include/hw/intc/loongarch_pic_common.h
323
+++ b/include/hw/loongarch/boot.h
174
+++ b/include/hw/intc/loongarch_pic_common.h
324
@@ -XXX,XX +XXX,XX @@ typedef struct {
175
@@ -XXX,XX +XXX,XX @@
325
EFI_GUID(0xb1b621d5, 0xf19c, 0x41a5, 0x83, 0x0b, \
176
#define POL_LO_START 0x40
326
0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0)
177
#define POL_HI_START 0x44
327
178
328
+/* Memory types: */
179
+#define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common"
329
+#define EFI_RESERVED_TYPE 0
180
+OBJECT_DECLARE_TYPE(LoongArchPICCommonState,
330
+#define EFI_LOADER_CODE 1
181
+ LoongArchPICCommonClass, LOONGARCH_PIC_COMMON)
331
+#define EFI_LOADER_DATA 2
332
+#define EFI_BOOT_SERVICES_CODE 3
333
+#define EFI_BOOT_SERVICES_DATA 4
334
+#define EFI_RUNTIME_SERVICES_CODE 5
335
+#define EFI_RUNTIME_SERVICES_DATA 6
336
+#define EFI_CONVENTIONAL_MEMORY 7
337
+#define EFI_UNUSABLE_MEMORY 8
338
+#define EFI_ACPI_RECLAIM_MEMORY 9
339
+#define EFI_ACPI_MEMORY_NVS 10
340
+#define EFI_MEMORY_MAPPED_IO 11
341
+#define EFI_MEMORY_MAPPED_IO_PORT_SPACE 12
342
+#define EFI_PAL_CODE 13
343
+#define EFI_PERSISTENT_MEMORY 14
344
+#define EFI_UNACCEPTED_MEMORY 15
345
+#define EFI_MAX_MEMORY_TYPE 16
346
+
182
+
347
+#define EFI_PAGE_SHIFT 12
183
struct LoongArchPICCommonState {
348
+#define EFI_PAGE_SIZE (1UL << EFI_PAGE_SHIFT)
184
SysBusDevice parent_obj;
185
186
@@ -XXX,XX +XXX,XX @@ struct LoongArchPICCommonState {
187
MemoryRegion iomem8;
188
unsigned int irq_num;
189
};
349
+
190
+
350
+#define EFI_TABLE_ALIGN (64 * KiB)
191
+struct LoongArchPICCommonClass {
192
+ SysBusDeviceClass parent_class;
351
+
193
+
352
struct efi_config_table {
194
+ DeviceRealize parent_realize;
353
efi_guid_t guid;
195
+};
354
uint64_t *ptr;
196
#endif /* HW_LOONGARCH_PIC_COMMON_H */
355
const char name[16];
356
-};
357
+} QEMU_PACKED;
358
359
typedef struct {
360
uint64_t signature;
361
@@ -XXX,XX +XXX,XX @@ typedef struct {
362
uint32_t headersize;
363
uint32_t crc32;
364
uint32_t reserved;
365
-} efi_table_hdr_t;
366
+} QEMU_PACKED efi_table_hdr_t;
367
368
-struct efi_configuration_table {
369
+struct efi_configuration_table_32 {
370
efi_guid_t guid;
371
- void *table;
372
-};
373
+ uint32_t table;
374
+} QEMU_PACKED;
375
376
-struct efi_system_table {
377
+struct efi_configuration_table_64 {
378
+ efi_guid_t guid;
379
+ uint64_t table;
380
+} QEMU_PACKED;
381
+
382
+struct efi_system_table_32 {
383
+ efi_table_hdr_t hdr;
384
+ uint32_t fw_vendor; /* physical addr of CHAR16 vendor string */
385
+ uint32_t fw_revision;
386
+ uint32_t con_in_handle;
387
+ uint32_t con_in;
388
+ uint32_t con_out_handle;
389
+ uint32_t con_out;
390
+ uint32_t stderr_handle;
391
+ uint32_t stderr_placeholder;
392
+ uint32_t runtime;
393
+ uint32_t boottime;
394
+ uint32_t nr_tables;
395
+ uint32_t tables;
396
+} QEMU_PACKED;
397
+
398
+struct efi_system_table_64 {
399
efi_table_hdr_t hdr;
400
uint64_t fw_vendor; /* physical addr of CHAR16 vendor string */
401
uint32_t fw_revision;
402
+ uint32_t __pad1;
403
uint64_t con_in_handle;
404
- uint64_t *con_in;
405
+ uint64_t con_in;
406
uint64_t con_out_handle;
407
- uint64_t *con_out;
408
+ uint64_t con_out;
409
uint64_t stderr_handle;
410
uint64_t stderr_placeholder;
411
- uint64_t *runtime;
412
- uint64_t *boottime;
413
- uint64_t nr_tables;
414
- struct efi_configuration_table *tables;
415
-};
416
+ uint64_t runtime;
417
+ uint64_t boottime;
418
+ uint32_t nr_tables;
419
+ uint32_t __pad2;
420
+ uint64_t tables;
421
+} QEMU_PACKED;
422
423
typedef struct {
424
uint32_t type;
425
- uint32_t pad;
426
+ uint32_t __pad;
427
uint64_t phys_addr;
428
uint64_t virt_addr;
429
uint64_t num_pages;
430
uint64_t attribute;
431
-} efi_memory_desc_t;
432
+} QEMU_PACKED efi_memory_desc_t;
433
+
434
+struct efi_boot_memmap_32 {
435
+ uint32_t map_size;
436
+ uint32_t desc_size;
437
+ uint32_t desc_ver;
438
+ uint32_t map_key;
439
+ uint32_t buff_size;
440
+ uint32_t __pad;
441
+ efi_memory_desc_t map[32];
442
+} QEMU_PACKED;
443
444
-struct efi_boot_memmap {
445
+struct efi_boot_memmap_64 {
446
uint64_t map_size;
447
uint64_t desc_size;
448
uint32_t desc_ver;
449
+ uint32_t __pad;
450
uint64_t map_key;
451
uint64_t buff_size;
452
efi_memory_desc_t map[32];
453
-};
454
+} QEMU_PACKED;
455
+
456
+struct efi_initrd_32 {
457
+ uint32_t base;
458
+ uint32_t size;
459
+} QEMU_PACKED;
460
461
-struct efi_initrd {
462
+struct efi_initrd_64 {
463
uint64_t base;
464
uint64_t size;
465
-};
466
+} QEMU_PACKED;
467
468
struct loongarch_boot_info {
469
uint64_t ram_size;
470
@@ -XXX,XX +XXX,XX @@ extern unsigned memmap_entries;
471
struct memmap_entry {
472
uint64_t address;
473
uint64_t length;
474
+ /* E820 style type */
475
+#define MEMMAP_TYPE_MEMORY 1
476
+#define MEMMAP_TYPE_RESERVED 2
477
+#define MEMMAP_TYPE_ACPI 3
478
+#define MEMMAP_TYPE_NVS 4
479
uint32_t type;
480
uint32_t reserved;
481
};
482
--
197
--
483
2.34.1
198
2.43.5
diff view generated by jsdifflib
[PULL 4/7] hw/loongarch/boot: Rework boot code generation
[PULL 07/18] hw/intc/loongarch_pch: Add pre_save and post_load interfaces
1
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
1
Add vmstate pre_save and post_load interfaces, which can be used
2
by pic kvm driver in future.
2
3
3
Use stl_p to write instructions so that host endian conversion
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
will be performed.
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
---
7
hw/intc/loongarch_pic_common.c | 26 ++++++++++++++++++++++++++
8
include/hw/intc/loongarch_pic_common.h | 2 ++
9
2 files changed, 28 insertions(+)
5
10
6
Replace mailbox read/write on LoongArch32 systems with 32bit IOCSR
11
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
7
instructions to prevent illegal instructions.
8
9
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
10
Reviewed-by: Song Gao <gaosong@loongson.cn>
11
Message-Id: <20240914-loongarch-booting-v1-2-1517cae11c10@flygoat.com>
12
Signed-off-by: Song Gao <gaosong@loongson.cn>
13
---
14
hw/loongarch/boot.c | 107 ++++++++++++++++++++++++--------------------
15
1 file changed, 59 insertions(+), 48 deletions(-)
16
17
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
18
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/loongarch/boot.c
13
--- a/hw/intc/loongarch_pic_common.c
20
+++ b/hw/loongarch/boot.c
14
+++ b/hw/intc/loongarch_pic_common.c
21
@@ -XXX,XX +XXX,XX @@ unsigned memmap_entries;
15
@@ -XXX,XX +XXX,XX @@
22
ram_addr_t initrd_offset;
16
#include "hw/qdev-properties.h"
23
uint64_t initrd_size;
17
#include "migration/vmstate.h"
24
18
25
-static const unsigned int slave_boot_code[] = {
19
+static int loongarch_pic_pre_save(void *opaque)
26
- /* Configure reset ebase. */
27
- 0x0400302c, /* csrwr $t0, LOONGARCH_CSR_EENTRY */
28
-
29
- /* Disable interrupt. */
30
- 0x0380100c, /* ori $t0, $zero,0x4 */
31
- 0x04000180, /* csrxchg $zero, $t0, LOONGARCH_CSR_CRMD */
32
-
33
- /* Clear mailbox. */
34
- 0x1400002d, /* lu12i.w $t1, 1(0x1) */
35
- 0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */
36
- 0x06481da0, /* iocsrwr.d $zero, $t1 */
37
-
38
- /* Enable IPI interrupt. */
39
- 0x1400002c, /* lu12i.w $t0, 1(0x1) */
40
- 0x0400118c, /* csrxchg $t0, $t0, LOONGARCH_CSR_ECFG */
41
- 0x02fffc0c, /* addi.d $t0, $r0,-1(0xfff) */
42
- 0x1400002d, /* lu12i.w $t1, 1(0x1) */
43
- 0x038011ad, /* ori $t1, $t1, CORE_EN_OFF */
44
- 0x064819ac, /* iocsrwr.w $t0, $t1 */
45
- 0x1400002d, /* lu12i.w $t1, 1(0x1) */
46
- 0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */
47
-
48
- /* Wait for wakeup <.L11>: */
49
- 0x06488000, /* idle 0x0 */
50
- 0x03400000, /* andi $zero, $zero, 0x0 */
51
- 0x064809ac, /* iocsrrd.w $t0, $t1 */
52
- 0x43fff59f, /* beqz $t0, -12(0x7ffff4) # 48 <.L11> */
53
-
54
- /* Read and clear IPI interrupt. */
55
- 0x1400002d, /* lu12i.w $t1, 1(0x1) */
56
- 0x064809ac, /* iocsrrd.w $t0, $t1 */
57
- 0x1400002d, /* lu12i.w $t1, 1(0x1) */
58
- 0x038031ad, /* ori $t1, $t1, CORE_CLEAR_OFF */
59
- 0x064819ac, /* iocsrwr.w $t0, $t1 */
60
-
61
- /* Disable IPI interrupt. */
62
- 0x1400002c, /* lu12i.w $t0, 1(0x1) */
63
- 0x04001180, /* csrxchg $zero, $t0, LOONGARCH_CSR_ECFG */
64
-
65
- /* Read mail buf and jump to specified entry */
66
- 0x1400002d, /* lu12i.w $t1, 1(0x1) */
67
- 0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */
68
- 0x06480dac, /* iocsrrd.d $t0, $t1 */
69
- 0x00150181, /* move $ra, $t0 */
70
- 0x4c000020, /* jirl $zero, $ra,0 */
71
-};
72
+static void generate_secondary_boot_code(void *boot_code, bool is_64bit)
73
+{
20
+{
74
+ uint32_t *p = boot_code;
21
+ LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
22
+ LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
75
+
23
+
76
+ /* Configure reset ebase. */
24
+ if (lpcc->pre_save) {
77
+ stl_p(p++, 0x0400302c); /* csrwr $t0, LOONGARCH_CSR_EENTRY */
25
+ return lpcc->pre_save(s);
78
+
79
+ /* Disable interrupt. */
80
+ stl_p(p++, 0x0380100c); /* ori $t0, $zero,0x4 */
81
+ stl_p(p++, 0x04000180); /* csrxchg $zero, $t0, LOONGARCH_CSR_CRMD */
82
+
83
+ /* Clear mailbox. */
84
+ stl_p(p++, 0x1400002d); /* lu12i.w $t1, 1(0x1) */
85
+ stl_p(p++, 0x038081ad); /* ori $t1, $t1, CORE_BUF_20 */
86
+ if (is_64bit) {
87
+ stl_p(p++, 0x06481da0); /* iocsrwr.d $zero, $t1 */
88
+ } else {
89
+ stl_p(p++, 0x064819a0); /* iocsrwr.w $zero, $t1 */
90
+ }
26
+ }
91
+
27
+
92
+ /* Enable IPI interrupt. */
28
+ return 0;
93
+ stl_p(p++, 0x1400002c); /* lu12i.w $t0, 1(0x1) */
29
+}
94
+ stl_p(p++, 0x0400118c); /* csrxchg $t0, $t0, LOONGARCH_CSR_ECFG */
95
+ stl_p(p++, 0x02fffc0c); /* addi.d $t0, $r0, -1(0xfff) */
96
+ stl_p(p++, 0x1400002d); /* lu12i.w $t1, 1(0x1) */
97
+ stl_p(p++, 0x038011ad); /* ori $t1, $t1, CORE_EN_OFF */
98
+ stl_p(p++, 0x064819ac); /* iocsrwr.w $t0, $t1 */
99
+ stl_p(p++, 0x1400002d); /* lu12i.w $t1, 1(0x1) */
100
+ stl_p(p++, 0x038081ad); /* ori $t1, $t1, CORE_BUF_20 */
101
+
30
+
102
+ /* Wait for wakeup <.L11>: */
31
+static int loongarch_pic_post_load(void *opaque, int version_id)
103
+ stl_p(p++, 0x06488000); /* idle 0x0 */
32
+{
104
+ stl_p(p++, 0x03400000); /* andi $zero, $zero, 0x0 */
33
+ LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
105
+ stl_p(p++, 0x064809ac); /* iocsrrd.w $t0, $t1 */
34
+ LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
106
+ stl_p(p++, 0x43fff59f); /* beqz $t0, -12(0x7ffff4) # 48 <.L11> */
107
+
35
+
108
+ /* Read and clear IPI interrupt. */
36
+ if (lpcc->post_load) {
109
+ stl_p(p++, 0x1400002d); /* lu12i.w $t1, 1(0x1) */
37
+ return lpcc->post_load(s, version_id);
110
+ stl_p(p++, 0x064809ac); /* iocsrrd.w $t0, $t1 */
38
+ }
111
+ stl_p(p++, 0x1400002d); /* lu12i.w $t1, 1(0x1) */
112
+ stl_p(p++, 0x038031ad); /* ori $t1, $t1, CORE_CLEAR_OFF */
113
+ stl_p(p++, 0x064819ac); /* iocsrwr.w $t0, $t1 */
114
+
39
+
115
+ /* Disable IPI interrupt. */
40
+ return 0;
116
+ stl_p(p++, 0x1400002c); /* lu12i.w $t0, 1(0x1) */
41
+}
117
+ stl_p(p++, 0x04001180); /* csrxchg $zero, $t0, LOONGARCH_CSR_ECFG */
118
+
42
+
119
+ /* Read mail buf and jump to specified entry. */
43
static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
120
+ stl_p(p++, 0x1400002d); /* lu12i.w $t1, 1(0x1) */
121
+ stl_p(p++, 0x038081ad); /* ori $t1, $t1, CORE_BUF_20 */
122
+ if (is_64bit) {
123
+ stl_p(p++, 0x06480dac); /* iocsrrd.d $t0, $t1 */
124
+ } else {
125
+ stl_p(p++, 0x064809ac); /* iocsrrd.w $t0, $t1 */
126
+ }
127
+ stl_p(p++, 0x00150181); /* move $ra, $t0 */
128
+ stl_p(p++, 0x4c000020); /* jirl $zero, $ra, 0 */
129
+}
130
131
static inline void *guidcpy(void *dst, const void *src)
132
{
44
{
133
@@ -XXX,XX +XXX,XX @@ static void loongarch_direct_kernel_boot(struct loongarch_boot_info *info)
45
LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
134
46
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_pic_common = {
135
/* Load slave boot code at pflash0 . */
47
.name = "loongarch_pch_pic",
136
void *boot_code = g_malloc0(VIRT_FLASH0_SIZE);
48
.version_id = 1,
137
- memcpy(boot_code, &slave_boot_code, sizeof(slave_boot_code));
49
.minimum_version_id = 1,
138
+ generate_secondary_boot_code(boot_code, is_la64(&lacpu->env));
50
+ .pre_save = loongarch_pic_pre_save,
139
rom_add_blob_fixed("boot_code", boot_code, VIRT_FLASH0_SIZE, VIRT_FLASH0_BASE);
51
+ .post_load = loongarch_pic_post_load,
140
52
.fields = (const VMStateField[]) {
141
CPU_FOREACH(cs) {
53
VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
54
VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
55
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
56
index XXXXXXX..XXXXXXX 100644
57
--- a/include/hw/intc/loongarch_pic_common.h
58
+++ b/include/hw/intc/loongarch_pic_common.h
59
@@ -XXX,XX +XXX,XX @@ struct LoongArchPICCommonClass {
60
SysBusDeviceClass parent_class;
61
62
DeviceRealize parent_realize;
63
+ int (*pre_save)(LoongArchPICCommonState *s);
64
+ int (*post_load)(LoongArchPICCommonState *s, int version_id);
65
};
66
#endif /* HW_LOONGARCH_PIC_COMMON_H */
142
--
67
--
143
2.34.1
68
2.43.5
diff view generated by jsdifflib
[PULL 2/7] hw/loongarch/virt: Add FDT table support with acpi ged pm register
[PULL 08/18] hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic
1
From: Bibo Mao <maobibo@loongson.cn>
1
Remove definition about LoongArchPCHPIC and LOONGARCH_PCH_PIC, and
2
2
replace them with LoongArchPICCommonState and LOONGARCH_PIC_COMMON
3
ACPI ged is used for power management on LoongArch virt platform, in
3
separately. Also remove unnecessary header files.
4
general it is parsed from acpi table. However if system boot directly from
5
elf kernel, no UEFI bios is provided and acpi table cannot be used also.
6
7
Here acpi ged pm register is exposed with FDT table, it is compatbile
8
with syscon method in FDT table, only that acpi ged pm register is accessed
9
with 8-bit mode, rather with 32-bit mode.
10
4
11
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
12
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
13
Tested-by: Song Gao <gaosong@loongson.cn>
14
Message-Id: <20240918014206.2165821-3-maobibo@loongson.cn>
15
Signed-off-by: Song Gao <gaosong@loongson.cn>
16
---
7
---
17
hw/loongarch/virt.c | 39 +++++++++++++++++++++++++++++++++++++++
8
hw/intc/loongarch_pch_pic.c | 24 ++++++++++--------------
18
1 file changed, 39 insertions(+)
9
hw/loongarch/virt.c | 2 +-
10
include/hw/intc/loongarch_pch_pic.h | 4 ----
11
3 files changed, 11 insertions(+), 19 deletions(-)
19
12
13
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/loongarch_pch_pic.c
16
+++ b/hw/intc/loongarch_pch_pic.c
17
@@ -XXX,XX +XXX,XX @@
18
19
#include "qemu/osdep.h"
20
#include "qemu/bitops.h"
21
-#include "hw/sysbus.h"
22
-#include "hw/loongarch/virt.h"
23
-#include "hw/pci-host/ls7a.h"
24
#include "hw/irq.h"
25
#include "hw/intc/loongarch_pch_pic.h"
26
-#include "hw/qdev-properties.h"
27
-#include "migration/vmstate.h"
28
#include "trace.h"
29
#include "qapi/error.h"
30
31
-static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
32
+static void pch_pic_update_irq(LoongArchPICCommonState *s, uint64_t mask,
33
+ int level)
34
{
35
uint64_t val;
36
int irq;
37
@@ -XXX,XX +XXX,XX @@ static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
38
39
static void pch_pic_irq_handler(void *opaque, int irq, int level)
40
{
41
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
42
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
43
uint64_t mask = 1ULL << irq;
44
45
assert(irq < s->irq_num);
46
@@ -XXX,XX +XXX,XX @@ static void pch_pic_irq_handler(void *opaque, int irq, int level)
47
static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,
48
unsigned size)
49
{
50
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
51
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
52
uint64_t val = 0;
53
uint32_t offset = addr & 0xfff;
54
55
@@ -XXX,XX +XXX,XX @@ static uint64_t get_writew_val(uint64_t value, uint32_t target, bool hi)
56
static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
57
uint64_t value, unsigned size)
58
{
59
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
60
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
61
uint32_t offset, old_valid, data = (uint32_t)value;
62
uint64_t old, int_mask;
63
offset = addr & 0xfff;
64
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
65
static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
66
unsigned size)
67
{
68
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
69
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
70
uint64_t val = 0;
71
uint32_t offset = addr & 0xfff;
72
73
@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
74
static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
75
uint64_t value, unsigned size)
76
{
77
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
78
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
79
uint32_t offset, data = (uint32_t)value;
80
offset = addr & 0xfff;
81
82
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
83
static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
84
unsigned size)
85
{
86
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
87
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
88
uint64_t val = 0;
89
uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
90
int64_t offset_tmp;
91
@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
92
static void loongarch_pch_pic_writeb(void *opaque, hwaddr addr,
93
uint64_t data, unsigned size)
94
{
95
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
96
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
97
int32_t offset_tmp;
98
uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
99
100
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps loongarch_pch_pic_reg8_ops = {
101
102
static void loongarch_pch_pic_reset(DeviceState *d)
103
{
104
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(d);
105
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(d);
106
int i;
107
108
s->int_mask = -1;
20
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
109
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
21
index XXXXXXX..XXXXXXX 100644
110
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/loongarch/virt.c
111
--- a/hw/loongarch/virt.c
23
+++ b/hw/loongarch/virt.c
112
+++ b/hw/loongarch/virt.c
24
@@ -XXX,XX +XXX,XX @@ static void fdt_add_rtc_node(LoongArchVirtMachineState *lvms,
113
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
25
g_free(nodename);
114
/* Add Extend I/O Interrupt Controller node */
26
}
115
fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
27
116
28
+static void fdt_add_ged_reset(LoongArchVirtMachineState *lvms)
117
- pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
29
+{
118
+ pch_pic = qdev_new(TYPE_LOONGARCH_PIC);
30
+ char *name;
119
num = VIRT_PCH_PIC_IRQ_NUM;
31
+ uint32_t ged_handle;
120
qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
32
+ MachineState *ms = MACHINE(lvms);
121
d = SYS_BUS_DEVICE(pch_pic);
33
+ hwaddr base = VIRT_GED_REG_ADDR;
122
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
34
+ hwaddr size = ACPI_GED_REG_COUNT;
123
index XXXXXXX..XXXXXXX 100644
35
+
124
--- a/include/hw/intc/loongarch_pch_pic.h
36
+ ged_handle = qemu_fdt_alloc_phandle(ms->fdt);
125
+++ b/include/hw/intc/loongarch_pch_pic.h
37
+ name = g_strdup_printf("/ged@%" PRIx64, base);
126
@@ -XXX,XX +XXX,XX @@ struct LoongarchPICClass {
38
+ qemu_fdt_add_subnode(ms->fdt, name);
127
DeviceRealize parent_realize;
39
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon");
128
};
40
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, base, 0x0, size);
129
41
+ /* 8 bit registers */
130
-#define TYPE_LOONGARCH_PCH_PIC TYPE_LOONGARCH_PIC
42
+ qemu_fdt_setprop_cell(ms->fdt, name, "reg-shift", 0);
131
-typedef struct LoongArchPICCommonState LoongArchPCHPIC;
43
+ qemu_fdt_setprop_cell(ms->fdt, name, "reg-io-width", 1);
132
-#define LOONGARCH_PCH_PIC(obj) ((struct LoongArchPICCommonState *)(obj))
44
+ qemu_fdt_setprop_cell(ms->fdt, name, "phandle", ged_handle);
133
-
45
+ ged_handle = qemu_fdt_get_phandle(ms->fdt, name);
134
#endif /* HW_LOONGARCH_PCH_PIC_H */
46
+ g_free(name);
47
+
48
+ name = g_strdup_printf("/reboot");
49
+ qemu_fdt_add_subnode(ms->fdt, name);
50
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot");
51
+ qemu_fdt_setprop_cell(ms->fdt, name, "regmap", ged_handle);
52
+ qemu_fdt_setprop_cell(ms->fdt, name, "offset", ACPI_GED_REG_RESET);
53
+ qemu_fdt_setprop_cell(ms->fdt, name, "value", ACPI_GED_RESET_VALUE);
54
+ g_free(name);
55
+
56
+ name = g_strdup_printf("/poweroff");
57
+ qemu_fdt_add_subnode(ms->fdt, name);
58
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff");
59
+ qemu_fdt_setprop_cell(ms->fdt, name, "regmap", ged_handle);
60
+ qemu_fdt_setprop_cell(ms->fdt, name, "offset", ACPI_GED_REG_SLEEP_CTL);
61
+ qemu_fdt_setprop_cell(ms->fdt, name, "value", ACPI_GED_SLP_EN |
62
+ (ACPI_GED_SLP_TYP_S5 << ACPI_GED_SLP_TYP_POS));
63
+ g_free(name);
64
+}
65
+
66
static void fdt_add_uart_node(LoongArchVirtMachineState *lvms,
67
uint32_t *pch_pic_phandle, hwaddr base,
68
int irq, bool chosen)
69
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
70
qdev_get_gpio_in(pch_pic,
71
VIRT_RTC_IRQ - VIRT_GSI_BASE));
72
fdt_add_rtc_node(lvms, pch_pic_phandle);
73
+ fdt_add_ged_reset(lvms);
74
75
/* acpi ged */
76
lvms->acpi_ged = create_acpi_ged(pch_pic, lvms);
77
--
135
--
78
2.34.1
136
2.43.5
diff view generated by jsdifflib
[PULL 6/7] hw/loongarch/virt: Remove unnecessary 'cpu.h' inclusion
[PULL 09/18] include: Add loongarch_extioi_common header file
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
Add common header file include/hw/intc/loongarch_extioi_common.h, and
2
move some macro definition from include/hw/intc/loongarch_extioi.h to
3
the common header file.
2
4
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
5
Message-Id: <20240927213254.17552-2-philmd@linaro.org>
6
Signed-off-by: Song Gao <gaosong@loongson.cn>
7
---
7
---
8
include/hw/loongarch/virt.h | 1 -
8
include/hw/intc/loongarch_extioi.h | 50 +------------------
9
1 file changed, 1 deletion(-)
9
include/hw/intc/loongarch_extioi_common.h | 58 +++++++++++++++++++++++
10
2 files changed, 59 insertions(+), 49 deletions(-)
11
create mode 100644 include/hw/intc/loongarch_extioi_common.h
10
12
11
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
13
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/loongarch/virt.h
15
--- a/include/hw/intc/loongarch_extioi.h
14
+++ b/include/hw/loongarch/virt.h
16
+++ b/include/hw/intc/loongarch_extioi.h
15
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@
16
#ifndef HW_LOONGARCH_H
18
* Copyright (C) 2021 Loongson Technology Corporation Limited
17
#define HW_LOONGARCH_H
19
*/
18
20
19
-#include "target/loongarch/cpu.h"
21
-#include "hw/sysbus.h"
20
#include "hw/boards.h"
22
-#include "hw/loongarch/virt.h"
21
#include "qemu/queue.h"
23
-
22
#include "hw/block/flash.h"
24
#ifndef LOONGARCH_EXTIOI_H
25
#define LOONGARCH_EXTIOI_H
26
27
-#define LS3A_INTC_IP 8
28
-#define EXTIOI_IRQS (256)
29
-#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
30
-/* irq from EXTIOI is routed to no more than 4 cpus */
31
-#define EXTIOI_CPUS (4)
32
-/* map to ipnum per 32 irqs */
33
-#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
34
-#define EXTIOI_IRQS_COREMAP_SIZE 256
35
-#define EXTIOI_IRQS_NODETYPE_COUNT 16
36
-#define EXTIOI_IRQS_GROUP_COUNT 8
37
-
38
-#define APIC_OFFSET 0x400
39
-#define APIC_BASE (0x1000ULL + APIC_OFFSET)
40
-
41
-#define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
42
-#define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
43
-#define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
44
-#define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
45
-#define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
46
-#define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
47
-#define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
48
-#define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
49
-#define EXTIOI_ISR_START (0x700 - APIC_OFFSET)
50
-#define EXTIOI_ISR_END (0x720 - APIC_OFFSET)
51
-#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET)
52
-#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
53
-#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
54
-#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
55
-#define EXTIOI_SIZE 0x800
56
-
57
-#define EXTIOI_VIRT_BASE (0x40000000)
58
-#define EXTIOI_VIRT_SIZE (0x1000)
59
-#define EXTIOI_VIRT_FEATURES (0x0)
60
-#define EXTIOI_HAS_VIRT_EXTENSION (0)
61
-#define EXTIOI_HAS_ENABLE_OPTION (1)
62
-#define EXTIOI_HAS_INT_ENCODE (2)
63
-#define EXTIOI_HAS_CPU_ENCODE (3)
64
-#define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \
65
- | BIT(EXTIOI_HAS_ENABLE_OPTION) \
66
- | BIT(EXTIOI_HAS_CPU_ENCODE))
67
-#define EXTIOI_VIRT_CONFIG (0x4)
68
-#define EXTIOI_ENABLE (1)
69
-#define EXTIOI_ENABLE_INT_ENCODE (2)
70
-#define EXTIOI_ENABLE_CPU_ENCODE (3)
71
-#define EXTIOI_VIRT_COREMAP_START (0x40)
72
-#define EXTIOI_VIRT_COREMAP_END (0x240)
73
+#include "hw/intc/loongarch_extioi_common.h"
74
75
typedef struct ExtIOICore {
76
uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
77
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
78
new file mode 100644
79
index XXXXXXX..XXXXXXX
80
--- /dev/null
81
+++ b/include/hw/intc/loongarch_extioi_common.h
82
@@ -XXX,XX +XXX,XX @@
83
+/* SPDX-License-Identifier: GPL-2.0-or-later */
84
+/*
85
+ * LoongArch 3A5000 ext interrupt controller definitions
86
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
87
+ */
88
+
89
+#ifndef LOONGARCH_EXTIOI_COMMON_H
90
+#define LOONGARCH_EXTIOI_COMMON_H
91
+
92
+#include "hw/sysbus.h"
93
+#include "hw/loongarch/virt.h"
94
+
95
+#define LS3A_INTC_IP 8
96
+#define EXTIOI_IRQS (256)
97
+#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
98
+/* irq from EXTIOI is routed to no more than 4 cpus */
99
+#define EXTIOI_CPUS (4)
100
+/* map to ipnum per 32 irqs */
101
+#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
102
+#define EXTIOI_IRQS_COREMAP_SIZE 256
103
+#define EXTIOI_IRQS_NODETYPE_COUNT 16
104
+#define EXTIOI_IRQS_GROUP_COUNT 8
105
+
106
+#define APIC_OFFSET 0x400
107
+#define APIC_BASE (0x1000ULL + APIC_OFFSET)
108
+#define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
109
+#define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
110
+#define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
111
+#define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
112
+#define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
113
+#define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
114
+#define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
115
+#define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
116
+#define EXTIOI_ISR_START (0x700 - APIC_OFFSET)
117
+#define EXTIOI_ISR_END (0x720 - APIC_OFFSET)
118
+#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET)
119
+#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
120
+#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
121
+#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
122
+#define EXTIOI_SIZE 0x800
123
+
124
+#define EXTIOI_VIRT_BASE (0x40000000)
125
+#define EXTIOI_VIRT_SIZE (0x1000)
126
+#define EXTIOI_VIRT_FEATURES (0x0)
127
+#define EXTIOI_HAS_VIRT_EXTENSION (0)
128
+#define EXTIOI_HAS_ENABLE_OPTION (1)
129
+#define EXTIOI_HAS_INT_ENCODE (2)
130
+#define EXTIOI_HAS_CPU_ENCODE (3)
131
+#define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \
132
+ | BIT(EXTIOI_HAS_ENABLE_OPTION) \
133
+ | BIT(EXTIOI_HAS_CPU_ENCODE))
134
+#define EXTIOI_VIRT_CONFIG (0x4)
135
+#define EXTIOI_ENABLE (1)
136
+#define EXTIOI_ENABLE_INT_ENCODE (2)
137
+#define EXTIOI_ENABLE_CPU_ENCODE (3)
138
+#define EXTIOI_VIRT_COREMAP_START (0x40)
139
+#define EXTIOI_VIRT_COREMAP_END (0x240)
140
+#endif /* LOONGARCH_EXTIOI_H */
23
--
141
--
24
2.34.1
142
2.43.5
25
26
diff view generated by jsdifflib
[PULL 5/7] target/loongarch: Avoid bits shift exceeding width of bool type
[PULL 10/18] include: Move struct LoongArchExtIOI to header file loongarch_extioi_common
1
From: Bibo Mao <maobibo@loongson.cn>
1
Move definiton of structure LoongArchExtIOI from header file loongarch_extioi.h
2
to file loongarch_extioi_common.h.
2
3
3
Variable env->cf[i] is defined as bool type, it is treated as int type
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
with shift operation. However the max possible width is 56 for the shift
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
5
operation, exceeding the width of int type. And there is existing api
6
---
6
read_fcc() which is converted to u64 type with bitwise shift, it can be
7
include/hw/intc/loongarch_extioi.h | 26 ----------------------
7
used to dump fp registers into coredump note segment.
8
include/hw/intc/loongarch_extioi_common.h | 27 +++++++++++++++++++++++
9
2 files changed, 27 insertions(+), 26 deletions(-)
8
10
9
Resolves: Coverity CID 1561133
11
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
10
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-Id: <20240914064645.2099169-1-maobibo@loongson.cn>
13
Signed-off-by: Song Gao <gaosong@loongson.cn>
14
---
15
target/loongarch/arch_dump.c | 6 +-----
16
1 file changed, 1 insertion(+), 5 deletions(-)
17
18
diff --git a/target/loongarch/arch_dump.c b/target/loongarch/arch_dump.c
19
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
20
--- a/target/loongarch/arch_dump.c
13
--- a/include/hw/intc/loongarch_extioi.h
21
+++ b/target/loongarch/arch_dump.c
14
+++ b/include/hw/intc/loongarch_extioi.h
22
@@ -XXX,XX +XXX,XX @@ static int loongarch_write_elf64_fprpreg(WriteCoreDumpFunction f,
15
@@ -XXX,XX +XXX,XX @@
23
16
24
loongarch_note_init(&note, s, "CORE", 5, NT_PRFPREG, sizeof(note.fpu));
17
#include "hw/intc/loongarch_extioi_common.h"
25
note.fpu.fcsr = cpu_to_dump64(s, env->fcsr0);
18
19
-typedef struct ExtIOICore {
20
- uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
21
- DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
22
- qemu_irq parent_irq[LS3A_INTC_IP];
23
-} ExtIOICore;
26
-
24
-
27
- for (i = 0; i < 8; i++) {
25
#define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
28
- note.fpu.fcc |= env->cf[i] << (8 * i);
26
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
29
- }
27
-struct LoongArchExtIOI {
30
- note.fpu.fcc = cpu_to_dump64(s, note.fpu.fcc);
28
- SysBusDevice parent_obj;
31
+ note.fpu.fcc = cpu_to_dump64(s, read_fcc(env));
29
- uint32_t num_cpu;
32
30
- uint32_t features;
33
for (i = 0; i < 32; ++i) {
31
- uint32_t status;
34
note.fpu.fpr[i] = cpu_to_dump64(s, env->fpr[i].vreg.UD[0]);
32
- /* hardware state */
33
- uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
34
- uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
35
- uint32_t isr[EXTIOI_IRQS / 32];
36
- uint32_t enable[EXTIOI_IRQS / 32];
37
- uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
38
- uint32_t coremap[EXTIOI_IRQS / 4];
39
- uint32_t sw_pending[EXTIOI_IRQS / 32];
40
- uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
41
- uint8_t sw_coremap[EXTIOI_IRQS];
42
- qemu_irq irq[EXTIOI_IRQS];
43
- ExtIOICore *cpu;
44
- MemoryRegion extioi_system_mem;
45
- MemoryRegion virt_extend;
46
-};
47
#endif /* LOONGARCH_EXTIOI_H */
48
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/intc/loongarch_extioi_common.h
51
+++ b/include/hw/intc/loongarch_extioi_common.h
52
@@ -XXX,XX +XXX,XX @@
53
#define EXTIOI_ENABLE_CPU_ENCODE (3)
54
#define EXTIOI_VIRT_COREMAP_START (0x40)
55
#define EXTIOI_VIRT_COREMAP_END (0x240)
56
+
57
+typedef struct ExtIOICore {
58
+ uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
59
+ DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
60
+ qemu_irq parent_irq[LS3A_INTC_IP];
61
+} ExtIOICore;
62
+
63
+struct LoongArchExtIOI {
64
+ SysBusDevice parent_obj;
65
+ uint32_t num_cpu;
66
+ uint32_t features;
67
+ uint32_t status;
68
+ /* hardware state */
69
+ uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
70
+ uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
71
+ uint32_t isr[EXTIOI_IRQS / 32];
72
+ uint32_t enable[EXTIOI_IRQS / 32];
73
+ uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
74
+ uint32_t coremap[EXTIOI_IRQS / 4];
75
+ uint32_t sw_pending[EXTIOI_IRQS / 32];
76
+ uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
77
+ uint8_t sw_coremap[EXTIOI_IRQS];
78
+ qemu_irq irq[EXTIOI_IRQS];
79
+ ExtIOICore *cpu;
80
+ MemoryRegion extioi_system_mem;
81
+ MemoryRegion virt_extend;
82
+};
83
#endif /* LOONGARCH_EXTIOI_H */
35
--
84
--
36
2.34.1
85
2.43.5
diff view generated by jsdifflib
[PULL 1/7] acpi: ged: Add macro for acpi sleep control register
[PULL 11/18] include: Rename LoongArchExtIOI with LoongArchExtIOICommonState
1
From: Bibo Mao <maobibo@loongson.cn>
1
Rename structure LoongArchExtIOI with LoongArchExtIOICommonState,
2
2
since it is defined in file loongarch_extioi_common.h
3
Macro definition is added for acpi sleep control register, ged emulation
4
driver can use the macro , also it can be used in FDT table if ged is
5
exposed with FDT table.
6
3
7
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
8
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
9
Message-Id: <20240918014206.2165821-2-maobibo@loongson.cn>
10
Signed-off-by: Song Gao <gaosong@loongson.cn>
11
---
6
---
12
hw/acpi/generic_event_device.c | 6 +++---
7
include/hw/intc/loongarch_extioi.h | 1 +
13
include/hw/acpi/generic_event_device.h | 7 +++++--
8
include/hw/intc/loongarch_extioi_common.h | 2 +-
14
2 files changed, 8 insertions(+), 5 deletions(-)
9
2 files changed, 2 insertions(+), 1 deletion(-)
15
10
16
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
11
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/acpi/generic_event_device.c
13
--- a/include/hw/intc/loongarch_extioi.h
19
+++ b/hw/acpi/generic_event_device.c
14
+++ b/include/hw/intc/loongarch_extioi.h
20
@@ -XXX,XX +XXX,XX @@ static void ged_regs_write(void *opaque, hwaddr addr, uint64_t data,
15
@@ -XXX,XX +XXX,XX @@
21
16
22
switch (addr) {
17
#include "hw/intc/loongarch_extioi_common.h"
23
case ACPI_GED_REG_SLEEP_CTL:
18
24
- slp_typ = (data >> 2) & 0x07;
19
+#define LoongArchExtIOI LoongArchExtIOICommonState
25
- slp_en = (data >> 5) & 0x01;
20
#define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
26
- if (slp_en && slp_typ == 5) {
21
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
27
+ slp_typ = (data >> ACPI_GED_SLP_TYP_POS) & ACPI_GED_SLP_TYP_MASK;
22
#endif /* LOONGARCH_EXTIOI_H */
28
+ slp_en = !!(data & ACPI_GED_SLP_EN);
23
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
29
+ if (slp_en && slp_typ == ACPI_GED_SLP_TYP_S5) {
30
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
31
}
32
return;
33
diff --git a/include/hw/acpi/generic_event_device.h b/include/hw/acpi/generic_event_device.h
34
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
35
--- a/include/hw/acpi/generic_event_device.h
25
--- a/include/hw/intc/loongarch_extioi_common.h
36
+++ b/include/hw/acpi/generic_event_device.h
26
+++ b/include/hw/intc/loongarch_extioi_common.h
37
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED)
27
@@ -XXX,XX +XXX,XX @@ typedef struct ExtIOICore {
38
/* ACPI_GED_REG_RESET value for reset*/
28
qemu_irq parent_irq[LS3A_INTC_IP];
39
#define ACPI_GED_RESET_VALUE 0x42
29
} ExtIOICore;
40
30
41
-/* ACPI_GED_REG_SLEEP_CTL.SLP_TYP value for S5 (aka poweroff) */
31
-struct LoongArchExtIOI {
42
-#define ACPI_GED_SLP_TYP_S5 0x05
32
+struct LoongArchExtIOICommonState {
43
+/* [ACPI 5.0 Chapter 4.8.3.7] Sleep Control and Status Register */
33
SysBusDevice parent_obj;
44
+#define ACPI_GED_SLP_TYP_POS 0x2 /* SLP_TYPx Bit Offset */
34
uint32_t num_cpu;
45
+#define ACPI_GED_SLP_TYP_MASK 0x07 /* SLP_TYPx 3-bit mask */
35
uint32_t features;
46
+#define ACPI_GED_SLP_TYP_S5 0x05 /* System _S5 State (Soft Off) */
47
+#define ACPI_GED_SLP_EN 0x20 /* SLP_EN write-only bit */
48
49
#define GED_DEVICE "GED"
50
#define AML_GED_EVT_REG "EREG"
51
--
36
--
52
2.34.1
37
2.43.5
diff view generated by jsdifflib
[PULL 7/7] hw/loongarch/fw_cfg: Build in common_ss[]
[PULL 12/18] hw/intc/loongarch_extioi: Rename LoongArchExtIOI with LoongArchExtIOICommonState
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
With some structure such as vmstate and property, rename LoongArchExtIOI
2
with LoongArchExtIOICommonState, these common structure will be moved
3
to common file.
2
4
3
Nothing in LoongArch fw_cfg.c requires target specific definitions.
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
hw/intc/loongarch_extioi.c | 41 +++++++++++++++++++++++---------------
9
1 file changed, 25 insertions(+), 16 deletions(-)
4
10
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
Message-Id: <20240927213254.17552-3-philmd@linaro.org>
8
Signed-off-by: Song Gao <gaosong@loongson.cn>
9
---
10
hw/loongarch/meson.build | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
12
13
diff --git a/hw/loongarch/meson.build b/hw/loongarch/meson.build
14
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/loongarch/meson.build
13
--- a/hw/intc/loongarch_extioi.c
16
+++ b/hw/loongarch/meson.build
14
+++ b/hw/intc/loongarch_extioi.c
17
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static int vmstate_extioi_post_load(void *opaque, int version_id)
18
loongarch_ss = ss.source_set()
16
return 0;
19
loongarch_ss.add(files(
17
}
20
- 'fw_cfg.c',
18
21
'boot.c',
19
+static int loongarch_extioi_common_post_load(void *opaque, int version_id)
22
))
20
+{
23
+common_ss.add(when: 'CONFIG_LOONGARCH_VIRT', if_true: files('fw_cfg.c'))
21
+ return vmstate_extioi_post_load(opaque, version_id);
24
loongarch_ss.add(when: 'CONFIG_LOONGARCH_VIRT', if_true: files('virt.c'))
22
+}
25
loongarch_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-build.c'))
23
+
24
static const VMStateDescription vmstate_extioi_core = {
25
.name = "extioi-core",
26
.version_id = 1,
27
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_extioi_core = {
28
};
29
30
static const VMStateDescription vmstate_loongarch_extioi = {
31
- .name = TYPE_LOONGARCH_EXTIOI,
32
+ .name = "loongarch.extioi",
33
.version_id = 3,
34
.minimum_version_id = 3,
35
- .post_load = vmstate_extioi_post_load,
36
+ .post_load = loongarch_extioi_common_post_load,
37
.fields = (const VMStateField[]) {
38
- VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
39
- VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
40
+ VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOICommonState,
41
+ EXTIOI_IRQS_GROUP_COUNT),
42
+ VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOICommonState,
43
EXTIOI_IRQS_NODETYPE_COUNT / 2),
44
- VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOI, EXTIOI_IRQS / 32),
45
- VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOI, EXTIOI_IRQS / 32),
46
- VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOI, EXTIOI_IRQS_IPMAP_SIZE / 4),
47
- VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOI, EXTIOI_IRQS / 4),
48
-
49
- VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOI, num_cpu,
50
- vmstate_extioi_core, ExtIOICore),
51
- VMSTATE_UINT32(features, LoongArchExtIOI),
52
- VMSTATE_UINT32(status, LoongArchExtIOI),
53
+ VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOICommonState,
54
+ EXTIOI_IRQS / 32),
55
+ VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOICommonState,
56
+ EXTIOI_IRQS / 32),
57
+ VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOICommonState,
58
+ EXTIOI_IRQS_IPMAP_SIZE / 4),
59
+ VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOICommonState,
60
+ EXTIOI_IRQS / 4),
61
+ VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOICommonState,
62
+ num_cpu, vmstate_extioi_core, ExtIOICore),
63
+ VMSTATE_UINT32(features, LoongArchExtIOICommonState),
64
+ VMSTATE_UINT32(status, LoongArchExtIOICommonState),
65
VMSTATE_END_OF_LIST()
66
}
67
};
68
69
static Property extioi_properties[] = {
70
- DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOI, num_cpu, 1),
71
- DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOI, features,
72
- EXTIOI_HAS_VIRT_EXTENSION, 0),
73
+ DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOICommonState, num_cpu, 1),
74
+ DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOICommonState,
75
+ features, EXTIOI_HAS_VIRT_EXTENSION, 0),
76
DEFINE_PROP_END_OF_LIST(),
77
};
26
78
27
--
79
--
28
2.34.1
80
2.43.5
29
30
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.