Fix secondary CPU reset for Xilinx Zynq 7000

[PATCH 0/2] Fix secondary CPU reset for Xilinx Zynq 7000

Sebastian Huber posted 2 patches 1 year, 4 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20240923035632.81304-1-sebastian.huber@embedded-brains.de

Maintainers: Peter Maydell <peter.maydell@linaro.org>, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Alistair Francis <alistair@alistair23.me>

hw/arm/boot.c        | 30 +++++++++++++++++++-----------
hw/arm/xilinx_zynq.c | 25 +++++++++++++++++++++++++
2 files changed, 44 insertions(+), 11 deletions(-)

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[PATCH 0/2] Fix secondary CPU reset for Xilinx Zynq 7000

Posted by Sebastian Huber 1 year, 4 months ago

I recently added the support for CPU1 to the xilinx-zynq-a9 machine
(hw/arm/xilinx_zynq.c). However, the reset behaviour doesn't match exactly with
the hardware. After a system reset (SRST), the CPU1 should execute a wfe
instruction and then load the start address from 0xfffffff0:

https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Starting-Code-on-CPU-1

Sebastian Huber (2):
  hw/arm/boot: Use hooks if PSCI is disabled
  hw/arm/xilinx_zynq: Add CPU1 reset

 hw/arm/boot.c        | 30 +++++++++++++++++++-----------
 hw/arm/xilinx_zynq.c | 25 +++++++++++++++++++++++++
 2 files changed, 44 insertions(+), 11 deletions(-)

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2.35.3