According to PLIC specification chapter 4, zeroth
priority register is reserved. Discard writes to
this register.

Signed-off-by: Sergey Makarov <s.makarov@syntacore.com>
---
 hw/intc/sifive_plic.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index e559f11805..3f3ee96ebc 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -189,8 +189,13 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
 
     if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
         uint32_t irq = (addr - plic->priority_base) >> 2;
-
-        if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
+        if (irq == 0) {
+            /* IRQ 0 source prioority is reserved */
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: Invalid source priority write 0x%"
+                          HWADDR_PRIx "\n", __func__, addr);
+            return;
+        } else if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
             /*
              * if "num_priorities + 1" is power-of-2, make each register bit of
              * interrupt priority WARL (Write-Any-Read-Legal). Just filter
-- 
2.34.1

On Thu, Sep 19, 2024 at 12:04 AM Sergey Makarov <s.makarov@syntacore.com> wrote:
>
> According to PLIC specification chapter 4, zeroth
> priority register is reserved. Discard writes to
> this register.
>
> Signed-off-by: Sergey Makarov <s.makarov@syntacore.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/intc/sifive_plic.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index e559f11805..3f3ee96ebc 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -189,8 +189,13 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
>
>      if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
>          uint32_t irq = (addr - plic->priority_base) >> 2;
> -
> -        if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
> +        if (irq == 0) {
> +            /* IRQ 0 source prioority is reserved */
> +            qemu_log_mask(LOG_GUEST_ERROR,
> +                          "%s: Invalid source priority write 0x%"
> +                          HWADDR_PRIx "\n", __func__, addr);
> +            return;
> +        } else if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
>              /*
>               * if "num_priorities + 1" is power-of-2, make each register bit of
>               * interrupt priority WARL (Write-Any-Read-Legal). Just filter
> --
> 2.34.1
>
>