riscv: hw/intc: Fixes for standard conformance

[PATCH 0/2] riscv: hw/intc: Fixes for standard conformance

Posted by Sergey Makarov 3 months, 1 week ago

*** Patchset goal ***

This patchset aims to improve standard conformance for SiFive PLIC
implementation.

*** Testing cases ***

Currently there are no automated tests for these changes, but there
are several test cases, with which these changes may be checked:
1. Zeroth priority register can be checked by reading it after
   writing to it. Without patch its value would be the same which
   is written there, but with it it would be zero;
2. Trigger call of `sifive_plic_irq_request` with level 0.
   Without second patch it will clear pending bit, but with it
   pending bit won't be cleared.
If anyone knows how this can be turned into automated test, help
would be appreciated.

Sergey Makarov (2):
  hw/intc: Make zeroth priority register read-only
  hw/intc: Don't clear pending bits on IRQ lowering

 hw/intc/sifive_plic.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

-- 
2.34.1

Re: [PATCH 0/2] riscv: hw/intc: Fixes for standard conformance

Posted by Alistair Francis 2 months, 3 weeks ago

On Thu, Sep 19, 2024 at 12:04 AM Sergey Makarov <s.makarov@syntacore.com> wrote:
>
> *** Patchset goal ***
>
> This patchset aims to improve standard conformance for SiFive PLIC
> implementation.
>
> *** Testing cases ***
>
> Currently there are no automated tests for these changes, but there
> are several test cases, with which these changes may be checked:
> 1. Zeroth priority register can be checked by reading it after
>    writing to it. Without patch its value would be the same which
>    is written there, but with it it would be zero;
> 2. Trigger call of `sifive_plic_irq_request` with level 0.
>    Without second patch it will clear pending bit, but with it
>    pending bit won't be cleared.
> If anyone knows how this can be turned into automated test, help
> would be appreciated.
>
> Sergey Makarov (2):
>   hw/intc: Make zeroth priority register read-only
>   hw/intc: Don't clear pending bits on IRQ lowering

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  hw/intc/sifive_plic.c | 15 +++++++++++----
>  1 file changed, 11 insertions(+), 4 deletions(-)
>
> --
> 2.34.1
>
>