target/arm: Correct ID_AA64ISAR1_EL1 value for neoverse-v1

[PATCH] target/arm: Correct ID_AA64ISAR1_EL1 value for neoverse-v1

Posted by Peter Maydell 1 year, 2 months ago

The Neoverse-V1 TRM is a bit confused about the layout of the
ID_AA64ISAR1_EL1 register, and so its table 3-6 has the wrong value
for this ID register.  Trust instead section 3.2.74's list of which
fields are set.

This means that we stop incorrectly reporting FEAT_XS as present, and
now report the presence of FEAT_BF16.

Cc: qemu-stable@nongnu.org
Reported-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/cpu64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index b9f34f044d0..01689208286 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -677,7 +677,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
     cpu->isar.id_aa64dfr0  = 0x000001f210305519ull;
     cpu->isar.id_aa64dfr1 = 0x00000000;
     cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */
-    cpu->isar.id_aa64isar1 = 0x0111000001211032ull;
+    cpu->isar.id_aa64isar1 = 0x0011100001211032ull;
     cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
     cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
     cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull;
-- 
2.34.1

Re: [PATCH] target/arm: Correct ID_AA64ISAR1_EL1 value for neoverse-v1

Posted by Marcin Juszkiewicz 1 year, 1 month ago

W dniu 17.09.2024 o 18:13, Peter Maydell pisze:
> The Neoverse-V1 TRM is a bit confused about the layout of the
> ID_AA64ISAR1_EL1 register, and so its table 3-6 has the wrong value
> for this ID register.  Trust instead section 3.2.74's list of which
> fields are set.
> 
> This means that we stop incorrectly reporting FEAT_XS as present, and
> now report the presence of FEAT_BF16.
> 
> Cc: qemu-stable@nongnu.org
> Reported-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   target/arm/tcg/cpu64.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index b9f34f044d0..01689208286 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -677,7 +677,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
>       cpu->isar.id_aa64dfr0  = 0x000001f210305519ull;
>       cpu->isar.id_aa64dfr1 = 0x00000000;
>       cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */
> -    cpu->isar.id_aa64isar1 = 0x0111000001211032ull;
> +    cpu->isar.id_aa64isar1 = 0x0011100001211032ull;
>       cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
>       cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
>       cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull;

I think that it would nice to have it backported to stable branches. It 
applies to stable-8.1 and above.

In master it is 8676007eff04bb4e454bcdf92fab3f855bcc59b3 commit.

Re: [PATCH] target/arm: Correct ID_AA64ISAR1_EL1 value for neoverse-v1

Posted by Michael Tokarev 1 year, 1 month ago

On 20.09.2024 11:10, Marcin Juszkiewicz wrote:
> W dniu 17.09.2024 o 18:13, Peter Maydell pisze:
>> The Neoverse-V1 TRM is a bit confused about the layout of the
>> ID_AA64ISAR1_EL1 register, and so its table 3-6 has the wrong value
>> for this ID register.  Trust instead section 3.2.74's list of which
>> fields are set.
>>
>> This means that we stop incorrectly reporting FEAT_XS as present, and
>> now report the presence of FEAT_BF16.
>>
>> Cc: qemu-stable@nongnu.org
...

> I think that it would nice to have it backported to stable branches. It 
> applies to stable-8.1 and above.

Since it has Cc: qemu-stable@, I already picked it up for 8.2, 9.0 and
9.1.

> In master it is 8676007eff04bb4e454bcdf92fab3f855bcc59b3 commit.

Thank you!

/mjt

Re: [PATCH] target/arm: Correct ID_AA64ISAR1_EL1 value for neoverse-v1

Posted by Richard Henderson 1 year, 2 months ago

On 9/17/24 18:13, Peter Maydell wrote:
> The Neoverse-V1 TRM is a bit confused about the layout of the
> ID_AA64ISAR1_EL1 register, and so its table 3-6 has the wrong value
> for this ID register.  Trust instead section 3.2.74's list of which
> fields are set.
> 
> This means that we stop incorrectly reporting FEAT_XS as present, and
> now report the presence of FEAT_BF16.
> 
> Cc:qemu-stable@nongnu.org
> Reported-by: Marcin Juszkiewicz<marcin.juszkiewicz@linaro.org>
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
>   target/arm/tcg/cpu64.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~